CN220692004U

CN220692004U - Chip packaging structure

Info

Publication number: CN220692004U
Application number: CN202322360014.1U
Authority: CN
Inventors: 洪胜平; 林红宽; 周斌; 余财祥; 彭燕君
Original assignee: Vanchip Tianjin Electronic Technology Co Ltd
Current assignee: Vanchip Tianjin Electronic Technology Co Ltd
Priority date: 2023-08-31
Filing date: 2023-08-31
Publication date: 2024-03-29
Anticipated expiration: 2033-08-31

Abstract

The utility model provides a chip packaging structure, which comprises: the filter chip mounting area of the substrate is provided with a metal bonding pad; the metal solder layer is fixed on the metal bonding pad; the filter chip comprises a filter chip body and a metal shielding layer, wherein the front surface of the filter chip body is provided with a plurality of first salient points, the front surface of the filter chip body is attached to a substrate, the metal shielding layer at least covers the side surface of the filter chip body, and the metal shielding layer, the metal welding material layer and the metal welding pad are mutually connected, so that a sealed cavity is formed by surrounding the filter chip, the metal welding material layer and the substrate; and the plastic layer is positioned on the substrate and is used for embedding the filter chip. According to the utility model, the filter chip, the metal solder layer and the substrate are surrounded to form the sealed cavity, so that plastic packaging materials can be prevented from entering the sealed cavity in the packaging process, and further, the problem of failure of the filter chip caused by filling of the sealed cavity can be avoided.

Description

Chip packaging structure

Technical Field

The present disclosure relates to chip packaging technology, and in particular, to a chip packaging structure.

Background

The acoustic surface filter has the advantages of small volume and good performance, and is widely applied to various electronic devices. The sound surface filter works on the principle that sound waves are transmitted on the surface of the chip. The packaging of the acoustic surface filter must ensure that the interdigital transducer surface cannot contact other substances, i.e., that the chip surface is of a cavity structure, otherwise affecting signal transmission.

In the prior art, all chips (filter chips and non-filter chips) in a module are packaged in a film coating mode, a cavity is formed at the bottom of the chip, the film coating is easy to break in the injection molding process, so that the bottom of the filter chip is filled to cause failure, and in addition, the risk of incomplete filling caused by insufficient film breaking exists in the non-filter chip.

Disclosure of Invention

The utility model aims to provide a chip packaging structure so as to form a sealed cavity between a filter chip, a metal solder layer and a substrate, and avoid the problem that a plastic packaging material enters the sealed cavity in the packaging process, so that the filter chip is invalid due to the fact that the sealed cavity is filled.

To achieve the above and other related objects, the present utility model also provides a chip package structure, comprising:

the filter chip mounting device comprises a substrate, wherein a metal bonding pad is arranged at the edge of a filter chip mounting area of the substrate, and the filter chip mounting area is an area for mounting a filter chip on the substrate;

a metal solder layer fixed on the metal pad;

the filter chip comprises a filter chip body and a metal shielding layer, wherein the filter chip body is provided with a front surface and a back surface, the front surface of the filter chip body is provided with a plurality of first protruding points, the front surface of the filter chip body is attached to a filter chip attaching region of the substrate, the metal shielding layer at least covers the side surface of the filter chip body, the metal shielding layer, the metal welding material layer and the metal welding pad are mutually connected, and a sealed cavity is formed by enclosing the filter chip, the metal welding material layer and the substrate;

and the plastic layer is positioned on the substrate and is used for embedding the filter chip.

Optionally, in the chip packaging structure, the metal shielding layer covers the back surface and the side surface of the filter chip body, and the thickness of the metal shielding layer on the back surface of the filter chip body is greater than 3 μm.

Optionally, in the chip packaging structure, the chip packaging structure further includes a non-filter chip, the non-filter chip includes a front surface and a back surface, the front surface of the non-filter chip is provided with a plurality of second bumps, the front surface of the non-filter chip is attached to the substrate, and the plastic sealing layer further embeds the non-filter chip and fills a cavity formed between the non-filter chip and the substrate.

Optionally, in the chip packaging structure, the number of the second bumps is a plurality of second bumps.

Optionally, in the chip packaging structure, the filter chip and the non-filter chip are mounted on the substrate at intervals.

Optionally, in the chip packaging structure, the metal pad on the substrate is annular.

Optionally, in the chip packaging structure, the metal solder layer is annular.

Optionally, in the chip packaging structure, the height of the metal pad is equal to the height of the first bump.

Optionally, in the chip packaging structure, the number of the first bumps is a plurality of bumps.

Compared with the prior art, the technical scheme of the utility model has the following beneficial effects:

in the chip packaging structure, a metal shielding layer is arranged on the side surface of a filter chip; the edge of the filter chip mounting area of the substrate is provided with a metal bonding pad; a metal solder layer is arranged on a metal bonding pad of the substrate; and the metal shielding layer, the metal solder layer and the bonding pad are interconnected, a sealed cavity can be formed among the filter chip, the metal solder layer and the substrate (namely, the cavity at the bottom of the filter chip is the sealed cavity), and the problem that the filter chip fails due to the fact that the cavity at the bottom is filled can be avoided because plastic packaging materials enter the sealed cavity in the packaging process.

And secondly, the non-filter chip is mounted on the substrate, and the plastic packaging material can completely fill the cavity at the bottom of the non-filter chip in the packaging process, so as to provide protection for the second salient point of the non-filter chip.

In addition, the side surface and the back surface of the filter chip can be provided with the metal shielding layers, and the metal shielding layers, the metal welding material layers and the substrate form the shielding cover of the filter chip body, so that the filter chip body can be prevented from generating electromagnetic interference to other chips.

Drawings

FIG. 1 is a cross-sectional view of a chip package structure according to an embodiment of the utility model;

FIG. 2 is a top view of a chip package structure according to an embodiment of the utility model;

FIG. 3 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present utility model;

fig. 4 is a cross-sectional view of a product after performing step S1 in the manufacturing method of the chip package structure of the present utility model;

fig. 5 is a cross-sectional view of a product after performing step S2 in the manufacturing method of the chip package structure of the present utility model;

fig. 6 is a cross-sectional view of a product after step S31 is performed in the manufacturing method of the chip package structure of the present utility model;

fig. 7 is a cross-sectional view of a product after step S32 is performed in the manufacturing method of the chip package structure of the present utility model;

fig. 8 is a cross-sectional view of a product after performing step S4 in the manufacturing method of the chip package structure of the present utility model;

fig. 9 is a cross-sectional view of a product after step S5 is performed in the manufacturing method of the chip package structure of the present utility model.

Detailed Description

The chip package structure according to the present utility model will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present utility model will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model.

In the prior art, a filter chip and a non-filter chip in a module are packaged in a film coating mode, a cavity is formed at the bottom of the chip, the film coating is easy to break in the injection molding process, so that the bottom of the filter chip is filled to cause failure, and in addition, the risk of incomplete filling caused by insufficient film breaking exists in the non-filter chip.

In order to solve the problem that a cavity at the bottom of a filter chip fails due to filling, the utility model provides a chip packaging structure. Referring to fig. 1 and 2, the chip package structure provided by the present utility model includes:

a substrate 10, wherein a metal pad 101 is arranged at the edge of a filter chip mounting area of the substrate 10, and the filter chip mounting area is an area on the substrate 10 for mounting a filter chip;

a metal solder layer 20 fixed on the metal pad 101;

the filter chip comprises a filter chip body 301 and a metal shielding layer 302, wherein the filter chip body 301 is provided with a front surface and a back surface, the front surface of the filter chip body 301 is provided with a plurality of first protruding points 3011, the front surface of the filter chip body 301 is attached to a filter chip attaching region of the substrate 10, the metal shielding layer 302 at least covers the side surface of the filter chip body 301, the metal shielding layer 302, the metal solder layer 20 and the metal bonding pad 101 are interconnected, and a sealed cavity is formed by surrounding the filter chip, the metal solder layer 20 and the substrate 10;

a plastic layer 60 on the substrate 10 and embedding the filter chip.

In this embodiment, the substrate 10 is mainly used for carrying a chip, and a circuit layer may be disposed inside the substrate. A metal pad 101 is provided on the substrate 10, and the metal pad 101 is provided at an edge of a filter chip mounting region on the substrate 10. In this embodiment, the metal pad 101 is preferably electrically connected to the wiring layer of the substrate 10. The filter chip mounting area of the present embodiment is an area for mounting a filter chip on the substrate 10.

The metal pad 101 is preferably in a ring structure, and the height of the metal pad 101 may be less than or equal to the height of the first bump 3011, and further, the height of the metal pad 101 is preferably the same as the height of the first bump 3011, so that the metal pad 101 may be in contact with the metal shielding layer 302 while the first bump 3011 is in contact with the substrate 10. In this embodiment, only the bottom of the metal shielding layer 302 may be located on the metal pad 101, or the bottom of the metal shielding layer 302 and the edge area of the front surface of the filter chip body 301 may be located on the metal pad 101 at the same time. The edge area of the front surface of the filter chip body 301 is smaller than the area from the first salient point 3011 at the outermost side of the filter chip body 301 to the side edge of the filter chip body 301, and the edge area of the front surface of the filter chip body 301 does not contain the first salient point 3011. In the present embodiment, the material of the metal solder layer 20 is preferably metal, but is not limited thereto. The material of the metal solder layer 20 is further preferably a metal with shielding effect, such as copper.

The metal solder layer 20 is located on the metal pad 101. In this embodiment, the metal solder layer 20 is preferably in a ring structure, and the width of the metal solder layer 20 is preferably less than or equal to the width of the metal pad 101. Further, the width of the metal solder layer 20 is preferably smaller than the width of the metal pad 101, so that the bottom of the metal shielding layer 302 and the edge area of the front surface of the filter chip body 301 may be located on the metal pad 101. In the present embodiment, the material of the metal solder layer 20 is preferably metal, but is not limited thereto. Further, the material of the metal solder layer 20 is preferably a metal with shielding effect, such as copper. Still further, the material of the metal solder layer 20 is preferably the same as that of the metal pad 101.

In this embodiment, although the metal pad 101 may contact the metal shielding layer 302 while the first bump 3011 contacts the substrate 10, in actual operation, due to a process error, while the first bump 3011 contacts the substrate 10, the metal pad 101 is difficult to completely contact the metal shielding layer 302, and a tiny gap may exist between the metal pad 101 and the metal shielding layer 302, so that molding compound may enter the sealed cavity 40 during the encapsulation process. In this embodiment, due to the arrangement of the metal solder layer 20, which is fixedly connected with the side surface of the metal shielding layer 302 and the metal bonding pad respectively, a tiny gap may exist between the metal bonding pad 101 and the metal shielding layer 302 to seal the metal bonding pad completely, so that the formed sealed cavity 40 may be prevented from being filled with the molding compound, that is, the metal solder layer 20 may ensure that the sealed space 40 is formed completely.

The filter chip is mounted on the filter chip mounting area of the substrate 10, and the filter chip, the metal solder layer 20 and the substrate 10 enclose a sealed cavity 40. In this embodiment, the filter chip includes a filter chip body 301 and a metal shielding layer 20. The filter chip body 301 has a front surface and a back surface, and the front surface is provided with a plurality of first bumps 3011. In this embodiment, the number of the first bumps 3011 is preferably plural.

The metal shielding layer 302 covers at least the side face of the filter chip body 301. Specifically, the metal shielding layer 302 may cover only the side surface of the filter chip body 301, or may cover both the side surface and the back surface of the filter chip body 301. Preferably, the metal shielding layer 302 covers both the side surface and the back surface of the filter chip body 301, so that not only the sealed cavity 40 can be formed, but also a shielding cover of the filter chip body 301 can be formed together with the metal solder layer 20 and the substrate 10, and electromagnetic interference of the filter chip body 301 to other chips can be avoided. The thickness of the metal shielding layer 302 on the back surface of the filter chip body 301 in this embodiment is preferably greater than 3 μm, and the thickness (width) of the metal shielding layer 302 on the side surface of the filter chip body 301 may also be greater than 3 μm, so that the sealing effect of the finally formed sealed cavity 40 and the electromagnetic shielding effect of the shielding case are better.

The chip package structure of the present embodiment may further include a non-filter chip 50. The non-filter chip 50 may be a conventional electronic component that can operate without a cavity, such as an antenna switch, a low noise amplifier, a capacitor, an inductor, etc. The non-filter chip 50 includes a front surface and a back surface, and the front surface is provided with a plurality of second bumps 501. In this embodiment, the number of the second bumps 501 is preferably a plurality, and the height of the second bumps 501 may be the same as or different from the height of the first bumps 3011. The front surface of the non-filter chip 50 is mounted on the substrate 10, and specifically, the front surface (the second bump 501) of the non-filter chip 50 is fixed to the non-filter chip mounting area of the substrate 10. In this embodiment, the filter chip is required to be mounted on the substrate 10 at a distance from the non-filter chip 50, and the surface of the first bump 3011 facing the substrate 10 is coplanar with the surface of the second bump 501 facing the substrate 10.

The plastic layer 60 is disposed on the substrate 10 and embeds the filter chip, and the plastic layer 60 also embeds the non-filter chip 50 and fills the cavity formed between the non-filter chip 50 (specifically, the bottom of the non-filter chip 50) and the substrate 10, that is, the non-sealed cavity 70. The plastic layer 60 may be made of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. In this embodiment, the surface of the first bump 3011 facing the substrate 10, the surface of the second bump 501 facing the substrate 10, and the surface of the molding layer 60 facing the substrate 10 are coplanar. Since the cavity at the bottom of the filter chip 301 (i.e. the sealed cavity 40) is sealed, the molding compound cannot enter the cavity during the packaging process; while the cavity at the bottom of the non-filter chip 50 (i.e., non-sealed cavity 70) is non-sealed, so that the molding compound will completely fill the cavity during the encapsulation process.

Compared with the prior art, the embodiment not only can avoid the sealing cavity 40 at the bottom of the filter chip to be filled with the plastic package material, but also can avoid the filling problem caused by incomplete membrane rupture of the non-filter chip because the embodiment does not have a membrane covering process, and the cavity at the bottom of the non-filter chip 50 can be completely filled.

Referring to fig. 3, the method for manufacturing the chip package structure may include the following steps:

step S1: providing a substrate 10, wherein a metal bonding pad 101 is arranged at the edge of a filter chip mounting area of the substrate 10, and the filter chip mounting area is an area for mounting a filter chip on the substrate 10;

step S2: fixing a metal solder layer 20 on the metal pad 101;

step S3: providing a filter chip, wherein the filter chip comprises a filter chip body 301 and a metal shielding layer 302, the filter chip body 301 is provided with a front surface and a back surface, the front surface is provided with a plurality of first protruding points 3011, the metal shielding layer 302 at least covers the side surface of the filter chip body 301, and the front surface of the filter chip body is attached to a filter chip attaching area of the substrate;

step S4: interconnecting the metal shielding layer 302, the metal solder layer 20 and the metal bonding pad 101, so that a sealed cavity is formed by surrounding the filter chip, the metal solder layer 20 and the substrate 10;

step S5: the filter chip is encapsulated to form an encapsulation layer 60 embedding the filter chip.

Referring to fig. 4, step S1 is performed to provide a substrate 10. In this embodiment, the substrate 10 is mainly used for carrying a chip, and a circuit layer may be disposed inside the substrate. The metal pad 101 is disposed on the substrate 10 in the present embodiment, and the metal solder layer 20 may be formed on the substrate 10 by electroplating, a substrate process, a printing process, or the like in the present embodiment. The material of the metal solder layer 20 is preferably metal, but is not limited thereto. Further, the material of the metal solder layer 20 is preferably a metal with shielding effect, such as copper. The metal pad 101 is disposed at an edge of the filter chip mounting area on the substrate 10 so that the metal pad 101 can be in contact with the metal shielding layer 302 and an edge area of the front surface of the filter chip body 301. The metal pad 101 is preferably in a ring structure, and the metal pad 101 is preferably the same as the first bump 3011 in height, so that the metal pad 101 may contact the metal shielding layer 302 and the edge region of the front surface of the filter chip body 301 while the first bump 3011 contacts the substrate 10.

Referring to fig. 5, step S2 is performed to form the metal solder layer 20. The forming process of the metal solder layer 20 of the present embodiment is preferably a printing process, but is not limited thereto. The metal solder layer 20 is preferably in a ring structure and is located on the metal pad 101. The material of the metal solder layer 20 is preferably metal, but is not limited thereto. Further, the material of the metal solder layer 20 is preferably a metal with shielding effect, such as copper. Further, the material of the metal solder layer 20 is preferably the same as that of the metal pad 101, and the forming process of the metal solder layer 20 is preferably the same as that of the metal pad 101, so that the metal solder layer 20 and the metal pad 101 can be completed in one process step to simplify the process. In other embodiments, the material and forming process of the metal solder layer 20 are the same as those of the metal pad 101, and may be completed in different process steps.

In this embodiment, the width of the metal solder layer 20 is preferably less than or equal to the width of the metal pad 101. Further, the width of the metal solder layer 20 is preferably smaller than the width of the metal pad 101, so that the side bottom of the metal shielding layer 302 and the edge area of the front surface of the filter chip body 301 may be located on the metal solder layer 20.

Referring to fig. 6 to 8, step S3 is performed to provide a filter chip, and the filter chip is mounted on the substrate 10. The filter chip comprises a filter chip body 301 and a metal shielding layer 302, and the preparation method of the filter chip can comprise the following steps:

step S31: providing a filter chip body 301 with a plurality of first bumps 3011 on the front surface;

step S32: at least the metal shielding layer 302 is formed on the side surface of the filter chip body 301 by using a sputtering process.

Referring to fig. 6, step S31 is performed to provide the filter chip body 301. The filter chip body 301 is mounted on the substrate 10 using first bumps 3011, the first bumps 3011 may be formed of a material such as metal or solder, and the number of the first bumps 3011 is preferably plural.

Referring to fig. 7, step S32 is performed to form the metal shielding layer 302. In the present embodiment, the metal shielding layer 302 is preferably formed using a sputtering process, but is not limited thereto. In this embodiment, the metal shielding layer 302 may be formed only on the side surface of the filter chip body 301, or may be formed on both the side surface and the back surface of the filter chip body 301. Preferably, the metal shielding layer 302 covers both the side and the back of the filter chip body 301, so that not only the sealed cavity 40 can be formed, but also a shielding case of the filter chip body 301 can be formed together with the metal solder layer 20, the substrate (the metal pad 101 and the circuit layer), so that electromagnetic interference of the filter chip body 301 to other chips can be avoided. The thickness of the metal shielding layer 302 on the back surface of the filter chip body 301 of this embodiment is preferably greater than 3 μm, and the thickness of the metal shielding layer 302 on the side surface of the filter chip body 301 may be greater than 3 μm.

Referring to fig. 8, the front surface of the filter chip body 301 is fixed toward the substrate 10, and specifically, the first bump 3011 of the filter chip body 301 may be flip-chip bonded to the substrate 10.

With continued reference to fig. 8, in this embodiment, in step S3, the method for manufacturing the chip package structure may further include: a non-filter chip 50 is provided, and the non-filter chip 50 is mounted on the substrate 10, wherein the non-filter chip 50 comprises a front surface and a back surface, the front surface is provided with a plurality of second bumps 501, and the front surface of the non-filter chip 50 is mounted on the substrate 10. The second bump 202 of the non-filter chip body 301 of the present embodiment may be flip-chip bonded to the substrate 10.

With continued reference to fig. 8, step S4 is performed to implement interconnection among the metal shielding layer 302, the metal solder layer 20 and the metal pad 101 by using a reflow soldering method. In this embodiment, the metal solder layer 20 is transformed into liquid during the reflow soldering process, and part of the liquid climbs along the side surface of the metal shielding layer 302, so that after the reflow soldering, the shape of the metal solder layer 20 is changed, and the metal solder layer 20 and the side surface of the metal shielding layer 302 are fixed together. The metal shielding layer 302 on the side of the filter chip body 301 of the present embodiment may form the sealed cavity 40 by being soldered and interconnected with the metal solder layer 20 and the metal pad 101, and the metal shielding layer 302 on the back and side of the filter chip body may form the shielding case by being soldered and interconnected with the metal solder layer 20 and the metal pad 101.

Referring to fig. 9, step S5 is performed to form a molding layer 60. The plastic packaging process is a mature process in the packaging industry, and the principle is that a plastic packaging material is plastic-packaged on a substrate containing a chip through a plastic packaging machine, so that the chip is protected, and the plastic packaging process has the advantages of being good in surface flatness, high in hardness, good in heat resistance, good in reliability, low in cost and the like. In this embodiment, the plastic sealing layer 60 may encapsulate the filter chip and the non-filter chip 50 at the same time. That is, the non-filter chip 50 may be further encapsulated at the same time as the filter chip is encapsulated, so that the encapsulation layer 60 further encapsulates the non-filter chip 50 and fills the cavity between the non-filter chip 50 and the substrate 10. Since the cavity at the bottom of the filter chip 301 (i.e. the sealed cavity 40) is sealed, the molding compound cannot enter the cavity during the packaging process; while the cavity at the bottom of the non-filter chip 50 (non-sealed cavity 70) is non-sealed, so that the molding compound fills the cavity completely during the packaging process, protecting the second bump 302. Compared with the prior art, the embodiment not only can avoid the sealing cavity 40 at the bottom of the filter chip to be filled with the plastic package material, but also can completely fill the cavity at the bottom of the non-filter chip 50 because the non-filter chip has no filling problem caused by incomplete membrane rupture because the embodiment has no membrane covering process.

In summary, the utility model is characterized in that the side surface of the filter chip body is provided with a metal shielding layer; a metal bonding pad is arranged at the edge of the filter chip mounting area on the substrate; and arranging a metal solder layer on the metal bonding pad of the substrate, and interconnecting the metal shielding layer, the metal solder layer and the metal bonding pad to form a sealed cavity.

In addition, the metal shielding layers can be arranged on the side surface and the back surface of the filter chip, and after reflow soldering, the metal shielding layers, the metal solder layers and the substrate form the shielding cover of the filter chip body, so that the filter chip body can be prevented from generating electromagnetic interference to other chips.

In addition, it will be understood that while the utility model has been described in terms of preferred embodiments, the above embodiments are not intended to limit the utility model. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present utility model still fall within the scope of the technical solution of the present utility model.

It is also to be understood that this utility model is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may vary. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present utility model. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood as having the definition of a logical "or" rather than a logical exclusive or "unless the context clearly indicates the contrary. Structures described herein will be understood to also refer to the functional equivalents of such structures. Language that may be construed as approximate should be construed unless the context clearly indicates the contrary.

Claims

1. A chip package structure, comprising:

a metal solder layer fixed on the metal pad;

2. The chip package structure of claim 1, wherein the metal shielding layer covers the back surface and the side surface of the filter chip body, and the thickness of the metal shielding layer on the back surface of the filter chip body is greater than 3 μm.

3. The chip package structure of claim 1, further comprising a non-filter chip, the non-filter chip comprising a front side and a back side, the front side of the non-filter chip having a plurality of second bumps, the front side of the non-filter chip being attached to the substrate, the molding layer further embedding the non-filter chip and filling a cavity formed between the non-filter chip and the substrate.

4. The chip package structure of claim 3, wherein the number of the second bumps is a plurality.

5. The chip package structure of claim 3, wherein the filter chip is mounted on the substrate spaced apart from the non-filter chip.

6. The chip package structure of claim 1, wherein the metal pads on the substrate are ring-shaped.

7. The chip package structure of claim 1, wherein the metal solder layer is ring-shaped.

8. The chip package structure of claim 1, wherein a height of the metal pad is equal to a height of the first bump.

9. The chip package structure of claim 1, wherein the number of first bumps is a plurality.