KR100364979B1 - Semiconductor device its manufacturing method - Google Patents
Semiconductor device its manufacturing method Download PDFInfo
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- KR100364979B1 KR100364979B1 KR1019990020942A KR19990020942A KR100364979B1 KR 100364979 B1 KR100364979 B1 KR 100364979B1 KR 1019990020942 A KR1019990020942 A KR 1019990020942A KR 19990020942 A KR19990020942 A KR 19990020942A KR 100364979 B1 KR100364979 B1 KR 100364979B1
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- semiconductor chip
- pcb substrate
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- semiconductor
- flip chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000003822 epoxy resin Substances 0.000 claims abstract description 18
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 230000008054 signal transmission Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 두 개의 반도체칩이 플립 칩 본딩에 의해 적층되도록 실장된 반도체칩을 PCB 기판에 플립 칩 본딩하여서 이루어지는 반도체 장치로서, 상기 PCB 기판에 실장되는 플립 칩 본딩부와, 상기 두 개의 반도체칩이 적층되도록 실장된 플립 칩 본딩부를 에폭시 수지로 한번 디스펜싱하는 것에 의해 동시에 봉지될 수 있도록 하는 것이 특징이며, 따라서 제조 공정을 간소화할 수 있어 생산성을 높이고, 또 디스펜싱에 의한 불량을 방지하여 신뢰성을 향상시킬 수 있도록 된 것이다.The present invention is a semiconductor device formed by flip chip bonding a semiconductor chip mounted so that two semiconductor chips are stacked by flip chip bonding on a PCB substrate, the flip chip bonding portion mounted on the PCB substrate, and the two semiconductor chips It is characterized in that the flip chip bonding portion mounted to be stacked can be encapsulated at the same time by dispensing with epoxy resin once, thus simplifying the manufacturing process, increasing productivity and preventing defects caused by dispensing to improve reliability. It is to improve.
Description
본 발명은 반도체 징치 및 그 제조방법에 관한 것으로, 더욱 상세하게는 두 개의 반도체칩이 플립 칩 본딩에 의해 적층되도록 실장된 반도체칩을 PCB 기판에 플립 칩 본딩하여서 이루어지는 반도체 장치로서, 상기 PCB 기판에 실장되는 플립 칩 본딩부와, 상기 두 개의 반도체칩이 적층되도록 실장된 플립 칩 본딩부를 에폭시 수지로 한번 디스펜싱하는 것에 의해 동시에 봉지될 수 있도록 하는 것이 특징이며, 따라서 제조 공정을 간소화하여 생상성을 높일 수 있고, 또 에폭시 디스펜싱에 의한 불량을 방지하여 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device formed by flip chip bonding a semiconductor chip mounted so that two semiconductor chips are stacked by flip chip bonding. The flip chip bonding portion to be mounted and the flip chip bonding portion mounted to stack the two semiconductor chips can be simultaneously encapsulated by dispensing with epoxy resin, thus simplifying the manufacturing process to increase productivity. In addition, it is possible to prevent defects caused by epoxy dispensing and to improve reliability.
최근에 다핀화의 추세에 따른 기술적 요구를 해결하기 위해서 등장한 볼 그리드 어레이(Ball Grid Array ; BGA) 반도체 패키지는 입출력 수단으로서 반도체 패키지의 일면에 솔더볼을 융착하여 이를 입출력 수단으로 사용함으로서 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 작게 형성된 것이다.In recent years, the Ball Grid Array (BGA) semiconductor package, which has emerged to solve the technical demands of the multi-pinning trend, is used as an input / output means by soldering solder balls to one surface of the semiconductor package and using it as an input / output means. In addition to being able to accept the signal, the size is also formed small.
이러한 볼 그리드 어레이 반도체 패키지의 구성은, 도 1에 도시된 바와 같이 회로패턴(2')이 형성되고, 이 회로패턴(2')을 보호하기 위해 커버코트(2")가 코팅된 PCB 기판(2)과, 상기 PCB 기판(2)의 일면 중앙에 부착된 반도체칩(1)과, 상기 반도체칩(1)과 상기 PCB 기판(2)의 회로패턴(2')을 전기적으로 연결하여 신호를 전달하는 와이어(3)와, 상기 PCB 기판(2)의 회로패턴(2')과 연결되어 외부로 신호를 전달할 수 있도록 PCB 기판(2)의 저면에 융착된 솔더볼(4)과, 상기 반도체칩(1)과 그 외 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 상기 PCB 기판(2)의 상면을 감싼 봉지재(5)로 구성된다.The ball grid array semiconductor package includes a PCB substrate having a circuit pattern 2 'formed thereon and having a cover coat 2 " coated thereon to protect the circuit pattern 2' as shown in FIG. 2), the semiconductor chip 1 attached to the center of one surface of the PCB substrate 2 and the circuit pattern 2 'of the semiconductor chip 1 and the PCB substrate 2 are electrically connected to provide a signal. A solder ball 4 fused to a bottom surface of the PCB board 2 so as to transmit a signal to the wire 3 to be transmitted, the circuit pattern 2 'of the PCB board 2 to transmit a signal to the outside, and the semiconductor chip It consists of an encapsulant 5 wrapping the upper surface of the PCB substrate 2 in order to protect (1) and other peripheral components from external oxidation and corrosion.
그러나, 이러한 볼 그리드 어레이 반도체 패키지는 내부에 하나의반도체칩(1)이 실장되어 있어 반도체 패키지의 용량을 확대하기 위해서는, 하나 이상의 볼 그리드 어레이 반도체 패키지를 마더보드에 실장하여야 그 용량을 확대시킬 수 있다.However, such a ball grid array semiconductor package has one semiconductor chip 1 mounted therein, and thus, in order to increase the capacity of the semiconductor package, at least one ball grid array semiconductor package must be mounted on a motherboard to increase its capacity. have.
따라서, 상기와 같이 하나 이상의 볼 그리드 어레이 반도체 패키지를 마더보드에 실장 할 경우에는 마더보드의 표면에 각각 실장하여야 됨으로서 실장면적이 커지게 되고, 이는 소형화 추세에 역행하는 결과를 가져오는 문제점이 있었던 것이다.Therefore, when one or more ball grid array semiconductor packages are mounted on the motherboard as described above, the mounting area is increased by mounting each of the ball grid array semiconductor packages on the motherboard, which results in a problem that results in a miniaturization trend. .
이러한 문제점을 해결하기 위하여 개발된 반도체 장치로, 일본 공개특허공보 특개평8-274250호(공개일; 1996년 10월 18일)에서 하나의 반도체 장치 내에 두 개의 반도체칩이 실장되어 있는 반도체 장치가 개시된 있다.A semiconductor device developed to solve such a problem is disclosed in Japanese Patent Application Laid-Open No. 8-274250 (published on October 18, 1996), in which two semiconductor chips are mounted in one semiconductor device. Has been disclosed.
이러한 반도체 장치를 도 2에 도시하였으며, 상기 반도체 장치는 도시된 바와 같이 플레이트(61')의 저면에는 제1 반도체칩(11')를 실장함과 동시에, 상기 제1 반도체칩(11')은 솔더볼(41')에 의해 신호를 전달하고, 플레이트(61')의 상면에는 제2 반도체칩(12')을 실장함과 동시에, 상기 제2 반도체칩(12')은 리드(42')에 의해 신호를 전달하도록 하며, 상기 리드(42')와 솔더볼(41')의 높이는 서로 동일한 레벨의 높이를 갖도록 구성된다.2 illustrates a semiconductor device, in which a first semiconductor chip 11 'is mounted on a bottom surface of a plate 61', and the first semiconductor chip 11 'is formed as shown in FIG. The signal is transmitted by the solder ball 41 ', and the second semiconductor chip 12' is mounted on the upper surface of the plate 61 ', and the second semiconductor chip 12' is connected to the lead 42 '. In order to transmit a signal, the height of the lead 42 'and the solder ball 41' is configured to have the same level with each other.
그러나, 이러한 구조의 반도체 장치는, 두 개의 반도체칩이 플레이트를 사이에 두고 상하로 실장됨으로서, 반도체 장치의 두께가 상대적으로 두꺼워지는 단점이 있고, 또 상기 제1 반도체칩과 제1 반도체칩의 신호를 외부로 전달하는 입출력 수단으로서 각각 리드와 솔더볼을 사용함으로서, 상기 리드와 솔더볼의 높이를 동일한 레벨의 높이를 갖도록 하기가 매우 어려운 등의 제조 공정상의 문제점도 내포하고 있었다.However, the semiconductor device of such a structure has a disadvantage in that the thickness of the semiconductor device is relatively thick because two semiconductor chips are mounted up and down with a plate interposed therebetween, and the signal of the first semiconductor chip and the first semiconductor chip is By using a lead and a solder ball, respectively, as an input / output means for transmitting the outside to the outside, the manufacturing process problems such as the difficulty of making the height of the lead and the solder ball have the same level also included.
또한, 상기한 종래기술에 있어서는, 반도체칩이 상하부로 실장됨으로서, 이 반도체칩을 포함한 그 외의 구성부품을 외부의 환경으로부터 보호하기 위한 봉지재는 상하부에 각각 별도로 봉지하여야 함으로, 제조 공정상의 번거로운 단점이 있었다.In addition, in the above-described prior art, since the semiconductor chip is mounted on the upper and lower parts, the encapsulant for protecting other components including the semiconductor chip from the external environment must be encapsulated separately in the upper and lower parts, which is a cumbersome disadvantage in manufacturing process. there was.
본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 발명한 것으로, 두 개의 반도체칩이 플립 칩 본딩에 의해 적층되도록 실장된 반도체칩을 PCB 기판에 플립 칩 본딩하여서 이루어지는 반도체 장치로서, 상기 PCB 기판에 실장되는 플립 칩 본딩부와, 상기 두 개의 반도체칩이 적층되도록 실장된 플립 칩 본딩부를 에폭시 수지로 한번 디스펜싱하는 것에 의해 동시에 봉지할 수 있는 것이 특징이며, 따라서 제조 공정을 간소화할 수 있어 생상성을 높일 수 있고, 또 에폭시 디스펜싱에 의한 불량을 방지하여 신뢰성을 향상시킬 수 있도록 된 반도체 장치 및 그 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and is a semiconductor device formed by flip chip bonding a semiconductor chip mounted on a PCB substrate so that two semiconductor chips are stacked by flip chip bonding. The flip chip bonding portion to be mounted and the flip chip bonding portion mounted to stack the two semiconductor chips can be encapsulated at the same time by dispensing with epoxy resin once. Therefore, the manufacturing process can be simplified and the productivity can be simplified. The present invention provides a semiconductor device and a method of manufacturing the same, which can increase the reliability and improve reliability by preventing defects caused by epoxy dispensing.
본 발명의 목적을 달성하기 위한 반도체 장치는, 제1 반도체칩과; 상기 제1 반도체칩의 일면에 한쪽으로 위치되도록 플립 칩 본딩에 의해 실장되는 제2 반도체칩과; 상기 제2 반도체칩이 위치될 수 있는 관통홀이 형성되고, 이 관통홀의 외측부에 상기 제1 반도체칩이 플립 칩 본딩에 의해 실장되는 PCB 기판과; 상기 제1 반도체칩과 제2 반도체칩 그리고 PCB 기판 간에 상호 신호 전달이 되도록 하는 도전체와; 상기 도전체를 외부의 환경으로부터 보호하기 위하여 감싼 에폭시 수지와; 상기 제1 반도체칩과 제2 반도체칩의 신호를 PCB 기판을 통하여 외부로 입출력하도록 상기 PCB 기판의 저면에 융착된 솔더볼을 포함하여서 이루어진다.A semiconductor device for achieving the object of the present invention, the first semiconductor chip; A second semiconductor chip mounted by flip chip bonding so as to be positioned on one surface of the first semiconductor chip; A PCB substrate in which a through hole in which the second semiconductor chip is located is formed, and the first semiconductor chip is mounted by flip chip bonding on an outer side of the through hole; A conductor for mutual signal transmission between the first semiconductor chip, the second semiconductor chip, and the PCB substrate; An epoxy resin wrapped to protect the conductor from an external environment; It includes a solder ball fused to the bottom surface of the PCB substrate to input and output the signals of the first semiconductor chip and the second semiconductor chip to the outside through the PCB substrate.
여기서, 상기 PCB 기판에 형성되는 관통홀의 내측벽과, 제1 반도체칩에 실장되는 제2 반도체칩과의 사이 간격은 2mm 이내의 간격으로 유지되도록 된 것이다.Here, the distance between the inner wall of the through hole formed in the PCB substrate and the second semiconductor chip mounted on the first semiconductor chip is maintained at a distance within 2 mm.
또한, 본 발명의 목적을 달성하기 위한 반도체 장치의 제조방법으로 첫 번째는, 제1 반도체칩의 일면에 제2 반도체칩을 한쪽으로 위치하도록 플립 칩 본딩에 의해 실장하는 단계와; PCB 기판의 관통홀에 제2 반도체칩이 위치하도록 제2 반도체칩이 실장되어 있는 제1 반도체칩을 플립 칩 본딩에 의해 실장하는 단계와; 상기 제1 반도체칩에 실장된 제2 반도체칩의 플립 칩 본딩부와 PCB 기판에 실장되는 제1 반도체칩의 플립 칩 본딩부를 에폭시 수지로 한 번 디스펜싱하는 것에 의해서 동시에 봉지하는 단계와; 상기 제1 반도체칩과 제2 반도체칩의 신호를 상기 PCB 기판을 통하여 외부로 입출력하도록 상기 PCB 기판의 저면에 솔더볼을 융착하는 단계를, 포함하여서 이루어진다.In addition, the first method of manufacturing a semiconductor device for achieving the object of the present invention comprises the steps of: mounting by flip chip bonding so as to position the second semiconductor chip on one side of the first semiconductor chip; Mounting, by flip chip bonding, the first semiconductor chip on which the second semiconductor chip is mounted such that the second semiconductor chip is positioned in the through hole of the PCB substrate; Simultaneously encapsulating the flip chip bonding portion of the second semiconductor chip mounted on the first semiconductor chip and the flip chip bonding portion of the first semiconductor chip mounted on the PCB substrate by dispensing with epoxy resin once; And fusion welding solder balls on a bottom surface of the PCB substrate to input and output signals of the first and second semiconductor chips to the outside through the PCB substrate.
여기서, 상기 PCB 기판의 관통홀에 위치하는 제2 반도체칩은 상기 관통홀의 내측벽과 2mm 이내의 간격이 유지되도록 하고, 이와 같이 유지되는 간격은 관통홀의 내측벽을 제2 반도체칩 측으로 연장하여서 유지되도록 할 수 있다.Here, the second semiconductor chip positioned in the through-hole of the PCB substrate is maintained so that a gap within 2 mm from the inner wall of the through-hole, and the gap is maintained by extending the inner wall of the through-hole toward the second semiconductor chip. You can do that.
또한, 본 발명의 목적을 달성하기 위한 반도체 장치의 제조방법으로 두 번째는, 관통홀이 형성된 PCB 기판에 제1 반도체칩을 플립 칩 본딩에 의해 실장하는 단계와, 상기 PCB 기판의 관통홀을 통해 상기 제1 반도체칩의 일면에 제2 반도체칩을상기 관통홀의 내측으로 위치하도록 플립 칩 본딩에 의해 실장하는 단계와; 상기 PCB 기판에 실장된 제1 반도체칩의 플립 칩 본딩부와 상기 제1 반도체칩에 실장된 제2 반도체칩의 플립 칩 본딩부를 에폭시 수지로 한 번 디스펜싱하는 것에 의해서 동시에 봉지하는 단계와; 상기 제1 반도체칩과 제2 반도체칩의 신호를 상기 PCB 기판을 통하여 외부로 입출력하도록 상기 PCB 기판의 저면에 솔더볼을 융착하는 단계를, 포함하여서 이루어진다.In addition, a second method of manufacturing a semiconductor device for achieving the object of the present invention, the step of mounting the first semiconductor chip on the PCB substrate with a through hole formed by flip chip bonding, and through the through hole of the PCB substrate Mounting a second semiconductor chip on one surface of the first semiconductor chip by flip chip bonding so as to be positioned inside the through hole; Simultaneously encapsulating the flip chip bonding portion of the first semiconductor chip mounted on the PCB substrate and the flip chip bonding portion of the second semiconductor chip mounted on the first semiconductor chip by dispensing with epoxy resin once; And fusion welding solder balls on a bottom surface of the PCB substrate to input and output signals of the first and second semiconductor chips to the outside through the PCB substrate.
여기서, 상기 PCB 기판의 관통홀을 통해 제1 반도체칩에 실장되는 제2 반도체칩은 상기 관통홀의 내측벽과 2mm 이내의 간격이 유지되도록 실장하는 것이고, 이와 같이 유지되는 간격은 제2 반도체칩을 PCB 기판에 형성되는 관통홀의 내측벽 쪽으로 밀착해서 실장함으로서 유지되도록 할 수 있다.Here, the second semiconductor chip mounted on the first semiconductor chip through the through-hole of the PCB substrate is mounted so as to maintain a gap within 2 mm from the inner wall of the through-hole. It can be maintained by being mounted in close contact with the inner side wall of the through hole formed in the PCB substrate.
도 1은 종래의 볼 그리드 어레이 반도체 패키지를 나타낸 단면도1 is a cross-sectional view showing a conventional ball grid array semiconductor package
도 2는 종래에 두 개의 반도체칩이 실장된 반도체 장치를 나타낸 단면도2 is a cross-sectional view illustrating a semiconductor device in which two semiconductor chips are conventionally mounted.
도 3은 본 발명에 따른 반도체 장치를 나타낸 단면도3 is a cross-sectional view showing a semiconductor device according to the present invention.
도 4는 본 발명에 따른 에폭시 수지의 디스펜싱 방법을 설명하기 위한 평면도Figure 4 is a plan view for explaining the dispensing method of the epoxy resin according to the present invention
도 5a와 도 5b는 본 발명에 따른 에폭시 디스펜싱을 위한 구조의 실시예를 나타낸 단면도5A and 5B are cross-sectional views showing an embodiment of a structure for epoxy dispensing according to the present invention.
- 도면중 주요 부호에 대한 부호의 설명 --Explanation of symbols for major symbols in the drawings-
11 - 제1 반도체칩 12 - 제2 반도체칩11-First semiconductor chip 12-Second semiconductor chip
21 - PCB 기판 22 - 관통홀21-PCB Board 22-Through Hole
31 - 도전체 41 - 솔더볼31-Conductor 41-Solder Ball
51 - 에폭시 수지51-epoxy resin
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
먼저, 본 발명에 관계하는 반도체 장치는, 두 개의 반도체칩이 플립 칩 본딩에 의해 직접 적층되도록 실장되어 있는 반도체 장치이다.First, a semiconductor device according to the present invention is a semiconductor device in which two semiconductor chips are mounted so as to be directly stacked by flip chip bonding.
이와 같이 플립 칩 본딩에 의해 두 개의 반도체칩이 적층된 반도체칩은 다시 PCB 기판에 플립 칩 본딩되어 실장되고, 상기 플립 칩 본딩된 부분은 에폭시 수지로 디스펜싱에 의해 봉지되어 외부의 산화 및 부식으로부터 보호된다.As described above, a semiconductor chip in which two semiconductor chips are stacked by flip chip bonding is flip chip bonded and mounted on a PCB substrate, and the flip chip bonded portion is encapsulated by dispensing with epoxy resin to prevent external oxidation and corrosion. Protected.
도 3은 본 발명에 따른 반도체 장치를 나타낸 단면도이다. 도시된 바와 같이 제1 반도체칩(11)의 표면에 상기 제1 반도체칩(11)의 크기 보다 작은 크기의 제2 반도체칩(12)이 플립 칩 본딩에 의해 실장되어 있고, 상기 제1 반도체칩(11)은 PCB기판(21)에 플립 칩 본딩에 의해 실장되어 있다.3 is a cross-sectional view of a semiconductor device according to the present invention. As shown in the drawing, a second semiconductor chip 12 having a size smaller than that of the first semiconductor chip 11 is mounted on the surface of the first semiconductor chip 11 by flip chip bonding. 11 is mounted to the PCB substrate 21 by flip chip bonding.
즉, 상기 제1 반도체칩(11)과 제2 반도체칩(12) 그리고 PCB 기판(21) 간에 상호 신호 전달이 되도록 도전체(31)에 의해 연결되어 있고, 이 도전체(31)를 외부의 환경으로부터 보호하도록 에폭시 수지(51)로 감싸져 있다.That is, the first semiconductor chip 11, the second semiconductor chip 12, and the PCB substrate 21 are connected by a conductor 31 so as to transmit signals to each other, and the conductor 31 is connected to an external device. It is wrapped with epoxy resin 51 to protect it from the environment.
그리고, 상기 제2 반도체칩(12)은 제1 반도체칩(11)의 일면에 한쪽으로 치우치도록 실장되어 있다.The second semiconductor chip 12 is mounted on one surface of the first semiconductor chip 11 so as to be biased to one side.
또한, 상기 PCB 기판(21)에는 상기 제1 반도체칩(11)에 실장된 제2 반도체칩(12)이 위치되는 관통홀(22)이 형성되어 있고, 상기 PCB 기판(21)의 저면에는 상기 제1 반도체칩(11)과 제2 반도체칩(12)의 신호를 외부로 전달하는 입출력 단자인 솔더볼(41)이 융착되어 있다.In addition, a through hole 22 in which the second semiconductor chip 12 mounted on the first semiconductor chip 11 is located is formed in the PCB substrate 21, and the bottom surface of the PCB substrate 21 is The solder ball 41, which is an input / output terminal for transmitting signals of the first semiconductor chip 11 and the second semiconductor chip 12 to the outside, is fused.
여기서, 상기 PCB 기판(21)에 형성되는 관통홀(22)의 내측벽과 상기 제1 반도체칩(11)에 적층되도록 실장된 제2 반도체칩(12)과의 사이 간격(d)은 2mm 이내의 간격으로 유지되어 있다. 즉, 그 사이의 간격(d)이 좁은 간격으로 유지되어 있다.Here, the distance d between the inner wall of the through hole 22 formed in the PCB substrate 21 and the second semiconductor chip 12 mounted to be stacked on the first semiconductor chip 11 is within 2 mm. It is maintained at intervals of. That is, the space | interval d between them is maintained by narrow space | interval.
상기와 같이 PCB 기판(21)의 내측벽과 상기 제1 반도체칩(11)에 적층되도록 실장된 제2 반도체칩(12)과의 사이 간격(d)을 2mm 이내로 하기 위한 구조는, 도 5a에 도시된 바와 같이 상기 PCB 기판(21)에 형성되는 관통홀(22)의 내측벽을 상기 제1 반도체칩(11)에 적층되도록 플립 칩 본딩되어 실장된 제2 반도체칩(12) 쪽으로 일정 거리(D2) 만큼 연장하여서 간격(d)을 유지할 수 있다.As described above, a structure for setting the distance d between the inner wall of the PCB substrate 21 and the second semiconductor chip 12 mounted to be stacked on the first semiconductor chip 11 to be within 2 mm is shown in FIG. 5A. As shown, a predetermined distance toward the second semiconductor chip 12 mounted by flip chip bonding the inner wall of the through hole 22 formed in the PCB substrate 21 to be stacked on the first semiconductor chip 11. The distance d can be maintained by extending by D2).
또는, 도 5b에 도시된 바와 같이 상기 제1 반도체칩(11)에 적층되도록 플립 칩 본딩되어 실장된 제2 반도체칩(12)의 위치를 상기 PCB 기판(21)에 형성되는 관통홀(22)의 내측벽 쪽으로 일정 거리(D2) 만큼 이동시켜서 간격(d)을 유지할 수 있다. 이때에는, 상기 제1 반도체칩(11)에 실장되는 제2 반도체칩(12)의 위치를 상기 제1 반도체칩(11)이 PCB 기판(21)에 실장되는 위치를 고려하여야 함은 당연하다.Alternatively, as illustrated in FIG. 5B, a through hole 22 is formed in the PCB substrate 21 to position the second semiconductor chip 12 that is flip chip bonded and mounted to be stacked on the first semiconductor chip 11. The distance d may be maintained by moving the inner wall toward the inner wall by a predetermined distance D2. In this case, the position of the second semiconductor chip 12 mounted on the first semiconductor chip 11 should be considered to be the position where the first semiconductor chip 11 is mounted on the PCB substrate 21.
즉, 상기와 같이 PCB 기판(21)의 관통홀(22) 내측벽과 제2 반도체칩(12)과의 사이 간격(d)을 2mm 이내로 유지하기 위해서는 상기 PCB 기판(21)에 형성되는 관통홀(22)의 내측벽을 제2 반도체칩(12) 측으로 연장하거나, 또는 상기 제2 반도체칩(12)을 PCB 기판(21)에 형성되는 관통홀(22)의 내측벽 쪽으로 밀착해서 실장함으로서 가능하다.That is, in order to maintain the distance d between the inner wall of the through hole 22 of the PCB substrate 21 and the second semiconductor chip 12 within 2 mm as described above, the through hole formed in the PCB substrate 21. It is possible by extending the inner wall of the 22 toward the second semiconductor chip 12 or by mounting the second semiconductor chip 12 in close contact with the inner wall of the through hole 22 formed in the PCB substrate 21. Do.
이와 같은 본 발명은, 상기 PCB 기판(21)에 실장되는 제1 반도체칩(11)의 플립 칩 본딩부와, 상기 제1 반도체칩(11)에 적층되도록 실장된 제2 반도체칩(12)의 플립 칩 본딩부를 에폭시 수지(51)로 한번 디스펜싱 하는 것에 의해 동시에 봉지하는 것으로, 도 4에 도시된 바와 같이 에폭시 수지(51)를 화살표 방향으로, 즉 제2 반도체칩(12)이 적층된 측에서부터 사방으로 돌려서 에폭시 수지(51)를 한번 디스펜싱하면 상기 PCB 기판(21)에 실장되는 제1 반도체칩(11)의 플립 칩 본딩부와, 상기 제1 반도체칩(11)에 적층되도록 실장된 제2 반도체칩(12)의 플립 칩 본딩부를 동시에 봉지할 수 있다.In the present invention, the flip chip bonding portion of the first semiconductor chip 11 mounted on the PCB substrate 21 and the second semiconductor chip 12 mounted on the first semiconductor chip 11 are stacked. Simultaneously sealing the flip chip bonding portion by dispensing with the epoxy resin 51, the epoxy resin 51 in the direction of the arrow, that is, the side on which the second semiconductor chip 12 is stacked as shown in FIG. When the epoxy resin 51 is dispensed once from all directions, the flip chip bonding portion of the first semiconductor chip 11 mounted on the PCB substrate 21 and the first semiconductor chip 11 are stacked to be stacked on the first semiconductor chip 11. The flip chip bonding portion of the second semiconductor chip 12 may be simultaneously sealed.
이와 같이 두 개의 플립 칩 본딩부가 동시에 봉지되는 것은, 상기 PCB 기판(21)의 관통홀(22) 내측벽과 제2 반도체칩(12)과의 사이 간격(d)이 좁기 때문에 모세관 현상에 의해 제2 반도체칩(12)의 플립 칩 본딩부에 자동으로 에폭시 수지(51)가 빨려 들어가면서 봉지된다.The two flip chip bonding parts are simultaneously encapsulated because the gap d between the inner wall of the through-hole 22 and the second semiconductor chip 12 of the PCB substrate 21 is narrow, which is caused by capillary action. 2 The epoxy resin 51 is automatically sucked into the flip chip bonding part of the semiconductor chip 12, and it is sealed.
이상의 설명에서와 같이 본 발명에 의한 반도체 장치 및 그 제조방법에 의하면, 두 개의 반도체칩이 적층되도록 실장된 반도체 장치로서, 상기 두 개의 반도체칩의 플립 칩 본딩부를 동시에 에폭시 수지로 디스펜싱하여 봉지할 수 있음으로서 공정을 간소화할 수 있어 생산성을 높이고, 또 디스펜싱에 의한 불량을 방지하여 신뢰성을 향상시킬 수 있는 등의 이점이 있다.As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, a semiconductor device mounted so that two semiconductor chips are stacked, and the flip chip bonding portions of the two semiconductor chips are simultaneously dispensed and sealed with an epoxy resin. This can simplify the process, increase productivity, prevent defects caused by dispensing, and improve reliability.
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