CN219834143U - S-band rapid frequency hopping local oscillation system of DDS and PLL - Google Patents

Abstract

The utility model discloses an S-band fast frequency hopping local oscillation system of DDS and PLL, which comprises a mixer, a TCXO temperature compensation crystal oscillator, DDS and PLL; the output end of the TCXO temperature compensation crystal oscillator is respectively connected with the input ends of the DDS and the PLL, and the output ends of the DDS and the PLL are both connected with the mixer. The frequency hopping frequency outputted by the DDS and the fixed local oscillator outputted by the PLL are subjected to frequency domain subtraction operation through the mixer, the fast frequency hopping local oscillator frequency is outputted externally, the frequency hopping rate is fast, the generated fast frequency hopping local oscillator frequency is 3452-3752 MHz, the theoretical minimum frequency hopping interval is about 9.6ns, namely hundreds of millions of frequency hopping can be completed within 1s, the principle is simple, the frequency hopping output frequency can be changed by adjusting the fixed local oscillator frequency outputted by the PLL, and the circuit reusability is high.

Description

S-band rapid frequency hopping local oscillation system of DDS and PLL

Technical Field

The utility model belongs to the field of frequency hopping communication, and relates to an S-band rapid frequency hopping local oscillation system of a DDS and a PLL.

Background

The frequency hopping communication is a communication technology of pseudo-random frequency hopping with carrier frequency in a wider frequency range, has the advantages of strong anti-interference performance, excellent anti-interception performance, good anti-fading performance, good communication effect and the like, can maximally utilize spectrum resources, and is widely applied to the communication field. The frequency hopping local oscillator is a key module of the frequency hopping communication system, and the frequency hopping rate determines the performance index of the frequency hopping communication system to a great extent, so that the design of the fast frequency hopping local oscillator becomes one of the keys of the frequency hopping communication system.

The current implementation modes of the frequency hopping local oscillator mainly comprise the following two modes: 1) A phase-locked loop (PLL) is a negative feedback control system for utilizing the voltage generated by the frequency phase difference to tune a voltage-controlled oscillator to generate target frequency, and the frequency information is configured by an upper computer, and the frequency is output after being locked again, so that the frequency hopping function is realized; 2) Direct digital frequency synthesis (DDS) is to utilize the Nyquist sampling theorem to generate waveforms through a table look-up method, and to realize rapid frequency hopping by configuring different frequency tuning words. The DDS has the advantages of fast frequency switching time, high frequency resolution and the like.

Due to the inherent characteristics of the phase-locked loop, the switching time of the output frequency of the PLL is very slow, and quick frequency hopping cannot be realized; the output frequency of the DDS can only be in the first Nyquist bandwidth, and can not output very high frequency, and usually, the output frequency of the DDS is 0.4 fs, and the output frequency can reach hundreds of MHz, so that the DDS is not suitable for application scenes with higher frequency.

Disclosure of Invention

The utility model aims to overcome the defects of the prior art, and provides an S-band fast frequency hopping local oscillation system of a DDS and a PLL, which can generate fast frequency hopping local oscillation frequencies of 3452-3752 MHz, and the theoretical minimum frequency hopping interval is about 9.6ns, namely hundreds of millions of frequency hopping can be completed within 1S.

In order to achieve the purpose, the utility model is realized by adopting the following technical scheme:

an S-band fast frequency hopping local oscillation system of a DDS and a PLL comprises a mixer, a TCXO temperature compensation crystal oscillator, the DDS and the PLL;

the output end of the TCXO temperature compensation crystal oscillator is respectively connected with the input ends of the DDS and the PLL, and the output ends of the DDS and the PLL are both connected with the mixer.

Preferably, the TCXO outputs a 40MHz clock.

Preferably, an LPF is provided between the DDS and the mixer.

Preferably, the mixer output has an input of the BPF.

Preferably, the inputs of the DDS and the PLL are both connected to an external controller.

Further, the external controller adopts an FPGA or a CPLD.

Preferably, the mixer supports RF/LO: 2.5-7 GHz, IF: DC-3 GHz.

Preferably, the sampling clock inside the DDS is a 2500MHz single frequency signal.

Compared with the prior art, the utility model has the following beneficial effects:

according to the utility model, the frequency hopping frequency output by the DDS and the fixed local oscillation output by the PLL are subjected to frequency domain subtraction operation by the mixer, the fast frequency hopping local oscillation frequency is output to the outside, the frequency hopping speed is fast, the generated fast frequency hopping local oscillation frequency is 3452-3752 MHz, the theoretical minimum frequency hopping interval is about 9.6ns, namely hundreds of millions of frequency hopping can be completed within 1s, the principle is simple, the output frequency hopping output frequency can be changed by adjusting the fixed local oscillation frequency output by the PLL, and the circuit reusability is high.

Drawings

Fig. 1 is a schematic diagram of an S-band fast frequency hopping local oscillation system of a DDS and PLL of the present utility model;

fig. 2 is a circuit diagram of a TCXO temperature compensated crystal oscillator according to the present utility model;

FIG. 3 is a schematic diagram of a PLL circuit of the present utility model;

fig. 4 is a schematic diagram of a mixer circuit of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model; all other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "inner" and "outer" refer to directions toward or away from, respectively, the geometric center of a particular component.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

As shown in FIG. 1, the S-band fast frequency hopping local oscillation system for the DDS and the PLL of the present utility model comprises a mixer, a BPF, LPF, TCXO temperature compensation crystal oscillator, the DDS and the PLL.

The input ends of the DDS and the PLL are connected with an external controller, the output ends of the TCXO temperature compensation crystal oscillator are respectively connected with the input ends of the DDS and the PLL, the output ends of the DDS and the PLL are connected with a mixer, an LPF is arranged between the DDS and the mixer, and the output end of the mixer is provided with the input end of the BPF.

The external controller adopts an FPGA or a CPLD.

As shown in fig. 2, the TCXO outputs a 40MHz clock, which is divided into two paths by a clock Buffer, wherein one path is used as a reference clock for DDS; one way is for the PLL to use as a reference clock.

The DDS outputs a rapid hopping frequency range 475-775 MHz, the DDS realizes rapid frequency hopping by configuring a frequency tuning word through an external controller (FPGA/CPLD), a 40MHz TCXO temperature compensation crystal oscillator is selected as an external reference clock for a reference clock, and a 2500MHz single-frequency signal is generated by a DDS internal phase-locked loop as a system clock, namely a sampling clock of a DDS internal DAC.

The LPF low pass filter is used for filtering the image frequency and harmonic wave of DDS output.

As shown in fig. 3, the PLL outputs a fixed local oscillation frequency 4227MHz, the PLL also uses a 40M TCXO temperature compensated crystal as a reference clock, and an external controller (FPGA/CPLD) monitors the locking state of the PLL in real time, and locks in time when an abnormal loss of lock occurs.

As shown in fig. 4, mixer U3 supports RF/LO: 2.5-7 GHz, IF: DC-3 GHz; the IF frequency in this design is the DDS output signal frequency range: 475-775 MHz, the LO frequency is the fixed frequency of the PLL output: 4227MHz, performing subtraction operation on the fixed local oscillator and the intermediate frequency, and outputting fast-jump local oscillator frequency: 3452-3752 MHz.

The band-pass filter BPF is used to suppress the image frequency and out-of-band harmonic noise generated by the mixing.

The fast frequency hopping local oscillator comprises the following steps: the TCXO outputs a 40MHz clock, and is divided into two paths through a clock Buffer, wherein one path is used as a reference clock for the DDS and the other path is used as a reference clock for the PLL; the mixer performs frequency domain subtraction operation on the frequency hopping frequencies 475-775 MHz output by the DDS and the fixed local oscillation 4227MHz output by the PLL, and externally outputs the fast frequency hopping local oscillation frequencies 3452-3752 MHz.

The system of the utility model has fast frequency hopping rate and the theoretical minimum frequency hopping interval is 9.6ns. The circuit has simple structure principle, can change the output frequency hopping output frequency by adjusting the fixed local oscillation frequency and the band-pass filter output by the phase-locked loop, and has high circuit reusability.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are incorporated herein by reference for the purpose of completeness. The omission of any aspect of the subject matter disclosed herein in the preceding claims is not intended to forego such subject matter, nor should the applicant not be considered to be a part of the disclosed subject matter.

Claims (8)

1. An S-band fast frequency hopping local oscillation system of a DDS and a PLL is characterized by comprising a mixer, a TCXO temperature compensation crystal oscillator, the DDS and the PLL;

the output end of the TCXO temperature compensation crystal oscillator is respectively connected with the input ends of the DDS and the PLL, and the output ends of the DDS and the PLL are both connected with the mixer.

2. The S-band fast frequency hopping local oscillator system of DDS and PLL of claim 1, wherein the TCXO temperature compensated oscillator outputs a 40MHz clock.

3. The S-band fast frequency hopping local oscillator system of DDS and PLL of claim 1, wherein an LPF is provided between the DDS and the mixer.

4. The S-band fast frequency hopping local oscillator system of claim 1, wherein the mixer output has an input of a BPF.

5. The S-band fast frequency hopping local oscillator system of claim 1, wherein the input terminals of the DDS and PLL are connected to an external controller.

6. The S-band fast frequency hopping local oscillator system of DDS and PLL of claim 5, wherein the external controller employs an FPGA or CPLD.

7. The S-band fast frequency hopping local oscillator system of DDS and PLL of claim 1, wherein the mixer supports RF/LO: 2.5-7 GHz, IF: DC-3 GHz.

8. The S-band fast frequency hopping local oscillator system of DDS and PLL of claim 1, wherein the sampling clock within DDS is a 2500MHz single frequency signal.