CN219738964U - High-voltage MOS device - Google Patents

Abstract

The utility model provides a high-voltage MOS device, which comprises a substrate, a grid electrode, a first shallow groove, a second shallow groove, a source electrode and a drain electrode, wherein the grid electrode is arranged on the substrate; the grid electrode is positioned on the upper surface of the substrate or in the substrate, the first shallow groove, the second shallow groove, the source electrode and the drain electrode are positioned in the substrate, the source electrode and the drain electrode are symmetrically distributed on two sides of the grid electrode, one ends of the first shallow groove and the second shallow groove are respectively adjacent to the source electrode and the drain electrode, and the other ends extend to the periphery of the grid electrode along the center direction of the device. According to the improved structural design, the shallow grooves are arranged between the source electrode and the drain electrode of the high-voltage MOS device, so that the spacing between the source electrode and the drain electrode is limited, and the high-voltage resistance of the device is ensured. Meanwhile, the shallow trench structure can play a self-alignment role in the manufacturing process of the device, is helpful for helping the source and drain terminals to keep symmetrical, can simplify the manufacturing process while ensuring the performance of the device, and reduces the manufacturing cost.

Description

High-voltage MOS device

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a high-voltage MOS device.

Background

High Voltage (HV) MOS (metal oxide semiconductor) devices are becoming more and more widely used in such fields as power control and driving circuits, because of their advantages of fast switching speed, low loss, high reliability, etc.

High voltage MOS devices, particularly high voltage CMOS (complementary metal oxide semiconductor) devices, require a relatively large distance between the Drain and the gate because of the high voltage required at the Drain, and therefore their Drain extension (Drain extension) length is important for the leakage current (leakage) of the device itself.

A common structure of the existing high-voltage MOS device is shown in fig. 1, and no other structure is formed in the substrate 14 between the gate 11 and the source 12 and drain 13. In the manufacturing process of the high-voltage MOS device with the structure, the source electrode and the drain electrode of the device are non-uniform in width and are asymmetric due to the fact that the doping process characteristics (such as the fact that the doping concentration is difficult to keep completely uniform, ions are easy to laterally diffuse in the high-temperature annealing process) of the N+/P+ and the manufacturing process of the MOS device are generally low. The source-drain width is different, so that the grid cannot be used as self-alignment, leakage current generated when the source-drain is exchanged is high, the voltage withstanding of the devices is different, and the use of the devices is affected.

It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present utility model and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the utility model section.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide a high-voltage MOS device, which is used for solving the problems that the high-voltage MOS device in the prior art is easy to cause inconsistent width of source and drain terminals in the manufacturing process, leakage current is high when the source and drain terminals are exchanged, voltage withstanding of the device is different, and use of the device is affected.

To achieve the above and other related objects, the present utility model provides a high voltage MOS device including a substrate, a gate electrode, a first shallow trench, a second shallow trench, a source electrode, and a drain electrode; the grid electrode is positioned on the upper surface of the substrate or in the substrate, the first shallow groove, the second shallow groove, the source electrode and the drain electrode are positioned in the substrate, the source electrode and the drain electrode are symmetrically distributed on two sides of the grid electrode, one ends of the first shallow groove and the second shallow groove are respectively adjacent to the source electrode and the drain electrode, and the other ends extend to the periphery of the grid electrode along the center direction of the device.

Optionally, the gate is located on the upper surface of the substrate, and the high-voltage MOS device further includes a sidewall structure, where the sidewall structure extends from a side surface of the gate to surfaces of the first shallow trench and the second shallow trench.

Optionally, the sidewall structure includes an oxide layer and a nitride layer, where the oxide layer is located on a side surface of the gate, and the nitride layer is located on a surface of the oxide layer facing away from the gate.

Optionally, the depth of the first shallow trench and the second shallow trench is greater than the depth of the source and the drain.

Optionally, the high-voltage MOS device includes a source drift region and a drain drift region that are spaced apart in the substrate, the gate is located between the source drift region and the drain drift region and extends to surfaces of the source drift region and the drain drift region, the first shallow trench and the source are located in the source drift region, and the second shallow trench and the drain are located in the drain drift region.

Optionally, the depths of the first shallow trench and the second shallow trench are smaller than the depths of the source drift region and the drain drift region.

Optionally, the high-voltage MOS device further includes a source electrode, a drain electrode, and a gate electrode, which are respectively connected to the source electrode, the drain electrode, and the gate in one-to-one correspondence.

Optionally, the source, drain and gate surfaces are each formed with a metal silicide layer.

Optionally, the first shallow trench and the second shallow trench each include a high-K dielectric layer and an isolation material layer located inside the high-K dielectric layer and completely filling the corresponding shallow trench.

Optionally, the surfaces of the first shallow trench and the second shallow trench are formed with a dummy gate structure.

As described above, the high-voltage MOS device of the present utility model has the following beneficial effects: according to the improved structural design, the shallow grooves are arranged between the source electrode and the drain electrode of the high-voltage MOS device, so that the spacing between the source electrode and the drain electrode is limited, and the high-voltage resistance of the device is ensured. Meanwhile, the shallow trench structure can play a self-alignment role in the manufacturing process of the device, is helpful for helping the source and drain terminals to keep symmetrical, can simplify the manufacturing process while ensuring the performance of the device, and reduces the manufacturing cost.

Drawings

Fig. 1 is a schematic cross-sectional structure of a high-voltage MOS device according to the prior art.

Fig. 2 and 3 are schematic cross-sectional views illustrating various examples of the high-voltage MOS device according to the present utility model.

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model. As described in detail in the embodiments of the present utility model, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present utility model, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. In order to make the illustration as concise as possible, not all structures are labeled in the drawings.

As shown in fig. 2 and 3, the present utility model provides a high voltage MOS device including a substrate 21, a gate electrode, a first shallow trench 23, a second shallow trench 24, a source electrode 25, and a drain electrode 26. The gate is located on the upper surface of the substrate 21 or within the substrate 21. That is, the gate electrode may be a planar gate structure as shown in fig. 2, or may be a trench gate structure as shown in fig. 3. The first shallow trench 23, the second shallow trench 24, the source 25 and the drain 26 are all located in the substrate 21, the source 25 and the drain 26 are symmetrically distributed on two sides of the gate, one ends of the first shallow trench 23 and the second shallow trench 24 are respectively adjacent to the source 25 and the drain 26, and the other ends extend to the periphery of the gate along the center direction of the device. Referring to fig. 2 and 3, it can be seen that the first shallow trench 23 has one end abutting the source 25 and the other end extending rightward to the gate periphery, the second shallow trench 24 has one end abutting the drain 26 and the other end extending leftward to the gate periphery, but the first shallow trench 23 and the second shallow trench 24 are not in contact with each other, with a space therebetween. The substrate 21 located at this pitch is located directly under the gate. The first shallow trench and the second shallow trench may be single or each of a plurality of the first shallow trench and the second shallow trench may be spaced apart.

The concept of symmetrical distribution is that the distance between the source electrode 25 and the drain electrode 26 and the gate electrode are the same and the widths thereof are the same. Accordingly, the first shallow trenches 23 and the second shallow trenches 24 also have the same depth and width, and are symmetrically distributed with respect to the center of the device. This symmetry is of great importance for the performance of high voltage MOS devices, which is only easily achieved based on the device structure of the present utility model. And the words such as "first" and "second" in this embodiment are merely for convenience of description and are not meant to be limiting in nature. For example, the trench at the drain end may be defined as a first shallow trench and the trench at the source end may be defined as a second shallow trench.

According to the improved structural design, the shallow grooves are arranged between the source electrode and the drain electrode of the high-voltage MOS device, so that the spacing between the source electrode and the drain electrode is limited, and the high-voltage resistance of the device is ensured. Meanwhile, the shallow trench structure can play a self-alignment role in the manufacturing process of the device, is helpful for helping the source and drain terminals to keep symmetrical, can simplify the manufacturing process while ensuring the performance of the device, and reduces the manufacturing cost.

The substrate 21 includes, but is not limited to, various types of semiconductor material layers such as silicon wafers, germanium wafers, silicon carbide wafers, silicon-on-insulator wafers, and the like. In this embodiment, a silicon wafer is preferable. In some examples, substrate 21 may include a base layer and a buffer layer on a surface of the base layer, the buffer layer having the same conductivity type as the substrate 21 layer, but having a doping concentration slightly lower than that of the base layer. In the case where the buffer layer is formed, the source electrode 25 and the drain electrode 26 are formed in the buffer layer by a heavy doping process.

In some examples, the high voltage MOS device includes a source drift region 28 and a drain drift region 29 spaced apart within the substrate 21, the gate electrode being located between the source drift region 28 and the drain drift region 29 and extending to the surfaces of the source drift region 28 and the drain drift region 29, the first shallow trench 23 and the source electrode 25 being located in the source drift region 28, and the second shallow trench 24 and the drain electrode 26 being located in the drain drift region 29. The source drift region 28 and the drain drift region 29 are both formed by a doping process, the doping depths of both are preferably uniform, and both are lightly doped, less than the doping concentrations of the source 25 and the drain 26. In a further example, the depth of both the first shallow trench 23 and the second shallow trench 24 is smaller than the depth of the source drift region 28 and the drain drift region 29, i.e. the bottoms of the first shallow trench 23 and the second shallow trench 24 are spaced from the bottom of the corresponding drift region. The first shallow trench 23 and the second shallow trench 24 preferably each have a depth greater than the depth of the source 25 and the drain 26. And the sides of the first and second shallow trenches 23 and 24 have a pitch with the sides of the corresponding drift regions, which is covered by the gate.

If the gate is a planar gate structure, the structure of the gate is shown in fig. 2, and the structure of the gate includes a gate oxide layer 221 on the upper surface of the substrate 21 and a gate conductive layer 222 on the upper surface of the gate oxide layer 221. The gate oxide layer 221 is preferably a silicon oxide layer, preferably having a thickness between 100nm and 200nm, and is preferably formed by a thermal oxidation process. The gate conductive layer 222 is typically a polysilicon layer and is preferably formed by a chemical vapor deposition process. In the case of a planar gate structure, the gate side may be formed with a sidewall structure extending from the gate side to the surfaces of the first and second shallow trenches 23 and 24 up to cover a portion of the shallow trenches. The sidewall structure may be a single-layer structure or a multi-layer structure, for example, in an example, the sidewall structure includes an oxide layer 271 and a nitride layer 272, where the oxide layer 271 is located on a side surface of the gate, and the nitride layer 272 is located on a surface of the oxide layer 271 facing away from the gate. In other examples, the sidewall structure may also be a structure with more than 3 layers, for example, a four-layer structure including two silicon oxide-silicon nitride stacked structures, which may help to further improve the isolation protection effect of the sidewall.

If the gate is a trench gate structure, the structure of the gate can be shown in fig. 3. It is located in the substrate 21, and the cross section of it may be U-shaped, including an outer gate oxide layer 221 and a gate conductive layer 222 lining the gate oxide layer 221, and may further include a gate dielectric layer 223 covering the gate conductive layer 222 and the gate oxide layer 221, where the gate dielectric layer includes, but is not limited to, a silicon nitride layer, and may also be another high-K dielectric material layer, for example. The trench gate may be formed by, for example, forming a corresponding trench in the substrate 21 by an etching process, forming a silicon oxide layer on the inner surface of the trench by a thermal oxidation process, and filling the polysilicon layer by a vapor deposition process to fill the remaining portion of the trench. In other examples, the gate conductive layer 222 may also be a metal material layer, such as a nickel layer, an aluminum layer. In other examples, the gate may also be a split gate structure, particularly without limitation.

The high-voltage MOS device further includes a source electrode 30, a drain electrode 31, and a gate electrode 32, which are respectively connected to the source electrode 25, the drain electrode 26, and the gate electrode in a one-to-one correspondence manner, so as to electrically lead out each structure. The electrodes may be, for example, one of metal electrodes such as aluminum electrodes, copper electrodes, gold electrodes, and silver electrodes, or may be other nonmetallic electrodes. The forming method of each electrode can be that firstly, the contact holes which correspondingly expose each structure are formed through an etching process, then, the metal layers which fill the contact holes are formed through a physical vapor deposition process, and then, each electrode is formed through etching.

In an example, the source 25, the drain 26 and the gate are each formed with a metal silicide layer 33, and each electrode is electrically connected to the corresponding metal silicide layer 33. The metal silicide layer 33 may be formed by forming a metal layer on the surface of each structure and then annealing the metal layer at a high temperature. The metal silicide layer has the advantages of good conductivity, high hardness and the like, and is beneficial to improving the performance of the device.

Each shallow trench is preferably of a wide top and narrow bottom morphology to facilitate filling, preferably a U-shaped trench. Each shallow trench may be filled with a single insulating material. In a preferred example, however, to enhance the isolation effect, the first shallow trench 23 and the second shallow trench 24 each include a high-K dielectric layer and an isolation material layer that is located inside the high-K dielectric layer and completely fills the corresponding shallow trench. The dielectric constant of the high-K dielectric layer is greater than that of the isolation material layer. For example, the high-K dielectric layer may be a silicon nitride layer or a porous silicon oxide layer, and the isolation material layer may be a silicon oxide layer.

In some examples, the surfaces of the first shallow trench 23 and the second shallow trench 24 are formed with a dummy gate structure (not shown). The dummy gate structure may also include, for example, a gate oxide layer and a conductive layer, but may not be electrically extracted. The formation of dummy gate structures helps to improve device stress distribution, especially during subsequent processes such as chemical mechanical polishing, to improve device surface planarity.

The high voltage MOS device may also include other structures, depending on the type of device. For example, if a superjunction high voltage MOSFET device, a superjunction structure formed within the substrate is also included. The utility model is not limited to the specific type of device and the corresponding device structure is known to those skilled in the art and is not developed one by one.

In summary, the present utility model provides a high-voltage MOS device, which includes a substrate, a gate, a first shallow trench, a second shallow trench, a source and a drain; the grid electrode is positioned on the upper surface of the substrate or in the substrate, the first shallow groove, the second shallow groove, the source electrode and the drain electrode are positioned in the substrate, the source electrode and the drain electrode are symmetrically distributed on two sides of the grid electrode, one ends of the first shallow groove and the second shallow groove are respectively adjacent to the source electrode and the drain electrode, and the other ends extend to the periphery of the grid electrode along the center direction of the device. According to the improved structural design, the shallow grooves are arranged between the source electrode and the drain electrode of the high-voltage MOS device, so that the spacing between the source electrode and the drain electrode is limited, and the high-voltage resistance of the device is ensured. Meanwhile, the shallow trench structure can play a self-alignment role in the manufacturing process of the device, is helpful for helping the source and drain terminals to keep symmetrical, can simplify the manufacturing process while ensuring the performance of the device, and reduces the manufacturing cost. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The high-voltage MOS device is characterized by comprising a substrate, a grid electrode, a first shallow groove, a second shallow groove, a source electrode and a drain electrode; the grid electrode is positioned on the upper surface of the substrate or in the substrate, the first shallow groove, the second shallow groove, the source electrode and the drain electrode are positioned in the substrate, the source electrode and the drain electrode are symmetrically distributed on two sides of the grid electrode, one ends of the first shallow groove and the second shallow groove are respectively adjacent to the source electrode and the drain electrode, and the other ends extend to the periphery of the grid electrode along the center direction of the device.

2. The high voltage MOS device of claim 1, wherein the gate is located on an upper surface of the substrate, the high voltage MOS device further comprising a sidewall structure extending from a side of the gate to a surface of the first shallow trench and the second shallow trench.

3. The high voltage MOS device of claim 2, wherein the sidewall structure comprises an oxide layer and a nitride layer, the oxide layer being located on a gate side surface, the nitride layer being located on a surface of the oxide layer facing away from the gate.

4. The high voltage MOS device of claim 1, wherein the first shallow trench and the second shallow trench each have a depth greater than a depth of the source and the drain.

5. The high voltage MOS device of claim 1, wherein the high voltage MOS device comprises a source drift region and a drain drift region spaced apart within the substrate, the gate is located between and extends to a surface of the source drift region and the drain drift region, the first shallow trench and the source are located in the source drift region, and the second shallow trench and the drain are located in the drain drift region.

6. The high voltage MOS device of claim 5, wherein the first shallow trench and the second shallow trench each have a depth that is less than a depth of the source drift region and the drain drift region.

7. The high voltage MOS device of claim 1, further comprising a source electrode, a drain electrode, and a gate electrode, each connected to the source, drain, and gate in a one-to-one correspondence.

8. The high voltage MOS device of claim 1, wherein the source, drain and gate surfaces are each formed with a metal silicide layer.

9. The high voltage MOS device of claim 1, wherein the first shallow trench and the second shallow trench each comprise a high-K dielectric layer and an isolation material layer inside the high-K dielectric layer that completely fills the corresponding shallow trench.

10. The high-voltage MOS device according to any one of claims 1 to 9, wherein the surfaces of the first and second shallow trenches are formed with a dummy gate structure.