CN115910795B - Shielding grid power device and preparation method thereof - Google Patents
Shielding grid power device and preparation method thereof Download PDFInfo
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Abstract
The invention provides a shielded gate power device and a preparation method thereof, wherein the shielded gate power device comprises a semiconductor layer, a dielectric layer, a shielded gate layer, a gate dielectric layer, a gate conducting layer, an interlayer dielectric layer, a plugging layer, a contact hole and a source electrode, wherein a plurality of grooves which are arranged at intervals are arranged on the upper surface layer of the semiconductor layer; the dielectric layer is positioned on the inner wall and the bottom surface of the groove; the shielding grid layer is positioned in the groove; the gate dielectric layer covers the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer; the gate conductive layer fills the trench; the interlayer dielectric layer covers the upper surfaces of the gate dielectric layer and the gate conducting layer, and a plurality of first through holes penetrating through the interlayer dielectric layer are formed in the interlayer dielectric layer; the blocking layer blocks the opening of the first through hole, and the bottom surface of the blocking layer is a preset distance away from the upper surface of the interlayer dielectric layer; the contact hole penetrates through the interlayer dielectric layer; the source electrode fills the contact hole. According to the invention, the cavity structure is arranged in the interlayer dielectric layer, so that the gate-source parasitic capacitance of the device is reduced, and the switching speed of the device is improved.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a shielded gate power device and a preparation method thereof.
Background
In power MOSFET devices, more and more emphasis is placed on the advantages of lower on-resistance, faster switching speed, etc. of shielded gate trench MOSFETs over conventional trench MOSFETs. As shown in fig. 1 and 2, a schematic cross-sectional structure of a shielded gate trench MOSFET and another schematic cross-sectional structure of a shielded gate trench MOSFET respectively include a semiconductor layer 01, a trench 011, a dielectric layer 012, a shielded gate layer 013, a gate dielectric layer 02, an isolation dielectric layer 03, a gate conductive layer 04, an interlayer dielectric layer 05, a contact hole 051 and a source 06, wherein the source of the shielded gate trench MOSFET covers the upper surface of the interlayer dielectric layer (Inter Layer Dielectric, abbreviated as ILD) above the gate conductive layer, that is, the interlayer dielectric layer is located between the source and the gate, so that the gate and the source are located between themThe facing area between the two electrodes increases, resulting in a parasitic capacitance C between the gate and the source gs The input capacitance of the device is increased, the switching speed of the device is reduced, and the switching loss of the device is increased.
At present, the parasitic capacitance of the gate source between the gate and the source is usually reduced by increasing the thickness of the interlayer dielectric layer, but as the interlayer dielectric layer is thickened, the aspect ratio of the contact hole is increased, the difficulty of the filling process of the contact hole is increased, the quality of the source for filling the contact hole is reduced, and the reliability of the device is reduced.
Therefore, there is an urgent need to find a shielded gate power device that does not need to reduce the parasitic capacitance of the gate source of the device by increasing the thickness of the interlayer dielectric layer.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a shielded gate power device and a method for manufacturing the same, which are used for solving the problem that in the prior art, the shielded gate power device is difficult to fill a contact hole due to the reduction of the parasitic capacitance of a gate source by increasing the thickness of an interlayer dielectric layer.
To achieve the above and other related objects, the present invention provides a method for manufacturing a shielded gate power device, including the steps of:
providing a semiconductor layer, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
sequentially forming a dielectric layer positioned on the inner wall and the bottom surface of the groove and the shielding gate layer positioned in the groove, wherein the dielectric layer wraps the side wall and the bottom surface of the shielding gate layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding gate layer;
forming a gate dielectric layer covering the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer, forming a gate conducting layer filling the groove, and wrapping the side wall and the bottom surface of the gate conducting layer by the gate dielectric layer;
forming an interlayer dielectric layer covering the upper surfaces of the gate dielectric layer and the gate conductive layer, and forming a plurality of first through holes and a plurality of second through holes penetrating through the interlayer dielectric layer, wherein the bottom surfaces of the first through holes expose the upper surface of the gate conductive layer, and the bottom surfaces of the second through holes expose the upper surface of the semiconductor layer between two adjacent grooves;
forming a blocking layer on the exposed surface of the interlayer dielectric layer to obtain a cavity structure composed of the blocking layer, the first through hole and the gate conducting layer, wherein the bottom surface of the blocking layer in the first through hole extends to a preset distance away from the upper surface of the interlayer dielectric layer, and thinning the blocking layer;
and forming a contact hole based on the second through hole, and forming a source electrode filling the contact hole.
Optionally, after the gate conductive layer is formed, before the interlayer dielectric layer is formed, a step of forming a first conductive type source region and a second conductive type base region on an upper surface layer of the semiconductor layer between two adjacent trenches is further included, and the source region is located on the upper surface layer of the base region.
Optionally, a lower surface of the gate conductive layer is lower than a lower surface of the base region.
Optionally, the method of forming the first via includes dry etching.
Optionally, the method for forming the blocking layer comprises chemical vapor deposition and physical vapor deposition.
The invention also provides a power MOSFET comprising:
the upper surface layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
the dielectric layer is positioned on the inner wall and the bottom surface of the groove;
the shielding grid layer is positioned in the groove, the dielectric layer wraps the side wall and the bottom surface of the shielding grid layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding grid layer;
a gate dielectric layer covering the inner wall of the trench, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer;
the gate conducting layer fills the groove, and the gate dielectric layer wraps the side wall and the bottom surface of the gate conducting layer;
the interlayer dielectric layer covers the upper surfaces of the gate dielectric layer and the gate conducting layer, and a plurality of first through holes penetrating through the interlayer dielectric layer and exposing the upper surface of the gate conducting layer are formed in the interlayer dielectric layer;
the blocking layer is used for blocking the opening of the first through hole, the bottom surface of the blocking layer is a preset distance away from the upper surface of the interlayer dielectric layer, and a cavity structure is formed by the blocking layer, the first through hole and the gate conducting layer;
the contact hole penetrates through the interlayer dielectric layer above the semiconductor layer between two adjacent grooves;
and the source electrode fills the contact hole.
Optionally, the aspect ratio of the first through hole is greater than the aspect ratio of the trench, and the aspect ratio of the first through hole is greater than the aspect ratio of the contact hole.
Optionally, the opening shape of the first through hole includes a circle shape and a quadrilateral shape.
Optionally, the first through holes are arranged in an array.
Optionally, the upper surface layer of the semiconductor layer between two adjacent trenches is further provided with a first conductive type source region and a second conductive type base region, and the source region is located on the upper surface layer of the base region.
As described above, in the shielded gate power device and the method for manufacturing the same, the plurality of first through holes penetrating through the interlayer dielectric layer and having a high aspect ratio are arranged in the interlayer dielectric layer region above the gate conductive layer, and the blocking layer for blocking the opening of the first through holes is formed, and the blocking layer, the first through holes and the gate conductive layer are surrounded to form a cavity structure; the cavity structure reduces the gate-source parasitic capacitance of the device, and the distance between the gate conducting layer and the source electrode is increased without increasing the thickness of the interlayer dielectric layer, so that the gate-source parasitic capacitance of the device is reduced, the aspect ratio of the contact hole is guaranteed, the filling difficulty of the source electrode for filling the contact hole is reduced, the quality of the source electrode for filling the contact hole is improved, the reliability of the device is improved, and the device has high industrial utilization value.
Drawings
Fig. 1 is a schematic view showing a cross-sectional structure of a trench portion of a shielded gate trench MOSFET.
Fig. 2 shows another cross-sectional structure of a trench portion of a shielded gate trench MOSFET.
Fig. 3 shows a process flow diagram of a method of fabricating a shielded gate power device of the present invention.
Fig. 4 is a schematic cross-sectional view showing the structure of a semiconductor layer of a method for manufacturing a shielded gate power device according to the present invention.
Fig. 5 is a schematic cross-sectional structure of a shield gate power device according to the present invention after a dielectric material layer is formed.
Fig. 6 is a schematic cross-sectional view of a manufacturing method of a shielded gate power device according to the present invention after forming a shielding gate material layer.
Fig. 7 is a schematic cross-sectional structure of a shield gate power device according to the present invention after a dielectric layer is formed.
Fig. 8 is a schematic cross-sectional structure of a gate dielectric layer formed in the method for manufacturing a shielded gate power device according to the present invention.
Fig. 9 is a schematic cross-sectional view of a manufacturing method of a shielded gate power device according to the present invention after forming a gate conductive material layer.
Fig. 10 is a schematic cross-sectional view of a manufacturing method of a shielded gate power device according to the present invention after forming a gate conductive layer.
Fig. 11 is a schematic cross-sectional structure of the shielding gate power device according to the present invention after forming the first via.
Fig. 12 is a schematic diagram of a top structure of an interlayer dielectric layer located above a gate conductive layer after forming a first via in the method for manufacturing a shielded gate power device according to the present invention.
Fig. 13 is a schematic cross-sectional structure of the shielded gate power device according to the present invention after forming a contact hole.
Fig. 14 is a schematic cross-sectional view of a manufacturing method of a shielded gate power device according to the present invention after forming a source.
Description of the reference numerals
01. Semiconductor layer
011. Groove(s)
012. Dielectric layer
013. Shielding grid layer
02. Gate dielectric layer
03. Isolation dielectric layer
04. Gate conductive layer
05. Interlayer dielectric layer
051. Contact hole
06. Source electrode
1. Semiconductor layer
11. Groove(s)
12. Dielectric layer
13. Shielding grid layer
14. Dielectric material layer
15. Shielding gate material layer
2. Gate dielectric layer
3. Gate conductive layer
31. Gate conductive material layer
4. Interlayer dielectric layer
41. First through hole
42. Second through hole
5. Plugging layer
51. Contact hole
6. Source electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3 to 14. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for preparing a shielded gate power device, as shown in fig. 3, which is a process flow chart of the method for preparing the shielded gate power device, and includes the following steps:
s1: providing a semiconductor layer, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
s2: forming a dielectric layer positioned on the inner wall and the bottom surface of the groove and the shielding grid layer positioned in the groove in sequence, wherein the dielectric layer wraps the side wall and the bottom surface of the shielding grid layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding grid layer;
s3: forming a gate dielectric layer covering the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer, forming a gate conducting layer filling the groove, and wrapping the side wall and the bottom surface of the gate conducting layer by the gate dielectric layer;
s4: forming an interlayer dielectric layer covering the upper surfaces of the gate dielectric layer and the gate conductive layer, and forming a plurality of first through holes and a plurality of second through holes penetrating through the interlayer dielectric layer, wherein the bottom surfaces of the first through holes expose the upper surface of the gate conductive layer, and the bottom surfaces of the second through holes expose the upper surface of the semiconductor layer between two adjacent grooves;
s5: forming a blocking layer on the exposed surface of the interlayer dielectric layer to obtain a cavity structure composed of the blocking layer, the first through hole and the gate conducting layer, wherein the bottom surface of the blocking layer in the first through hole extends to a preset distance away from the upper surface of the interlayer dielectric layer, and thinning the blocking layer;
s6: and forming a contact hole based on the second through hole, and forming a source electrode filling the contact hole.
Referring to fig. 4 to 7, the steps S1 and S2 are performed: providing a semiconductor layer 1, wherein a plurality of grooves 11 with upward openings and arranged at intervals along the X direction are formed in the upper surface layer of the semiconductor layer 1; the dielectric layer 12 located on the inner wall and the bottom surface of the trench 11 and the shielding gate layer 13 located in the trench 11 are sequentially formed, the dielectric layer 12 wraps the side wall and the bottom surface of the shielding gate layer 13, and the upper surface of the dielectric layer 12 is lower than the upper surface of the shielding gate layer 13.
Specifically, as shown in fig. 4, a schematic cross-sectional structure of the semiconductor layer 1 is shown, and the semiconductor layer 1 includes a first conductivity type substrate (not shown) and a first conductivity type drift region (not shown).
Specifically, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.
Specifically, the doping concentration of the substrate is greater than the doping concentration of the drift region, and the doping concentration of the substrate can be selected according to practical situations without limitation under the condition that the device performance and the doping concentration of the substrate are ensured to be greater than the doping concentration of the drift region; the doping concentration of the drift region may be selected according to practical situations, and is not limited here.
Specifically, the substrate may be made of silicon, silicon germanium, silicon carbide or other suitable semiconductor materials.
Specifically, the thickness of the substrate may be selected according to the actual situation, and the thickness of the drift region may be not limited.
Specifically, the trench 11 is located in the drift region, and the depth and the opening size of the trench 11 may be selected according to the actual situation under the condition of ensuring the device performance, which is not limited herein. The depth here refers to the distance between the bottom surface of the trench 11 and the opening of the trench 11 (i.e., the upper surface of the semiconductor layer 1).
Specifically, the distance between two adjacent trenches 11 in the X direction may be selected according to the actual situation, while ensuring the device performance, and is not limited here.
Specifically, the step of forming the dielectric layer 12 further includes the step of forming a dielectric material layer 14 covering the upper surface of the semiconductor layer 1 and the inner walls and the bottom surface of the trench 11.
Specifically, as shown in fig. 5, to schematically illustrate the cross-sectional structure of the dielectric material layer 14 after forming the dielectric material layer 14, the method for forming the dielectric material layer 14 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the material of the dielectric material layer 14 includes silicon oxide, silicon nitride or other suitable dielectric materials.
Specifically, the thickness of the dielectric material layer 14 covering the inner wall of the trench 11 may be selected according to the actual situation, while ensuring the device performance, and is not limited.
Specifically, as shown in fig. 6, after forming the dielectric material layer 14, and before forming the dielectric layer 12, the step of forming the shield gate material layer 15 that covers the upper surface of the dielectric material layer 14 and fills the trench 11 is further included.
Specifically, the method of forming the barrier gate material layer 15 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the material of the shielding gate material layer 15 includes polysilicon or other suitable conductive material.
Specifically, forming the dielectric layer 12 and the shielding gate layer 13 includes the following steps: removing the shielding gate material layer 15 covering the upper surface of the dielectric material layer 14 and the top of the trench 11 to obtain the shielding gate layer 13 with a preset height; the dielectric material layer 14 covering the upper surface of the semiconductor layer 1 and the top inner wall of the trench 11 is removed to obtain the dielectric layer 12 having an upper surface lower than the upper surface of the shield gate layer 13.
Specifically, the method for removing the shielding gate material layer 15 covering the upper surface of the dielectric material layer 14 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods; the method of removing the shield gate material layer 15 on top of the trench 11 includes dry etching, wet etching or other suitable method.
Specifically, the height of the shielding gate layer 13 may be selected according to the actual situation, while ensuring the device performance, which is not limited. The height here refers to the distance from the bottom surface of the shield gate layer 13 to the upper surface of the shield gate layer 13.
Specifically, the method for removing the dielectric material layer 14 covering the upper surface of the semiconductor layer 1 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods; the method of removing the dielectric material layer 14 on the top inner wall of the trench 11 may include dry etching, wet etching, or other suitable method
Specifically, as shown in fig. 7, in order to schematically illustrate the cross-sectional structure of the dielectric layer 12 after formation, the distance from the upper surface of the dielectric layer 12 to the upper surface of the shielding gate layer 13 may be selected according to practical situations, and is not limited herein.
Referring to fig. 8 to 12, the steps S3 and S4 are performed: forming a gate dielectric layer 2 covering the inner wall of the groove 11, the upper surface of the dielectric layer 12 and the exposed surface of the shielding gate layer 13, forming a gate conductive layer 3 filling the groove 11, wherein the gate dielectric layer 2 wraps the side wall and the bottom surface of the gate conductive layer 3; an interlayer dielectric layer 4 is formed to cover the gate dielectric layer 2 and the upper surface 3 of the gate conductive layer, a plurality of first through holes 41 and a plurality of second through holes 42 are formed to penetrate through the interlayer dielectric layer 4, and the bottom surfaces of the first through holes 41 expose the upper surface of the gate conductive layer 3.
Specifically, as shown in fig. 8, to schematically illustrate the cross-sectional structure of the gate dielectric layer 2 after forming the gate dielectric layer 2, the method for forming the gate dielectric layer 2 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the thickness of the gate dielectric layer 2 may be selected according to practical situations under the condition of ensuring the performance of the device, which is not limited herein.
Specifically, the gate dielectric layer 2 is made of silicon oxide, silicon nitride or other suitable dielectric materials.
Specifically, forming the gate conductive layer 3 includes the steps of: forming a gate conductive material layer 31 covering the upper surface of the gate dielectric layer 2 and filling the trench 11; and removing the gate conductive material layer 31 covering the upper surface of the gate dielectric layer 2 to obtain the gate conductive layer 3 in the trench 11.
Specifically, as shown in fig. 9, to schematically illustrate the cross-sectional structure of the gate conductive material layer 31 after forming the gate conductive material layer 31, the method for forming the gate conductive material layer 31 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the method for removing the gate conductive material layer 31 covering the upper surface of the gate dielectric layer 2 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.
As an example, after the gate conductive layer 3 is formed and before the interlayer dielectric layer 4 is formed, a step of forming a first conductivity type source region (not shown) and a second conductivity type base region (not shown) on an upper surface layer of the semiconductor layer 1 between two adjacent trenches 11 is further included.
Specifically, the method of forming the base region includes ion implantation or other suitable method.
Specifically, under the condition of ensuring the performance of the device, the doping concentration and thickness of the base region can be selected according to practical situations, and the method is not limited. The thickness here refers to the distance between the lower surface of the base region and the upper surface of the base region.
Specifically, the method of forming the source region includes ion implantation or other suitable method.
Specifically, the doping concentration of the source region is greater than that of the drift region, and the doping concentration, size, thickness and shape of the source region can be selected according to practical situations under the condition of ensuring the performance of the device, which is not limited. The thickness here refers to the distance between the lower surface of the source region and the upper surface of the source region.
As an example, the lower surface of the gate conductive layer 3 is lower than the lower surface of the base region, that is, the lower surface of the gate conductive layer 3 has a position height smaller than the position height of the lower surface of the base region, where the position height of the lower surface of the gate conductive layer 3 refers to the distance between the gate conductive layer 3 and the bottom surface of the semiconductor layer 1, and the position height of the lower surface of the base region refers to the distance between the lower surface of the base region and the bottom surface of the semiconductor layer 1.
Specifically, the lower surface of the gate conductive layer 3 is lower than the lower surface of the base region, so that the gate conductive layer 3 can control the opening and closing of the conductive channel in the base region.
Specifically, the method for forming the interlayer dielectric layer 4 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
As an example, as shown in fig. 11 and 12, a schematic cross-sectional structure after forming the first via 41 and a schematic top surface structure of the interlayer dielectric layer 4 above the gate conductive layer 3 after forming the first via 41 are respectively shown, and a method for forming the first via 41 includes dry etching or other suitable methods. In this embodiment, since the dry etching has good anisotropy, the first via hole 41 is formed by dry etching.
Specifically, the method of forming the second via hole 42 includes dry etching, wet etching, or other suitable methods. In this embodiment, in order to save cost, the first via 41 and the second via 42 are formed simultaneously by dry etching.
Specifically, the first via hole 41 has a high aspect ratio, so that the plugging layer is difficult to fill into the bottom of the first via hole 41 during the process of forming the plugging layer (see fig. 12 later), and only the top of the first via hole 41 can be filled to plug the opening of the first via hole 41. The aspect ratio herein refers to a ratio of the depth of the first via 41 to the opening size of the first via 41.
Referring to fig. 13 to 14, the steps S5 and S6 are performed: forming a blocking layer 5 on the exposed surface of the interlayer dielectric layer 4 to obtain a cavity structure composed of the blocking layer 5, the first through hole 41 and the gate conductive layer 3, wherein the bottom surface of the blocking layer 5 in the first through hole 41 extends to a preset distance from the upper surface of the interlayer dielectric layer 4, and thinning and covering the blocking layer 5; a contact hole 51 is formed based on the second via hole 42, and a source electrode 6 filling the contact hole 51 is formed.
By way of example, the method of forming the blocking layer 5 includes chemical vapor deposition, physical vapor deposition, or other suitable method.
Specifically, the material of the blocking layer 5 includes silicon oxide, silicon nitride or other suitable dielectric materials.
Specifically, since the first via hole 41 has a high aspect ratio, the plugging layer 5 is difficult to fill into the first via hole 41 in the process of forming the plugging layer 5, and only the top of the first via hole 41 can be filled, and then the upper surface layer of the first via hole 41 is plugged, so that the plugging layer 5, the first via hole 41 and the gate conductive layer 3 form a plurality of cavity structures.
Specifically, since the cavity portion in the cavity structure is a vacuum cavity or an air cavity filled with air, and the dielectric constant value of the vacuum and the air is smaller than the dielectric constant values of the interlayer dielectric layer 4 and the blocking layer 5, the formation of the cavity structure in the interlayer dielectric layer 4 above the gate conductive layer 3 results in a decrease in the dielectric properties of the area of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, the method for thinning the blocking layer 5 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.
Specifically, the thickness of the thinned blocking layer 5 may be selected according to practical situations, without limitation, while ensuring device performance.
Specifically, under the condition that the device performance is ensured and the plugging layer 5 can plug the opening of the first through hole 41, the upper surface layer of the interlayer dielectric layer 4 can be thinned while the plugging layer 5 is thinned.
Specifically, the blocking layer 5 is removed while the blocking layer 5 is thinned, so as to expose the upper surface of the conductor layer 1 by removing the blocking layer 5 covering the bottom surface of the second via hole 42 (i.e., the exposed upper surface of the semiconductor layer 1), and the opening size of the via hole of the second via hole 42 is adjusted by using the blocking layer 5, so as to obtain a portion of the contact hole 51 with a suitable size, which is located in the interlayer dielectric layer 4.
Specifically, the semiconductor layer 1 at the bottom of the second via hole 42 is etched based on the second via hole 42 after the via hole opening size is adjusted to form the contact hole 51.
Specifically, the method of etching the semiconductor layer 1 at the bottom of the second via hole 42 includes dry etching, wet etching, or other suitable methods.
Specifically, as shown in fig. 13, the cross-sectional structure of the contact hole 51 is schematically shown after the contact hole 51 is formed, the contact hole 51 penetrates through the source region and the bottom surface exposes the base region.
Specifically, a contact region (not shown) of the second conductivity type is further formed at the bottom of the contact hole 51, and the doping concentration of the contact region is greater than that of the base region.
Specifically, the method of forming the contact region includes ion implantation or other suitable method.
Specifically, the method for forming the source electrode 6 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, as shown in fig. 14, the source electrode 6 is made of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials, which is a schematic cross-sectional structure after the source electrode 6 is formed.
Specifically, the source electrode 6 also covers the upper surface of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, after forming the source electrode 6, a step (not shown) of forming a gate electrode (not shown) and a drain electrode is further included.
Specifically, the gate electrode is electrically connected to the gate conductive layer 3, and the drain electrode is electrically connected to the lower surface of the semiconductor layer 1.
Specifically, the method for forming the gate electrode includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods of forming the drain electrode include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the material of the gate electrode includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials; the drain electrode is made of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials.
Specifically, since the source electrode 6 covers the upper surface of the interlayer dielectric layer 4 above the gate conductive layer 3, the blocking layer 5, the first through hole 41 and the interlayer dielectric layer 4 surround to form the cavity structure, which reduces the dielectric performance of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, since the gate conductive layer 3 is electrically connected to the gate electrode, the parasitic capacitance of the gate source of the deviceWherein S is the opposite effective area of the source electrode 6 and the gate electrode, k is the constant of vacuum electrostatic force, d is the distance between the source electrode 6 and the gate electrode of the device, and the effective dielectric constant epsilon of the dielectric between the source electrode 6 and the gate electrode is caused by the reduction of the dielectric property of the interlayer dielectric layer 4 r Reduced, in turn, reducing the gate-source parasitic capacitance C between the source 6 and the gate gs . The effective dielectric constant of the dielectric here refers to the equivalent dielectric constant of the interlayer dielectric layer 4 between the gate conductive layer 3 and the source electrode 6 and the cavity structure region.
Specifically, due to the formation of the cavity structure in the interlayer dielectric layer 4 above the gate conductive layer 3, the effective dielectric constant of the dielectric between the gate and the source electrode 6 is reduced, the dielectric performance of the dielectric between the gate and the source electrode 6 is not required to be reduced by increasing the thickness of the interlayer dielectric layer 4 (i.e., increasing the distance between the source electrode 6 and the gate electrode), and under the condition that the opening size of the contact hole 51 is fixed, the depth-to-width ratio of the contact hole 51 is not required to be increased, so that the process difficulty of forming the source electrode 6 for filling the contact hole 51 is reduced, the quality of the source electrode 6 for filling the contact hole 51 is ensured, and the reliability of the source electrode 6 is improved.
According to the manufacturing method of the shielded gate power device of the embodiment, after the interlayer dielectric layer 4 is formed and before the contact hole 51 is formed, a plurality of first through holes 41 penetrating through the interlayer dielectric layer 4 are formed in the interlayer dielectric layer 4 covering the upper part of the gate conductive layer 3, the first through holes 41 have a high depth-to-width ratio so as to form the blocking layer 5 for blocking the opening of the first through holes 41, the blocking layer 5 is used for blocking the opening of the first through holes 41, a plurality of cavity structures formed by surrounding the blocking layer 5, the first through holes 41 and the gate conductive layer 3 are formed in the interlayer dielectric layer, and as the cavity part of the cavity structures is air or vacuum, the dielectric property of the interlayer dielectric layer 4 is reduced, and then the dielectric constant of a dielectric between the gate and the source electrode 6 is reduced, so that the gate source parasitic capacitance of the device is reduced; due to the formation of the cavity structure, the reduction of the gate-source parasitic capacitance of the device by increasing the thickness of the interlayer dielectric layer 4 is avoided, the increase of the aspect ratio of the contact hole 51 is not caused under the condition that the opening size of the contact hole 51 is certain, the process difficulty of forming the source electrode 6 for filling the contact hole 51 is reduced, the quality of the source electrode 6 for filling the contact hole 51 is ensured, and the reliability of the source electrode 6 is improved.
Example two
The embodiment provides a shielded gate power device, as shown in fig. 14, which is a schematic cross-sectional structure of the shielded gate power device, and includes a semiconductor layer 1, a dielectric layer 12, a shielded gate layer 13, a gate dielectric layer 2, a gate conductive layer 3, an interlayer dielectric layer 4, a blocking layer 5, a contact hole 51 and a source electrode 6, wherein a plurality of trenches 11 with upward openings and arranged at intervals along an X direction are arranged on an upper surface layer of the semiconductor layer 1; the dielectric layer 12 is positioned on the inner wall and the bottom surface of the groove 11; the shielding gate layer 13 is located in the trench 11, the dielectric layer 12 wraps the side wall and the bottom surface of the shielding gate layer 13, and the upper surface of the dielectric layer 12 is lower than the upper surface of the shielding gate layer 13; the gate dielectric layer 2 covers the inner wall of the trench 11, the upper surface of the dielectric layer 12 and the exposed surface of the shielding gate layer 13; the gate conducting layer 3 fills the groove 11, and the gate dielectric layer 2 wraps the side wall and the bottom surface of the gate conducting layer 3; the interlayer dielectric layer 4 covers the upper surfaces of the gate dielectric layer 2 and the gate conductive layer 3, and a plurality of first through holes 41 penetrating through the interlayer dielectric layer 4 and exposing the upper surface of the gate conductive layer 3 are formed in the interlayer dielectric layer 4; the blocking layer 5 blocks the opening of the first through hole 41, the bottom surface of the blocking layer 5 is a preset distance away from the upper surface of the interlayer dielectric layer 4, and a cavity structure is formed by the blocking layer 5, the first through hole 51 and the gate conducting layer 3; the contact hole 51 penetrates through the interlayer dielectric layer 4 above the semiconductor layer 1 between two adjacent trenches 11; the source electrode 6 fills the contact hole 51.
Specifically, the semiconductor layer 1 includes a first conductivity type substrate and a first conductivity type drift region that are sequentially stacked, where the doping concentration of the drift region is smaller than that of the substrate.
As an example, the upper surface layer of the semiconductor layer 1 between two adjacent trenches 11 is further provided with a first conductivity type source region and a second conductivity type base region, and the source region is located on the upper surface layer of the base region.
Specifically, the doping concentration of the source region is greater than the doping concentration of the drift region.
Specifically, the base region has a bottom surface height greater than that of the gate conductive layer 3 so as to form a conductive channel in the base region.
As an example, the aspect ratio of the first via 41 is greater than the aspect ratio of the trench 11, and the aspect ratio of the first via 41 is greater than the aspect ratio of the contact hole 51.
Specifically, by plugging the plugging layer 5, the first through hole 41, the plugging layer 5 and the gate conductive layer 3 form a cavity structure, and the cavity of the cavity structure is a vacuum cavity or an air cavity.
Specifically, since the dielectric constant value of the cavity portion (i.e., the vacuum cavity and the air cavity) in the interlayer dielectric layer 4 is smaller than the dielectric constant value of the material of the interlayer dielectric layer 4, the dielectric performance of the interlayer dielectric layer 4 between the gate conductive layer 3 and the source electrode 6 is reduced.
As an example, the opening shape of the first through hole 41 includes a circle, a quadrangle, or other suitable shape.
Specifically, the arrangement of the first through holes 41 may be a random arrangement while ensuring the device performance.
As an example, the first through holes 41 are arranged in an array so as to uniformly change the dielectric properties of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, the shielded gate power device is further provided with a gate and a drain, the gate is electrically connected with the gate conductive layer 3, and the drain is electrically connected with the bottom surface of the semiconductor layer 1.
Specifically, the source electrode covers the upper surface of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, the bottom surface of the contact hole 51 exposes the base region, the base region of the bottom surface of the contact hole 51 is further provided with a contact region of a second conductivity type, and the doping concentration of the contact region is greater than that of the base region.
Specifically, the source electrode 6 filling the contact hole 51 forms an ohmic contact with the source region.
Specifically, due to the arrangement of the cavity structure in the interlayer dielectric layer 4 above the gate conductive layer 3, the effective dielectric constant value of the interlayer dielectric layer 4 between the gate conductive layer 3 and the source electrode 6 is reduced, the gate conductive layer 3 is electrically connected with the gate electrode, and the gate-source parasitic capacitance C between the gate electrode and the source electrode is reduced gs 。
Specifically, due to the reduction of the parasitic capacitance of the gate source, the input capacitance of the device is reduced, so that the switching speed of the device is improved, and the switching loss of the device is reduced.
The shielding gate power device of this embodiment sets up by the first through hole 41, the shutoff layer 5 and the cavity structure that the gate conducting layer 3 encloses in the interlayer dielectric layer 4 above the gate conducting layer 3, thereby reducing the dielectric properties of the interlayer dielectric layer 4 between the gate conducting layer 3 and the source electrode 6, and then reducing the gate source parasitic capacitance of the device, improving the switching speed of the device, and reducing the switching loss of the device.
In summary, in the shielded gate power device and the manufacturing method thereof, the plurality of first through holes penetrating through the interlayer dielectric layer are formed in the interlayer dielectric layer above the gate conductive layer, and the plugging layer for plugging the openings of the first through holes is formed at the top of the first through holes, so that the first through holes, the plugging layer and the gate conductive layer are surrounded to form a cavity structure, and through the arrangement of the cavity structure, the parasitic capacitance of the gate source between the gate and the source is reduced, the switching speed of the device is improved, and the switching loss of the device is reduced. In addition, the arrangement of the hollow cavity structure of the interlayer dielectric layer ensures that the gate-source parasitic capacitance of the device is not required to be reduced by increasing the thickness of the interlayer dielectric layer, the depth-to-width ratio of the formed contact hole is ensured, the process difficulty of filling the contact hole is reduced, the quality of a source electrode for filling the contact hole is ensured, and the reliability of the source electrode is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the shielded gate power device is characterized by comprising the following steps of:
providing a semiconductor layer, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
sequentially forming a dielectric layer positioned on the inner wall and the bottom surface of the groove and a shielding grid layer positioned in the groove, wherein the dielectric layer wraps the side wall and the bottom surface of the shielding grid layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding grid layer;
forming a gate dielectric layer covering the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer, forming a gate conducting layer filling the groove, and wrapping the side wall and the bottom surface of the gate conducting layer by the gate dielectric layer;
forming an interlayer dielectric layer covering the upper surfaces of the gate dielectric layer and the gate conductive layer, and forming a plurality of first through holes and a plurality of second through holes penetrating through the interlayer dielectric layer, wherein the bottom surfaces of the first through holes expose the upper surface of the gate conductive layer;
forming a blocking layer on the exposed surface of the interlayer dielectric layer to obtain a cavity structure composed of the blocking layer, the first through hole and the gate conducting layer, wherein the bottom surface of the blocking layer in the first through hole extends to a preset distance away from the upper surface of the interlayer dielectric layer, and thinning the blocking layer;
and forming a contact hole based on the second through hole, and forming a source electrode filling the contact hole.
2. The method for manufacturing the shielded gate power device according to claim 1, wherein: after the gate conductive layer is formed, before the interlayer dielectric layer is formed, the method further comprises the step of forming a first conductive type source region and a second conductive type base region on the upper surface layer of the semiconductor layer between two adjacent grooves, wherein the source region is located on the upper surface layer of the base region.
3. The method for manufacturing the shielded gate power device according to claim 2, wherein: the lower surface of the gate conductive layer is lower than the lower surface of the base region.
4. The method for manufacturing the shielded gate power device according to claim 1, wherein: the method of forming the first through hole includes dry etching.
5. The method for manufacturing the shielded gate power device according to claim 1, wherein: the method for forming the blocking layer comprises chemical vapor deposition and physical vapor deposition.
6. A shielded gate power device, comprising:
the upper surface layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
the dielectric layer is positioned on the inner wall and the bottom surface of the groove;
the shielding grid layer is positioned in the groove, the dielectric layer wraps the side wall and the bottom surface of the shielding grid layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding grid layer;
a gate dielectric layer covering the inner wall of the trench, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer;
the gate conducting layer fills the groove, and the gate dielectric layer wraps the side wall and the bottom surface of the gate conducting layer;
the interlayer dielectric layer covers the upper surfaces of the gate dielectric layer and the gate conducting layer, and a plurality of first through holes penetrating through the interlayer dielectric layer and exposing the upper surface of the gate conducting layer are formed in the interlayer dielectric layer;
the blocking layer is used for blocking the opening of the first through hole, the bottom surface of the blocking layer is a preset distance away from the upper surface of the interlayer dielectric layer, and the blocking layer, the first through hole and the gate conducting layer form a cavity structure;
the contact hole penetrates through the interlayer dielectric layer above the semiconductor layer between two adjacent grooves;
and the source electrode fills the contact hole.
7. The shielded gate power device of claim 6, wherein: the depth-to-width ratio of the first through hole is larger than that of the groove, and the depth-to-width ratio of the first through hole is larger than that of the contact hole.
8. The shielded gate power device of claim 6, wherein: the opening shape of the first through hole comprises a circle and a quadrangle.
9. The shielded gate power device of claim 6, wherein: the first through holes are arranged in an array.
10. The shielded gate power device of claim 6, wherein: the upper surface layer of the semiconductor layer between two adjacent grooves is also provided with a first conduction type source region and a second conduction type base region, and the source region is positioned on the upper surface layer of the base region.
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