CN217590254U - Mining intrinsic safety circuit - Google Patents

Abstract

The utility model discloses a mining intrinsic safety circuit, which comprises a first transistor and a second transistor; the source electrode of the first transistor is connected with the power supply input end, the drain electrode of the first transistor is connected with the power supply output end, and a first resistor is connected between the source electrode and the grid electrode in parallel; a second resistor is connected in parallel between the source electrode and the drain electrode of the first transistor; the drain electrode of the second transistor is connected with the grid electrode of the first transistor; the grid electrode of the second transistor is connected with the control signal input end; the source electrode of the second transistor is grounded, and the first capacitor is connected in parallel with the drain electrode of the first transistor. The utility model discloses can effectively restrict the instantaneous heavy current of the power-on in-process on the equipment, guarantee that equipment can slowly go up smoothly, whole circuit has simple structure, the cost is lower, the practicality is strong advantage simultaneously.

Description

Mining intrinsic safety circuit

Technical Field

The utility model relates to a safety power supply technical field, concretely relates to mining essence safety circuit.

Background

At present, the requirement of mining equipment on intellectualization is higher and higher, the equipment is more and more complex, so the current required by the equipment is also larger and larger, and particularly the instantaneous current of software in the loading process is larger than 2A. The existing mine intrinsic safety circuit cannot well meet the design requirements of equipment on the mine intrinsic safety power supply.

Disclosure of Invention

Not enough to the above-mentioned among the prior art, the utility model provides a mining essence safety circuit.

In order to achieve the purpose of the invention, the technical scheme adopted by the utility model is as follows:

in a first aspect, the utility model provides a mining intrinsic safety circuit, including a first transistor and a second transistor;

the source electrode of the first transistor is connected with the power supply input end, and the drain electrode of the first transistor is connected with the power supply output end; a first resistor is connected in parallel between the source electrode and the grid electrode of the first transistor; a second resistor is connected in parallel between the source electrode and the drain electrode of the first transistor;

the drain electrode of the second transistor is connected with the grid electrode of the first transistor; the grid electrode of the second transistor is connected with the input end of the control signal; the source electrode of the second transistor is grounded, and a first capacitor is connected in parallel with the drain electrode of the first transistor.

Optionally, the first transistor is a PMOS transistor.

Optionally, the second transistor is an NMOS transistor.

In a second aspect, the present invention further provides a mining intrinsically safe circuit, which includes a third transistor and a fourth transistor;

the source electrode of the third transistor is connected with the power supply input end, and the drain electrode of the third transistor is connected with the power supply output end and grounded through a second capacitor; a third capacitor, a third resistor and a fourth resistor which are connected in series are connected in parallel between the source electrode and the grid electrode of the third transistor; a fifth resistor is connected in parallel between the source and the drain of the third transistor;

the drain electrode of the fourth transistor is connected with the connecting end of the third resistor and the fourth resistor; the grid electrode of the fourth transistor is connected with the input end of the control signal; the source of the fourth transistor is grounded.

Optionally, the third transistor is a PMOS transistor.

Optionally, the fourth transistor is an NMOS transistor.

The utility model discloses following beneficial effect has:

the utility model discloses a PMOS transistor and an NMOS transistor to and a parallel resistance, instantaneous heavy current in the electric process on can effectively restricting equipment prevents that the electric current from producing the sudden change, guarantees that equipment can slowly go up smoothly, and whole circuit has simple structure, the cost is lower, the practicality is strong advantage simultaneously.

Drawings

Fig. 1 is a schematic structural diagram of a mining intrinsically safe circuit according to embodiment 1 of the present invention.

Fig. 2 is a schematic structural diagram of a mining intrinsically safe circuit according to embodiment 2 of the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art within the spirit and scope of the present invention as defined and defined by the appended claims.

Example 1

As shown in fig. 1, an embodiment of the present invention provides a mining intrinsically safe circuit, which includes a first transistor Q1 and a second transistor Q2;

the source electrode of the first transistor Q1 is connected with the power supply input end, and the drain electrode of the first transistor Q1 is connected with the power supply output end; a first resistor R1 is connected in parallel between the source electrode and the grid electrode of the first transistor Q1; a second resistor R2 is connected in parallel between the source electrode and the drain electrode of the first transistor Q1;

the drain electrode of the second transistor Q2 is connected with the grid electrode of the first transistor Q1; the grid electrode of the second transistor Q2 is connected with the input end of the control signal; the source of the second transistor Q2 is grounded, and a first capacitor is connected in parallel with the drain of the first transistor.

In an optional embodiment of the present invention, the first transistor is a PMOS transistor, i.e., a P-type metal oxide semiconductor transistor.

In an optional embodiment of the present invention, the second transistor is an NMOS transistor, i.e., an NMOS transistor.

The utility model discloses mining intrinsically safe circuit's of embodiment theory of operation does:

the voltage of the power input terminal is usually 12V input voltage, which is pre-charged to the first capacitor C1 through the second resistor R2, and when the charging reaches a certain rate, the second transistor Q2 is turned on by inputting a high-level control signal to the gate of the second transistor Q2, that is, the source and the drain of the second transistor Q2 are turned on, so that the gate of the first transistor Q1 is grounded. At this time, the source voltage of the first transistor Q1 minus the gate voltage of the first transistor Q1 is greater than the threshold voltage (Vth) of the PMOS transistor conduction, so that the source and the drain of the first transistor Q1 are conducted, and thus the input voltage is loaded to one end of the first capacitor C1, and because the first capacitor C1 is precharged through the second resistor R2 and the voltage of the first capacitor C1 is already close to the input voltage, when the source and the drain of the first transistor Q1 are conducted, an impact current greater than 2A cannot be generated by the first capacitor C1, and thus the safety of an instantaneous current in the power-on process of the mining equipment is ensured.

Example 2

As shown in fig. 2, an embodiment of the present invention provides a mining intrinsically safe circuit, which includes a third transistor Q3 and a fourth transistor Q4;

the source electrode of the third transistor Q3 is connected with the power supply input end, and the drain electrode of the third transistor Q3 is connected with the power supply output end and is grounded through a second capacitor C2; a third capacitor C3, a third resistor R3 and a fourth resistor R4 which are connected in series are connected in parallel between the source and the gate of the third transistor Q3; a fifth resistor R5 is connected in parallel between the source electrode and the drain electrode of the third transistor Q3;

the drain electrode of the fourth transistor Q4 is connected with the connecting end of the third resistor R3 and the fourth resistor R4; the grid electrode of the fourth transistor Q4 is connected with the input end of the control signal; the source of the fourth transistor Q4 is grounded.

In an optional embodiment of the present invention, the third transistor is a PMOS transistor, i.e., a P-type metal oxide semiconductor transistor.

In an optional embodiment of the present invention, the fourth transistor is an NMOS transistor, i.e., an NMOS transistor.

The utility model discloses mining essence safety circuit's theory of operation does:

the voltage at the power input end usually adopts 12V input voltage, and at the moment of inputting 12V voltage, because the voltage at the two ends of the third capacitor C3 cannot change suddenly, the gate voltage of the third transistor Q3 is also 12V, so that the voltage difference between the source voltage and the gate voltage of the third transistor Q3 is zero, and the third transistor Q3 is not turned on; the input 12V voltage is used for pre-charging the second capacitor C2 through the fifth resistor R5, and the fifth resistor R5 has a certain resistance value so that the charging current of the 12V voltage to the capacitor is smaller than 2A; when the charging reaches a certain rate, a high-level control signal is input to the gate of the fourth transistor Q4 to turn on the fourth transistor Q4, that is, the source and the drain of the fourth transistor Q4 are turned on, and the source of the fourth transistor Q4 is grounded, so that the third capacitor C3 is discharged through the fourth resistor R4, and the source voltage of the third transistor Q3 is slowly reduced to 0V, and when the Vgs voltage of the third transistor Q3 is greater than the conducting threshold voltage, the third transistor Q3 is slowly turned on until the third transistor Q3 is completely turned on, so that the input voltage is applied to one end of the second capacitor C2, and since the second capacitor C2 is precharged through the fifth resistor R5 and the voltage of the second capacitor C2 is already close to the input voltage, the voltage of the third transistor Q3 in the turn-on process is slowly raised, and no impact current greater than 2A is generated by the second capacitor C2, thereby ensuring the safety of instantaneous current in the power-on process of the mining equipment.

The principle and the implementation mode of the utility model are explained by applying the specific embodiment, and the explanation of the above embodiment is only used for helping to understand the method and the core idea of the utility model; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention, and it is to be understood that the scope of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations without departing from the spirit of the invention, which fall within the scope of the claims.

Claims (6)

1. A mining intrinsic safety circuit is characterized by comprising a first transistor and a second transistor;

the source electrode of the first transistor is connected with the power supply input end, and the drain electrode of the first transistor is connected with the power supply output end; a first resistor is connected in parallel between the source electrode and the grid electrode of the first transistor; a second resistor is connected in parallel between the source electrode and the drain electrode of the first transistor;

the drain electrode of the second transistor is connected with the grid electrode of the first transistor; the grid electrode of the second transistor is connected with the input end of the control signal; the source electrode of the second transistor is grounded, and a first capacitor is connected in parallel with the drain electrode of the first transistor.

2. The mining intrinsically safe circuit of claim 1, wherein the first transistor is a PMOS transistor.

3. The intrinsically safe circuit of claim 1, wherein the second transistor is an NMOS transistor.

4. A mining intrinsic safety circuit is characterized by comprising a third transistor and a fourth transistor;

the source electrode of the third transistor is connected with the power supply input end, and the drain electrode of the third transistor is connected with the power supply output end and grounded through a second capacitor; a third capacitor, a third resistor and a fourth resistor which are connected in series are connected in parallel between the source electrode and the grid electrode of the third transistor; a fifth resistor is connected in parallel between the source and the drain of the third transistor;

the drain electrode of the fourth transistor is connected with the connecting end of the third resistor and the fourth resistor; the grid electrode of the fourth transistor is connected with the input end of the control signal; the source of the fourth transistor is grounded.

5. The mining intrinsically safe circuit of claim 4, wherein the third transistor is a PMOS transistor.

6. The mining intrinsically safe circuit of claim 4, wherein the fourth transistor is an NMOS transistor.

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