CN210123454U

CN210123454U - Under-voltage detection circuit applicable to low-voltage environment

Info

Publication number: CN210123454U
Application number: CN201920605006.XU
Authority: CN
Inventors: 庄在龙
Original assignee: Nanjing Corner Semiconductor Co Ltd
Current assignee: Nanjing Corner Semiconductor Co Ltd
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2020-03-03
Anticipated expiration: 2029-04-29

Abstract

The utility model provides an under-voltage detection circuit which can be applied to low-voltage environment, comprising a PMOS pipe PM 1; NMOS transistors NM1 and NM 2; inverters I1 and I2; the capacitor CP is connected with the power supply voltage VDD at one end, and is connected with the source end of the NM2 at the other end, wherein NM2 is a low-threshold NMOS transistor. The utility model discloses can use and do not have static consumption under normal operating condition in the low voltage environment.

Description

Under-voltage detection circuit applicable to low-voltage environment

Technical Field

The utility model belongs to integrated circuit design field, concretely relates to under-voltage detection circuit that can be applied to low-voltage environment.

Background

As shown in fig. 1, in a conventional undervoltage detection circuit, three series resistors are used to generate a divided voltage, a positive input terminal of a comparator is connected to a divided voltage point, a negative input terminal of the comparator is connected to a reference voltage, and an output of the comparator is shaped by a phase inverter to generate an undervoltage detection signal, which is effective when the voltage level is low. Meanwhile, the signal end is connected with the grid electrode of the NMOS tube, and the drain electrode of the NMOS tube is connected with the second voltage division point of the voltage division resistor. The source end of the NMOS tube and one end of the third resistor are grounded together. When the detection signal changes to low level, the NMOS tube is disconnected, and rises through the first voltage division point, so that a hysteresis effect is generated.

The resistor and the comparator of the common power-down detection circuit structure consume direct current power consumption in normal work, and the static power consumption of the resistor voltage division part can be reduced by improving the resistor, but the area of the resistor is inevitably increased, so that the common power-down detection circuit structure is not suitable for low-power consumption application. Also, in applications where the supply voltage is relatively low, the reference voltage and the operating state of the comparator are difficult to guarantee, which makes this configuration less suitable for low voltage applications.

SUMMERY OF THE UTILITY MODEL

In order to solve the problem existing in the prior art, the utility model provides a zero-power consumption undervoltage detection circuit that can use in low-voltage environment. The technical scheme of the utility model as follows:

an under-voltage detection circuit applicable to a low voltage environment, comprising:

a PMOS tube PM1 connected to the power supply voltage VDD to output a voltage VP;

an NMOS transistor NM2 to which the voltage VP is input;

an NMOS transistor NM1 and an NMOS transistor NM2 for outputting voltage VQ;

one end of the capacitor CP is connected with a power supply voltage VDD, and the other end of the capacitor CP is respectively connected with NM1 in series;

the secondary inverter is formed by connecting an inverter I1 and an inverter I2 in series, inputs a voltage VP signal and outputs an under-voltage control signal;

the PM1 is respectively connected with an NMOS tube NM2 and a secondary inverter in series;

the NM1, the NM2 and the secondary inverter are sequentially connected in series;

the NM2 employs low threshold NMOS devices.

Specifically, the gate (G) of the PM1 is grounded, the source (S) is connected to the power supply voltage VDD, and the drain (D) of the PM1 is connected to the NM2 drain and to the input of the inverter I1; the source (S) of the NM1 is grounded, the grid (G) is connected with the drain (D) and is connected with the source (S) of the NM2 in common; the gate (G) of the NM2 is grounded, the source (S) is connected with one end of a capacitor CP, and the other end of the capacitor CP is connected with a power supply voltage VDD; the output end of the inverter I1 is connected with the input end of the inverter I2, and the output end of the inverter I2 outputs a brown-out control signal s _ uvb.

Further, the typical threshold voltage of the NM2 is 300-500 mV.

Based on the technical scheme, the utility model discloses the technological effect that can realize does:

1. the utility model is suitable for an under-voltage detection of low voltage environment is used, and power voltage VDD's voltage upset point depends on PM1 and NM 2's size selection, can be decided by the emulation, and its upset point is approximate near PMOS's threshold voltage, is fit for the low pressure and uses.

2. The utility model discloses an under-voltage detection circuit that can be applied to low-voltage environment, when normal during operation, supply voltage VDD is the high level, and NM 1's grid source voltage is only slightly higher than the ground potential, and NM 2's grid source voltage is the negative voltage this moment, helps ending more, and the passageway does not have static consumption.

Drawings

FIG. 1 is a schematic diagram of a conventional common undervoltage detection circuit;

fig. 2 is the utility model discloses a structural schematic diagram of the under-voltage detection circuit that can be applied to low-voltage environment.

Detailed Description

The present invention will be further described with reference to the accompanying drawings, and it is to be understood that the described embodiments are merely illustrative of some, but not all, embodiments of the invention.

As shown in fig. 2, the present embodiment provides an under-voltage detection circuit applicable to a low voltage environment, which includes a PMOS transistor PM 1; NMOS transistors NM1 and NM 2; inverters I1 and I2; a capacitor CP and a supply voltage VDD.

PM1, connected to power supply voltage VDD, and outputting voltage VP;

NM2, input voltage VP;

NM1, NM2, output voltage VQ;

one end of the CP is connected with a power supply voltage VDD, and the other end of the CP is respectively connected with NM1 and NM2 in series;

the two-stage inverter is formed by connecting I1 and I2 in series, inputs a voltage VP signal and outputs an undervoltage control signal;

PM1 is respectively connected with NM2 and the two-stage inverter in series;

NM1, NM2 and the secondary inverter are connected in series in sequence;

NM2 employs low threshold NMOS devices.

Specifically, the gate (G) of PM1 is grounded, the source (S) is connected to the supply voltage VDD, and the drain (D) of PM1 is connected to the NM2 drain and to the input of inverter I1. The source (S) of NM1 is grounded, and the gate (G) is connected to the drain (D) and commonly connected to the source (S) of NM 2. NM2 has a gate (G) grounded, a source (S) connected to one end of a capacitor CP, and the other end of capacitor CP connected to a power supply voltage VDD. The output end of the inverter I1 is connected with the input end of the inverter I2, and the output end of the inverter I2 outputs the undervoltage control signal s _ uvb.

Preferably, the typical threshold voltage of NM2 is 300-500 mV.

Based on foretell structure, the utility model is suitable for an under-voltage detection of low-voltage environment is used, when power supply voltage VDD is the high level, PM1 switches on, the VP electric potential equals with the power supply potential, NM2 ' S grid (G) ground connection, source (S) voltage is NM1 ' S grid source voltage, because there is not direct current to flow through, therefore NM1 ' S grid source voltage only slightly is higher than the ground potential (depends on leakage current and NM1 ' S subthreshold operating condition), NM2 ' S grid source voltage is the negative voltage this moment, help is ending more, thereby guarantee that the passageway does not have static power consumption. The voltage difference between the supply voltage VDD and ground is approximated across the capacitor CP. NM1 and NM2 employ low threshold NMOS devices with typical threshold voltages of 400 mV; therefore, s _ uvb is high and the chip is operating normally.

When the power supply voltage VDD drops, VP drops along with the power supply voltage VDD, and VQ remains low, PM1 gradually enters an off state when the power supply voltage VDD reaches around the threshold of PM1, and VP and VQ gradually enter a high impedance state. When the power supply voltage VDD further drops to reach the inversion voltage, due to the charge holding effect of the capacitor CP and no charge discharging path exists in the VP and VQ paths, the VQ voltage approaches to the negative voltage, at the moment, the source and the drain of the NM1 are exchanged, the gate-source voltage is equal and is completely cut off, the gate-source voltage of the NM2 has a voltage difference, due to the low-threshold device, when the VQ reaches-400 mv, the NM2 is turned on, the VP is pulled down to a low potential, even the negative voltage, and after the VP is shaped by the I1 and the I2, the output s _ uvb is the low potential to provide an under-voltage detection signal.

The utility model discloses a can be applied to the undervoltage detection circuit of low voltage environment, supply voltage VDD's voltage upset point depends on PM1 and NM 2's size selection, can be decided by the emulation, but its upset point is approximate near PMOS threshold voltage, is fit for the low pressure and uses. The common NMOS transistor and PMOS transistor have a threshold difference that is not large, making the detection circuit difficult to trigger, and NM2 uses a low threshold device, which can trigger the undervoltage detection circuit after VDD drops to a certain extent.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims

1. An under-voltage detection circuit applicable to a low-voltage environment, comprising:

an NMOS transistor NM2 to which the voltage VP is input;

an NMOS transistor NM1 and an NMOS transistor NM2 for outputting voltage VQ;

the NM2 employs low threshold NMOS devices.

2. The brown-out detection circuit applicable to a low voltage environment of claim 1, wherein: the gate (G) of the PM1 is grounded, the source (S) is connected with a power supply voltage VDD, the drain (D) of the PM1 is connected with the drain of the NM2 and is connected with the input end of the inverter I1; the source (S) of the NM1 is grounded, the grid (G) is connected with the drain (D) and is connected with the source (S) of the NM2 in common; the gate (G) of the NM2 is grounded, the source (S) is connected with one end of a capacitor CP, and the other end of the capacitor CP is connected with a power supply voltage VDD; the output end of the inverter I1 is connected with the input end of the inverter I2, and the output end of the inverter I2 outputs a brown-out control signal s _ uvb.

3. The brown-out detection circuit applicable to a low voltage environment of claim 1, wherein a typical threshold voltage of the NM2 is 300-500 mV.