CN217543620U

CN217543620U - Array substrate and electrophoresis display panel

Info

Publication number: CN217543620U
Application number: CN202221654216.6U
Authority: CN
Inventors: 熊钦; 孙松; 卢劲松; 王然龙; 刘凯军; 洪文进; 郑浩旋
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-10-04
Anticipated expiration: 2032-06-29

Abstract

The utility model belongs to the technical field of electrophoretic display, concretely relates to array substrate and electrophoretic display panel, array substrate includes the substrate base plate and forms thin film transistor and data line on the substrate base plate, thin film transistor includes grid, first utmost point and second utmost point, first utmost point with the data line is connected, the pixel electrode forms substrate base plate keeps away from one side of grid, just the pixel electrode pass through the via hole with the second utmost point is connected. According to the scheme, the pixel electrode is formed on one side, away from the grid, of the substrate base plate, so that the pixel electrode is prevented from being corroded, the integrity of the pixel electrode is guaranteed, the display effect of the electrophoresis display panel is guaranteed, and the production cost can be reduced.

Description

Array substrate and electrophoresis display panel

Technical Field

The disclosure belongs to the technical field of electrophoretic display, and particularly relates to an array substrate and an electrophoretic display panel.

Background

The electrophoretic display of electronic paper is a novel display technology which utilizes the principle of electrophoresis to realize color alternate display through the movement of charged substances between electrodes under the action of an electric field.

Electrophoresis liquid and electrophoresis particles are arranged between two substrates of an electrophoresis display of a common electronic ink type electrophoresis display and a novel display plasma technology, the electrophoresis liquid or the electrophoresis particles have a corrosion effect on electrodes on the substrates, the driving voltage between the two substrates is influenced, the moving effect of the electrophoresis particles is further influenced, and the problems of poor display effect and the like are caused.

SUMMERY OF THE UTILITY MODEL

An object of the present disclosure is to provide an array substrate and an electrophoretic display panel, which can better protect a pixel electrode and ensure a display effect of the display panel.

The first aspect of the present disclosure provides an array substrate, including a substrate, and a thin film transistor and a data line formed on the substrate, where the thin film transistor includes a gate, a first pole and a second pole, the first pole is connected to the data line, the array substrate further includes a pixel electrode, the pixel electrode is formed on one side of the substrate away from the gate, and the pixel electrode is connected to the second pole through a via hole.

In an exemplary embodiment of the present disclosure, the thin film transistor further includes an active layer located on a side of the gate electrode away from the substrate, and a first insulating layer is disposed between the active layer and the gate electrode;

wherein at least part of the first pole and the second pole is positioned on one side of the active layer far away from the substrate base plate and is overlapped with the active layer.

In an exemplary embodiment of the present disclosure, the via hole sequentially penetrates through the substrate base and the first insulating layer in a direction from the substrate base to the gate, and exposes a portion of the second electrode.

In an exemplary embodiment of the present disclosure, the array substrate further includes a second insulating layer and a planarization layer, the second insulating layer is disposed on a side of the gate electrode away from the substrate and covers the first pole and the second pole; the planarization layer is arranged on one side, far away from the substrate, of the second insulating layer.

In an exemplary embodiment of the present disclosure, the data line, the first pole, and the second pole are disposed at the same layer.

In an exemplary embodiment of the present disclosure, the array substrate further includes a scan line formed on the substrate, and the scan line and the gate electrode are disposed on the same layer.

A second aspect of the present disclosure provides an electrophoretic display panel, including an opposite substrate, electrophoretic particles, and the array substrate of any one of the above, the array substrate and the opposite substrate are arranged in a cassette, and the electrophoretic particles are arranged between the array substrate and the opposite substrate.

In another exemplary embodiment of the present disclosure, retaining walls arranged in an array are disposed between the opposing substrate and the array substrate, the retaining walls are respectively abutted to the opposing substrate and the array substrate, an electrophoretic fluid is disposed between adjacent retaining walls, and the electrophoretic particles are located in the electrophoretic fluid.

In another exemplary embodiment of the present disclosure, an orthographic projection of the retaining wall on the substrate base plate is located within an orthographic projection of the thin film transistor on the substrate base plate.

In another exemplary embodiment of the present disclosure, the opposite substrate includes a transparent substrate, and a common electrode layer and a glue layer disposed on the transparent substrate, the glue layer being disposed on a side of the common electrode layer away from the transparent substrate and covering the common electrode layer; the glue layer is connected with the retaining wall in an abutting mode.

The scheme disclosed by the invention has the following beneficial effects:

the array substrate comprises a substrate, a thin film transistor and a pixel electrode, wherein the pixel electrode is formed on one side of the substrate, which is far away from a grid electrode, so that the pixel electrode is not in direct contact with electrophoretic particles and electrophoretic liquid, the electrophoretic particles or the electrophoretic liquid can be prevented from corroding the pixel electrode, and the pixel electrode is better protected; in addition, the pixel electrode is formed on the side, far away from the grid electrode, of the substrate, the use of an anti-corrosion glue layer can be reduced, and further the production cost can be reduced.

In addition, the electrophoresis display panel comprises an array substrate and an opposite substrate, the pixel electrode on the array substrate is replaced to form a position, electrophoresis particles or electrophoresis liquid between the array substrate and the opposite substrate can be prevented from corroding the pixel electrode, the moving effect of the electrophoresis particles is further ensured, and the display effect of the electrophoresis display panel is ensured; and the use of a glue layer can be reduced, and the production cost is reduced.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural diagram illustrating an array substrate according to a first embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating a structure of an electrophoretic display panel according to a second embodiment of the disclosure;

3a-3g illustrate a schematic flow chart for manufacturing an array substrate according to a second embodiment of the disclosure;

fig. 3a is a schematic structural diagram illustrating a gate formed on a substrate according to a second embodiment of the disclosure;

fig. 3b is a schematic structural diagram illustrating a first insulating layer formed on a gate according to a second embodiment of the disclosure;

fig. 3c is a schematic structural diagram illustrating an active layer formed on the first insulating layer according to a second embodiment of the disclosure;

fig. 3d is a schematic diagram illustrating a structure of forming a first pole and a second pole on an active layer provided in the second embodiment of the disclosure;

fig. 3e illustrates a schematic structural diagram of forming a second insulating layer on the first insulating layer, the first pole and the second pole provided by the second embodiment of the disclosure;

fig. 3f is a schematic structural diagram illustrating a planarization layer formed on the second insulating layer according to the second embodiment of the disclosure;

fig. 3g shows a schematic structural diagram of a substrate provided by the second embodiment of the present disclosure and a via hole opened in the first insulating layer.

Description of reference numerals:

10. an array substrate; 101. a substrate base plate; 1021. a gate electrode; 1022. an active layer; 1023. a first pole; 1024. a second pole; 103. a first insulating layer; 104. a pixel electrode; 105. a via hole; 106. a second insulating layer; 107. a planarization layer; 20. an opposing substrate; 201. a transparent substrate; 202. a common electrode layer; 203. a glue layer; 30. electrophoretic particles; 40. a retaining wall; 100. an electrophoretic display panel.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

In the present disclosure, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood as a specific case by a person of ordinary skill in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.

Example one

The first embodiment of the present application provides an array substrate 10, which can be applied to an electrophoretic display panel, but is not limited thereto.

Referring to fig. 1, the array substrate 10 may include a base substrate 101, and a thin film transistor, a plurality of scan lines, and a plurality of data lines formed on the base substrate 101.

The substrate 101 includes a plurality of pixel units, one pixel unit corresponds to one thin film transistor, the pixel units may be arranged on the substrate 101 in an array along a row direction or a column direction, a plurality of data lines may extend in the column direction and are arranged at intervals in the row direction, and each data line may be connected to one column of pixel units, but is not limited thereto, and may also be connected to two adjacent columns of pixel units, as the case may be.

It should be noted that the data line may include a metal material or an alloy material, such as molybdenum, aluminum, copper, titanium, etc., to ensure good conductivity.

In addition, the substrate base 101 may be a glass base or a PI (polyimide) base,

further, as shown in fig. 1, the thin film transistor may include a gate 1021, an active layer 1022, a first pole 1023 and a second pole 1024, and it should be noted that a first insulating layer 103 may be further disposed between the gate 1021 and the active layer 1022 to insulate the gate 1021 and the active layer 1022 from each other; the first insulating layer 103 can be made of inorganic materials, such as: inorganic materials such as silicon oxide and silicon nitride; in addition, the data line is connected with the first pole 1023, and the first pole 1023, the second pole 1024 and the data line are arranged in the same layer, so that the process steps can be reduced, and the cost can be reduced.

In this application, unless otherwise specified, the term "disposed on the same layer" is used to indicate that two layers, components, members, elements or portions can be formed by the same patterning process, and that the two layers, components, members, elements or portions are generally formed of the same material.

In the present application, unless otherwise specified, the expression "patterning process" generally includes the steps of coating of a photoresist, exposure, development, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, component, or the like using one mask.

The thin film transistor may be a top gate type or a bottom gate type. In the embodiments of the present application, a thin film transistor is mainly used as a bottom gate type.

When the tft is a bottom gate type, for example, the gate 1021 is formed on the substrate 101, and the gate 1021 may include a metal material or an alloy material, such as molybdenum, aluminum, copper, and titanium, to ensure good conductivity; the first insulating layer 103 is formed on the substrate 101 and covers the gate 1021, and the first insulating layer 103 can be made of inorganic materials, such as: inorganic materials such as silicon oxide and silicon nitride; the active layer 1022 is formed on a side of the first insulating layer 103 facing away from the substrate 101, and the active layer 1022 may include a hydrogenated amorphous silicon (a-Si: H) layer and an N-type conductive layer formed at both ends of the hydrogenated amorphous silicon layer and doped at a high concentration; the first pole 1023 and the second pole 1024 are respectively connected to the N-type conductive layer with high concentration doping at two ends of the active layer 1022, and the first pole 1023 and the second pole 1024 may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, copper, titanium, etc., for example, the multi-layer structure is a multi-metal layer stack, such as a titanium, aluminum, copper, titanium three-layer metal stack (Al/Ti/Cu/Al), etc.

It is worth mentioning that the first and

second poles

1023 and 1024 may determine a source electrode and a drain electrode according to a type of the thin film transistor; for example, when the tft is a bottom gate type, the first electrode 1023 is a source and the second electrode 1024 is a drain.

Further, the array substrate 10 may include scan lines extending in the row direction and arranged to intersect the data lines perpendicularly, and the scan lines are disposed on the same layer as the gate 1021 and connected to the gate 1021, and the same layer is disposed on the same layer as the layer, which is not described herein again.

The array substrate 10 further includes a pixel electrode 104, and in order to ensure a display effect, the pixel electrode 104 may be made of a transparent material such as ITO (indium tin oxide), indium Zinc Oxide (IZO), or zinc oxide (ZnO).

As shown in fig. 1, in order to avoid the electrophoretic particles and the electrophoretic liquid in the electrophoretic display panel from corroding the pixel electrode 104, the pixel electrode 104 on the array substrate 10 is formed on the side of the substrate 101 away from the gate 1021, that is, the pixel electrode 104 and the gate 1021 are formed on the opposite side of the substrate 101. In this way, the electrophoretic particles and the electrophoretic liquid can be prevented from contacting the pixel electrode 104, and the pixel electrode 104 can be better protected; in addition, the manufacturing of a glue layer can be reduced by forming the pixel electrode 104 on the side of the substrate 101 away from the gate 1021, and the production cost can be reduced.

Furthermore, as shown in fig. 1, in order to connect the pixel electrode 104 to the second pole 1024, in the direction from the substrate 101 to the gate 1021, the substrate 101 and the first insulating layer 103 are designed to be a via 105, that is, the substrate 101 and the first insulating layer 103 penetrate through, and at least a portion of the surface of the second pole 1024 is exposed at the via 105, so that the pixel electrode 104 can be electrically connected to the second pole 1024 through the via 105, and further, a data signal on a data line can be obtained to obtain a driving voltage.

In addition, as shown in fig. 1, the array substrate 10 further includes a second insulating layer 106 (PV protection layer) and a planarization layer 107 (PFA), the second insulating layer 106 (PV protection layer) is disposed on a side of the gate 1021 away from the substrate 101 and covers the first pole 1023 and the second pole 1024 to better protect the first pole 1023 and the second pole 1024; a planarization layer 107 (PFA) is provided on the side of the second insulating layer 106 (PV protection layer) away from the substrate 101 to further protect the first and

second poles

1023, 1024.

Illustratively, the second insulating layer 106 (PV protection layer) may be made of the same inorganic material as the first insulating layer 103, for example: the inorganic materials such as silicon oxide and silicon nitride can achieve the effect of isolating water and oxygen while playing the role of insulation, thereby ensuring the performance of the thin film transistor.

It should be noted that, in order to ensure the driving effect of the pixel electrode 104, the thickness of the substrate 101 is thinner than that of the conventional substrate 101, and the thickness of the pixel electrode 104 is thicker than that of the pixel electrode 104 on the same side as the gate electrode 1021.

In another alternative embodiment, the pixel electrode 104 may be further disposed between the second insulating layer 106 (PV protection layer) and the planarization layer 107 (PFA), and the pixel electrode 104 is protected by the planarization layer 107 (PFA) to prevent the electrophoretic particles 30 and the electrophoretic solution from corroding the pixel electrode 104.

Example two

The second embodiment of the present disclosure provides an electrophoretic display panel 100, as shown in fig. 2, the electrophoretic display panel 100 includes an opposite substrate 20, electrophoretic particles 30, and an array substrate according to the first embodiment, the array substrate 10 and the opposite substrate 20 are arranged in a pair, and the electrophoretic particles 30 are arranged between the array substrate 10 and the opposite substrate 20.

Furthermore, retaining walls 40 arranged in an array are arranged between the opposite substrate 20 and the array substrate 10, an electrophoretic fluid is arranged between adjacent retaining walls 40, the retaining walls 40 are respectively abutted against the opposite substrate 20 and the array substrate 10, and the electrophoretic particles 30 are located in the electrophoretic fluid.

It should be noted that a pixel unit is formed between adjacent retaining walls 40, and the retaining walls 40 are connected to the opposite substrate 20 and the array substrate 10 in an abutting manner. In this way, the electrophoretic fluid and the electrophoretic particles 30 of the adjacent pixel units can be prevented from mixing with each other, and the display effect of the electrophoretic display panel 100 can be ensured.

The electrophoretic particles 30 and the electrophoretic fluid may be colored charged particles and dyed electrophoretic fluid, or may be particles having two different colors and opposite charges and colorless electrophoretic fluid, and may be designed according to different embodiments, and are not limited herein.

Furthermore, as shown in fig. 2, in order to avoid the blocking wall 40 from affecting the display effect of the electrophoretic display panel 100, the orthographic projection of the blocking wall 40 on the substrate 101 is located in the orthographic projection of the tft on the substrate 101.

That is, as shown in fig. 2, the retaining wall 40 can be located above the first pole 1023; or above the second pole 1024; the gate 1021 may be located above the gate 1021, and may be designed according to different embodiments, which is not limited herein.

For example, the retaining wall 40 is located above the first pole 1023.

In addition, the pixel electrode 104 in one pixel unit should be located between the adjacent retaining walls 40, that is, the adjacent pixel electrodes 104 are not connected to each other, so as to avoid interference between the pixel units and ensure the display effect of the electrophoretic display panel 100.

As shown in fig. 2, in order to drive the electrophoretic particles 30 between the adjacent retaining walls 40 to move, the opposite substrate 20 includes a transparent substrate 201, and a common electrode layer 202 and a glue layer 203 disposed on the transparent substrate 201, and the glue layer 203 is disposed on a side of the common electrode layer 202 away from the transparent substrate 201 and covers the common electrode layer 202. Thus, the electrophoretic liquid or the electrophoretic particles 30 can be prevented from corroding the common electrode, and the common electrode can be better protected. In addition, the glue layer 203 is abutted against the retaining wall 40 to prevent the electrophoretic fluid from leaking outside.

In another alternative embodiment, the common electrode layer 202 on the opposite substrate 20 can also be disposed on the other side of the transparent substrate 201, so that the problem of corrosion of the common electrode layer 202 by the electrophoretic particles 30 or the electrophoretic solution can also be avoided. Thus, the design of the glue layer 203 can be further reduced, thereby reducing the production cost.

The method for manufacturing the electrophoretic display panel 100 is as follows:

the method comprises the following steps: obtaining a first metal layer M1 on the substrate 101 by sputtering (sputter), and exposing and developing the first metal layer M1 to form a gate 1021 and a scan line, as shown in fig. 3 a;

step two: forming a first insulating layer 103 on the side of the first metal layer M1 away from the base substrate 101 by Chemical Vapor Deposition (CVD) plating, as shown in fig. 3 b;

step three: obtaining a second metal layer M2 by sputtering (sputter), and exposing and developing the second metal layer M2 to fabricate a first pole 1023, a second pole 1024 and a data line, as shown in fig. 3c and 3 d;

step four: forming a second insulating layer 106 (PV protection layer) on the side of the second metal layer M2 away from the base substrate 101 by Chemical Vapor Deposition (CVD) plating, as shown in fig. 3 e;

step five: a planarization layer 107 (PFA) is formed by a photolithography process, as shown in fig. 3 f;

step six: coating resin on the planarization layer 107 (PFA), and forming a retaining wall 40 for separating the electrophoretic liquid from the electrophoretic particles 30 by exposure and development;

step seven: coating frame glue, printing the electrophoretic liquid and the electrophoretic particles 30 into the retaining wall 40 in a relief printing mode, then placing the opposite substrate 20 on the other side of the retaining wall 40, and realizing the pair with the array substrate 10, wherein the electrophoretic liquid and the electrophoretic particles 30 are positioned between the opposite substrate 20 and the array substrate 10, and the electrophoretic liquid and the electrophoretic particles 30 are formed between adjacent pixels.

Step eight: via holes 105 are laser drilled into the substrate 101 as shown in fig. 3 g;

step nine: back plating an ITO material on one side of the substrate base plate 101, which is far away from the grid 1021, and manufacturing a pixel electrode 104 through exposure and development;

step ten: and cutting and binding.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present disclosure have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, and therefore all changes and modifications that are intended to be covered by the claims and the specification of this disclosure are within the scope of the patent disclosure.

Claims

1. An array substrate, including substrate base plate and thin film transistor and data line formed on the substrate base plate, the thin film transistor includes grid, first utmost point and second utmost point, the first utmost point with the data line is connected, its characterized in that, the array substrate still includes:

and the pixel electrode is formed on one side of the substrate far away from the grid electrode and is connected with the second pole through a through hole.

2. The array substrate of claim 1, wherein the thin film transistor further comprises an active layer on a side of the gate electrode away from the substrate, and a first insulating layer is disposed between the active layer and the gate electrode;

3. The array substrate of claim 2, wherein the via hole penetrates through the substrate base plate and the first insulating layer in sequence in a direction from the substrate base plate to the gate, and exposes a portion of the second pole.

4. The array substrate of claim 2 or 3, further comprising a second insulating layer and a planarization layer, wherein the second insulating layer is disposed on a side of the gate electrode away from the substrate and covers the first pole and the second pole; the planarization layer is arranged on one side, far away from the substrate, of the second insulating layer.

5. The array substrate of any of claims 1-3, wherein the data line, the first pole, and the second pole are disposed in the same layer.

6. The array substrate of claim 2 or 3, further comprising a scan line formed on the substrate, wherein the scan line and the gate are disposed on the same layer.

7. An electrophoretic display panel comprising a counter substrate, electrophoretic particles, and the array substrate according to any one of claims 1 to 6, wherein the array substrate and the counter substrate are arranged in a cassette, and the electrophoretic particles are arranged between the array substrate and the counter substrate.

8. The electrophoretic display panel according to claim 7, wherein retaining walls arranged in an array are disposed between the opposite substrate and the array substrate, the retaining walls are respectively abutted to the opposite substrate and the array substrate, an electrophoretic fluid is disposed between adjacent retaining walls, and the electrophoretic particles are disposed in the electrophoretic fluid.

9. The electrophoretic display panel of claim 8, wherein an orthographic projection of the dam wall on the substrate is within an orthographic projection of the thin film transistor on the substrate.

10. The electrophoretic display panel according to claim 9, wherein the opposite substrate comprises a transparent substrate, and a common electrode layer and a glue layer provided on the transparent substrate, the glue layer being provided on a side of the common electrode layer away from the transparent substrate and covering the common electrode layer; the glue layer is connected with the retaining wall in an abutting mode.