CN114200726A

CN114200726A - Array substrate, manufacturing method thereof, and display device

Info

Publication number: CN114200726A
Application number: CN202111446932.5A
Authority: CN
Inventors: 王晓洁; 李振亚; 常红燕; 袁海江
Original assignee: HKC Co Ltd; Chuzhou HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chuzhou HKC Optoelectronics Technology Co Ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2022-03-18

Abstract

The array substrate comprises a substrate, a plurality of pixel units and a plurality of data lines, wherein the pixel units are formed on the substrate; the color resistance layer is formed on one side of the thin film transistor, which is far away from the substrate base plate, the edge of the color resistance layer, which is far away from the first pole, is provided with a notch penetrating through the color resistance layer, and the notch is opposite to the part, which is far away from the first pole, of the second pole and exposes part of the second pole; the pixel electrode is formed on one side of the color resistance layer far away from the substrate base plate, and the pixel electrode is connected with the second pole through the notch. The scheme can improve the standing space of the thin film transistor on the color resistance layer, improve the display effect and avoid the condition that the alignment liquid is gathered around the notch to form uneven display brightness.

Description

Array substrate, manufacturing method thereof and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to an array substrate, a manufacturing method of the array substrate and a display device.

Background

In the COA (color filter on array) technology design of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD), namely: the RGB (red, green, blue) color resist layer is formed on the array substrate, and in order to facilitate the switching of the signal lines on the array substrate, a hole is formed in the color resist layer to connect the pixel electrode with the TFT.

Disclosure of Invention

An object of the present application is to provide an array substrate, a method of fabricating the array substrate, and a display device, which overcome one or more of the problems due to the limitations and disadvantages of the related art, at least to some extent.

The application provides an array substrate, which comprises a substrate, a plurality of pixel units and a plurality of data lines, wherein the pixel units and the data lines are formed on the substrate; it is characterized in that the preparation method is characterized in that,

the color resistance layer is formed on one side of the thin film transistor, which is far away from the substrate base plate, the edge of the color resistance layer, which is far away from the first pole, is provided with a notch penetrating through the color resistance layer, and the notch is opposite to the part, which is far away from the first pole, of the second pole and exposes part of the second pole;

the pixel electrode is formed on one side of the color resistance layer far away from the substrate base plate, and the pixel electrode is connected with the second pole through the notch.

In an exemplary embodiment of the present application, the thin film transistor further includes a gate electrode and an active layer, the active layer is located on a side of the gate electrode away from the substrate, and a first insulating layer is disposed between the active layer and the gate electrode;

wherein at least a portion of the first pole and the second pole is located on a side of the active layer away from the substrate base plate and in direct contact with the active layer.

In one exemplary embodiment of the present application, a second insulating layer is disposed between the thin film transistor and the color resistance layer.

In an exemplary embodiment of the present application, a third insulating layer is further disposed between the pixel electrode and the color resistance layer; and an alignment layer is arranged on one side of the pixel electrode, which is far away from the substrate base plate.

In an exemplary embodiment of the present application, the data line, the first pole, and the second pole are disposed at the same layer.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

forming a thin film transistor and a data line on a substrate, wherein the thin film transistor is provided with a first pole and a second pole, and the first pole is connected with the data line;

forming a color resistance layer on one side of the thin film transistor, which is far away from the substrate base plate, wherein the edge of the color resistance layer, which is far away from the first pole, is provided with a notch penetrating through the color resistance layer, and the notch is opposite to the part, which is far away from the first pole, of the second pole and exposes part of the second pole;

and forming a pixel electrode on one side of the color resistance layer, which is far away from the substrate base plate, wherein the pixel electrode is connected with the second pole through the notch.

In another exemplary embodiment of the present application, the forming of the thin film transistor and the data line on the substrate base includes:

forming a grid electrode of a thin film transistor on the substrate base plate;

forming a first insulating layer covering the gate electrode on the substrate base plate;

forming an active layer of the thin film transistor on one side of the first insulating layer, which is far away from the substrate;

and simultaneously forming a data line, a first pole and a second pole of the thin film transistor on the first insulating layer, wherein the first pole and the second pole are at least partially positioned on one side of the active layer, which is far away from the substrate base plate, and are in direct contact with the active layer.

In another exemplary embodiment of the present application, before forming the color resistance layer on the side of the thin film transistor away from the substrate base plate, the manufacturing method further includes:

and forming a second insulating layer on one side of the thin film transistor and the data line far away from the substrate.

In another exemplary embodiment of the present application, the manufacturing method further includes:

before forming a pixel electrode on one side of the color resistance layer far away from the substrate base plate, forming a third insulating layer on one side of the color resistance layer far away from the substrate base plate;

and after a pixel electrode is formed on one side of the color resistance layer, which is far away from the substrate base plate, an alignment layer is formed on one side of the pixel electrode, which is far away from the color resistance layer.

The application also provides a display device, which comprises the array substrate and an opposite substrate arranged opposite to the array substrate in a box.

The scheme of the application has the following beneficial effects:

this application is through forming the breach that supplies pixel electrode and thin film transistor's second pole to be connected in the edge on the look hinders the layer, compares in the second pole connection scheme of designing the through-hole on the look hinders the layer and in order to supply pixel electrode and thin film transistor, makes it not receive or reduce the restriction of exposure board equipment self processing procedure ability (exposure minimum critical dimension), has reduced the design degree of difficulty of breach, simultaneously, still can reduce the influence to thin film transistor occupation space when the breach is designed, promptly: the standing space of the thin film transistor can be improved, so that the thin film transistor can meet the requirements of corresponding products, and then the display effect can be improved.

In addition, since the notch design is not limited by the minimum critical dimension of exposure, when designing the notch, the size of the notch should be reduced as much as possible while the size of the notch satisfies the design rule of the corresponding product, that is: the size of the notch can meet the minimum specified design, and the design can reduce the space occupied by the notch, thereby further improving the standing space of the thin film transistor and improving the display effect; similarly, the notch is arranged at the edge of the color resistance layer, and one side of the notch is open, so that the PI alignment liquid is favorably leaked, the condition that the PI alignment liquid is gathered around the notch to form mura (uneven display brightness) can be avoided, and the display effect is further improved.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic diagram illustrating a stand structure of a thin film transistor according to the present application;

fig. 2 is a schematic plan view illustrating an array substrate according to a first embodiment of the present application;

fig. 3 is a schematic cross-sectional view illustrating an array substrate according to a first embodiment of the present application;

FIG. 4 is a flow chart of a method for manufacturing a second array substrate according to an embodiment of the present disclosure;

fig. 5 is a flowchart illustrating a method for manufacturing a thin film transistor according to a second embodiment of the present application;

fig. 6 is a schematic structural diagram of a display device according to a third embodiment of the present application.

Description of reference numerals:

1. an array substrate; 2. an opposing substrate; 3. a spacer; 4. a liquid crystal layer; 100. a thin film transistor; 101. a gate electrode; 102. a first insulating layer; 103. an active layer; 104a, a first pole; 104b, a second pole; 105. a second insulating layer; 200. a color resist layer; 201. a notch; 300. a third insulating layer; 400. a pixel electrode; 500. an alignment layer; 600. a substrate base plate; 700. and a data line.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

The present application will be described in further detail with reference to the following drawings and specific examples. It should be noted that the technical features mentioned in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

The first embodiment is as follows:

the first embodiment of the present application provides an array substrate, which can be applied to a liquid crystal display device, but is not limited thereto.

The array substrate may include a substrate base substrate 600, and a plurality of pixel cells and a plurality of data lines 700 formed on the substrate base substrate 600.

As shown in fig. 2, a plurality of pixel units may be arranged on the substrate 600 in an array along a first direction X (i.e., a row direction) and a second direction Y (i.e., a column direction), a plurality of data lines 700 may extend in the column direction and be arranged at intervals in the row direction, and each data line 700 may be connected to one column of pixel units, but is not limited thereto, and may also be connected to two adjacent columns of pixel units, as the case may be.

It should be noted that the data line 700 may include a metal material or an alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity.

In the present embodiment, the pixel unit may include a thin film transistor 100, a color resistance layer 200, and a pixel electrode 400.

For example, the plurality of pixel units of the present embodiment may include a red pixel unit, a green pixel unit, and a blue pixel unit, and it should be understood that the color corresponding to the color resist layer 200 in the red pixel unit is red, the color corresponding to the color resist layer 200 in the green pixel unit is green, and the color corresponding to the color resist layer 200 in the blue pixel unit is blue.

In the array substrate, the red pixel units, the green pixel units and the blue pixel units are sequentially arranged in the row direction, and the colors of the adjacent pixel units in the column direction are the same, that is, the arrangement of the pixel units in the array substrate can be that a column of red pixel units, a column of green pixel units and a column of blue pixel units are sequentially and alternately arranged in the row direction.

Since the color of a column of pixel cells is the same, namely: the color of the color resist layer 200 corresponding to a row of pixel units is the same, so the color resist layer 200 can be designed to be a strip-shaped structure extending in the row direction, and the color resist layer 200 corresponds to a row of pixel units.

Further, as shown in fig. 3, the thin film transistor 100 may include a gate 101, an active layer 103, a first pole 104a and a second pole 104b, and it should be noted that a first insulating layer 102 may be further disposed between the gate 101 and the active layer 103 to insulate the gate 101 and the active layer 103 from each other; the first insulating layer 102 can be made of inorganic materials, such as: inorganic materials such as silicon oxide and silicon nitride; in addition, the data line 700 is connected to the first pole 104a, and the first pole 104a, the second pole 104b and the data line 700 are disposed in the same layer, so that the process steps can be reduced, and the cost can be reduced.

In this application, unless otherwise specified, the term "disposed on the same layer" is used to indicate that two layers, components, members, elements or portions can be formed by the same patterning process, and that the two layers, components, members, elements or portions are generally formed of the same material.

In the present application, unless otherwise specified, the expression "patterning process" generally includes the steps of coating of a photoresist, exposure, development, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.

The thin film transistor 100 may be a top gate type or a bottom gate type. In the embodiments of the present application, the thin film transistor 100 is mainly used as a bottom gate type.

When the thin film transistor 100 is a bottom gate type, the gate 101 is formed on the substrate 600, and the gate 101 may include a metal material or an alloy material, such as molybdenum, aluminum, and titanium, to ensure good conductivity; as shown in fig. 3, the first insulating layer 102 is formed on the substrate 600 and covers the gate 101, and the first insulating layer 102 can be made of inorganic materials, such as: inorganic materials such as silicon oxide and silicon nitride; the active layer 103 is formed on a side of the first insulating layer 102 facing away from the substrate 600, and the active layer 103 may include a hydrogenated amorphous silicon (a-Si: H) layer and an N-type conductive layer formed at both ends of the hydrogenated amorphous silicon layer and doped at a high concentration; the first and second poles 104a and 104b are respectively connected to the N-type conductive layer with high concentration doping at two ends of the active layer 103, and the first and second poles 104a and 104b may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal layer stack, such as a titanium, aluminum, titanium three-layer metal stack (Al/Ti/Al), etc.

Further, the array substrate may include a scan line (not shown) extending in a row direction and arranged to cross the data line 700 perpendicularly, and the scan line (not shown) is disposed on the same layer as and connected to the gate electrode 101.

Further, as shown in fig. 2 or fig. 3, a notch 201 is formed on a side of the color resist layer 200 away from the first pole 104a, the notch 201 is opposite to a portion of the second pole 104b away from the first pole 104a and exposes a portion of the second pole 104b, and the pixel electrode 400 disposed on the color resist layer 200 is electrically connected to the second pole 104b through the notch 201.

It should be noted that the notch 201 is opened at the edge of the color resist layer 200, is aligned with the edge line of the color resist layer 200, and has an open side away from the first pole 104 a; in contrast to the manner of providing a closed opening on the photoresist layer 200 shown in fig. 1 (i.e. the opening size is shown at c in fig. 1), the notch 201 shown in fig. 2 in this embodiment is not limited by the process capability (exposure minimum critical dimension) of the exposure apparatus, that is: the design difficulty of the notch 201 is reduced, and meanwhile, the influence on the station space of the thin film transistor 100 (the occupied space of the thin film transistor 100 can refer to the area a in fig. 1) in the design of the notch 201 can be reduced, that is, the station space of the thin film transistor 100 can be increased, so that the thin film transistor 100 can meet the requirements of corresponding products, and the display effect can be improved; for example, in the present embodiment, the notch 201 shown in fig. 2 is not limited by the minimum critical dimension of the exposure machine, so that the distance at the position b in fig. 1 does not need to be reserved, and thus a larger occupation space is provided for the thin film transistor 100 in the present embodiment, so that the manufactured thin film transistor 100 can meet the performance requirement of the product.

In addition, since the design of the notch 201 is not limited by the minimum critical dimension of exposure, when designing the notch 201, the size of the notch 201 should be reduced as much as possible while the size of the notch 201 satisfies the design rule of the corresponding product, that is, the size of the notch 201 only satisfies the minimum specified design, so that the design can reduce the space occupied by the notch 201, and also can satisfy the connection relationship between the pixel electrode 400 and the second electrode 104b, and further improve the standing space of the thin film transistor 100 and the display effect.

Further, a second insulating layer 105 is further disposed between the color resistance layer 200 and the thin film transistor 100, so that the thin film transistor 100 can be better protected by the second insulating layer 105, and the distance between the pixel electrode 400 and the thin film transistor 100 is increased, thereby reducing coupling and improving display effect.

The array substrate further includes a pixel electrode 400, and in order to ensure a display effect, the pixel electrode 400 may be made of transparent materials such as ITO (indium tin oxide), Indium Zinc Oxide (IZO), and zinc oxide (ZnO); the pixel electrode 400 is disposed above the side of the color resist layer 200 away from the substrate 600, and the pixel motor is connected to the second electrode 104b through the notch 201, it should be understood that, in order to connect the pixel electrode 400 to the second electrode 104b, the second insulating layer 105 is also provided with the corresponding notch 201, and the notch 201 can at least expose a portion of the surface of the second electrode 104b, so that the pixel electrode 400 can be electrically connected to the second electrode 104b through the notch 201.

Further, as shown in fig. 3, a third insulating layer 300 is further disposed between the pixel electrode 400 and the color resistance layer 200, on one hand, to better protect the thin film transistor 100 and the color resistance layer 200, and on the other hand, to increase the distance between the pixel electrode 400 and the thin film transistor 100, to reduce coupling and further improve the display effect.

Illustratively, the second insulating layer 105 and the third insulating layer 300 may be made of the same inorganic material as the first insulating layer 102, for example: inorganic materials such as silicon oxide and silicon nitride can insulate and isolate water and oxygen, thereby ensuring the performance of the thin film transistor 100.

Further, an alignment layer 500 is disposed on a side of the pixel electrode 400 away from the substrate 600; in addition, the edge of the color resistance layer 200 is provided with the opening-shaped notch 201, so that the opening-shaped notch is an open ring, which is beneficial to the downward leakage of PI (polyimide) liquid, the PI liquid in the alignment layer 500 is not easy to gather around the opening, the bad problems of mura (uneven display brightness) are avoided, and the display effect is further improved.

Example two

A second embodiment of the present application provides a method for manufacturing an array substrate, where the structure of the array substrate may refer to the structure of the array substrate described in the first embodiment, and details are not repeated here, where as shown in fig. 3 and fig. 5, the method for manufacturing the array substrate includes:

step S1: forming a thin film transistor 100 and a data line 700 on a substrate 600, the thin film transistor 100 having a first pole 104a and a second pole 104b, the first pole 104a being connected to the data line 700;

step S2: forming a color resistance layer 200 on one side of the thin film transistor 100 far away from the substrate 600, wherein the edge of the color resistance layer 200 far away from the first pole 104a is provided with a notch 201 penetrating through the color resistance layer, and the notch 201 is opposite to the part of the second pole 104b far away from the first pole 104a and exposes part of the second pole 104 b;

step S3: forming a pixel electrode 400 on one side of the color resistance layer 200 far away from the substrate base plate 600, wherein the pixel electrode 400 is connected with the second electrode 104b through the notch 201;

step S4: an alignment layer 500 is formed on the side of the pixel electrode 400 away from the color resist layer 200.

Wherein, step S1 specifically includes the following steps:

step S11: depositing a first metal layer on the substrate 600, and performing a first patterning process to form a gate 101 and a scan line (not shown);

step S12: depositing a first insulating layer 102 over a side of the gate 101 remote from the substrate 600;

step S13: forming an active layer 103 of the thin film transistor 100 on a side of the first insulating layer 102 away from the substrate base plate 600;

step S14: a second metal layer is deposited on the first insulating layer 102 away from the substrate 600 and is subjected to a second patterning process to form a first pole 104a and a second pole 104b of the thin film transistor 100, at least a portion of the first pole 104a and the second pole 104b is located on a side of the active layer 103 away from the substrate 600 and is in direct contact with the active layer 103, and the first pole 104a is electrically connected to the data line 700.

Specifically, step S2 specifically includes the following steps:

a second insulating layer 105 is formed on the thin film transistor 100 and the data line 700 on a side away from the base substrate 600.

Specifically, the second insulating layer 105 is covered with the color-resist layer 200, and a third patterning process is performed on the color-resist layer 200, and a notch 201 penetrating through the color-resist layer 200 is formed at an edge of the color-resist layer 200 away from the first pole 104a, where the notch 201 is opposite to a portion of the second pole 104b away from the first pole 104a, and a portion of the second pole 104b is exposed.

It should be noted that, the notch 201 is opened at the edge of the color resist layer 200, and is aligned with the edge line of the color resist layer 200, and the side far away from the first electrode 104a is open, so that compared with the scheme shown in fig. 1 in which a closed through hole is designed on the color resist layer 200 for connecting the pixel electrode 400 and the second electrode of the thin film transistor 100, the design is not limited by or reduces the process capability of the exposure apparatus, the design difficulty of the notch 201 is reduced, and meanwhile, the influence on the occupied space of the thin film transistor 100 when the notch 201 is designed can also be reduced, that is: the standing space of the thin film transistor 100 can be improved, so that the thin film transistor 100 can meet the requirements of corresponding products, and the display effect can be improved.

Further, a third insulating layer 300 is formed on the side of the color resist layer 200 away from the base substrate 600; covering a transparent conductive film on the third insulating layer 300, and performing a fourth patterning process on the transparent conductive film to form a pixel electrode 400, wherein the pixel electrode 400 is electrically connected with the second electrode 104b through a gap 201 formed in the color resist layer 200;

it should be understood that, in order to electrically connect the pixel electrode 400 and the second electrode 104b, an opening is also required on the third insulating layer 300 so that the pixel electrode 400 is connected to the second electrode 104 b.

It should be noted that the second insulating layer 105 is disposed between the thin film transistor 100 and the color resistance layer 200, and the third insulating layer 300 is disposed between the color resistance layer 200 and the pixel electrode 400, so that the design increases the distance between the pixel electrode 400 and the thin film transistor 100, reduces coupling, and improves the display effect.

Specifically, in step S4, an alignment layer 500 is formed on the side of the pixel electrode 400 away from the color resist layer 200, where the alignment layer 500 may be made of Polyimide (PI) alignment liquid; when PI liquid is used for coating, in this embodiment, since the color resist layer 200 is provided with the notch 201 at the edge, the PI liquid can be prevented from being gathered around the notch 201 to form mura (uneven display brightness) defects, and the display effect is improved.

It should be understood that the above-mentioned manufacturing method provided by the embodiments of the present application should have the same characteristics and advantages as the array substrate provided by the embodiments of the present application, and therefore, the characteristics and advantages of the above-mentioned manufacturing method provided by the embodiments of the present application can refer to the characteristics and advantages of the array substrate described above, and are not described herein again.

It should be noted that although the various steps of the methods in this application are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the shown steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc. Further, some of the above steps may be performed in parallel or sequentially, etc., and are not limited to the specific order of operations described above.

EXAMPLE III

A third embodiment of the present application provides a display device, as shown in fig. 6, which includes an array substrate 1 and an opposite substrate 2 disposed opposite to the array substrate 1, where a specific structure of the array substrate 1 can refer to the content described in the first embodiment, and is not repeated herein.

As shown in fig. 2 and fig. 3, in the array substrate 1 of the display device of the present application, the edge of one side of the color resistance layer 200 away from the first electrode 104a is provided with a notch 201, and the side of the notch 201 away from the first electrode 104a is open, so that the pixel electrode 400 on the third insulating layer 300 is connected to the second electrode 104b through the notch 201, the standing space of the thin film transistor 100 is increased, the coated PI solution is prevented from being collected around the notch 201, and the display effect is improved.

For example, the display device of the embodiment of the present application may be a liquid crystal display device, and therefore, the display device further includes a liquid crystal layer 4 between the array substrate 1 and the opposite substrate 2; the opposite substrate 2 is provided with a black matrix (not shown), and the black matrix is provided with a common electrode layer (not shown), and the common electrode layer may be made of indium tin oxide.

In order to maintain the thickness of the display device, a spacer 3 may be provided between the counter substrate 2 and the array substrate 1.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present application have been shown and described, it is understood that the above embodiments are illustrative and should not be construed as limiting the present application and that various changes, modifications, substitutions and alterations can be made therein by those skilled in the art within the scope of the present application, and therefore all changes and modifications that come within the meaning of the claims and the description of the invention are to be embraced therein.

Claims

1. An array substrate comprising a base substrate and a plurality of pixel units and a plurality of data lines formed on the base substrate, the pixel units comprising a thin film transistor, a color resist layer and a pixel electrode, the thin film transistor It has a first pole and a second pole, and the first pole is connected to the data line; it is characterized in that,

The color resist layer is formed on the side of the thin film transistor away from the base substrate, and the edge of the color resist layer away from the first pole has a notch through itself, and the notch is far away from the second pole A part of the first pole is opposite and exposes a part of the second pole;

The pixel electrode is formed on a side of the color resist layer away from the base substrate, and the pixel electrode is connected to the second electrode through the gap.

2 . The array substrate according to claim 1 , wherein the thin film transistor further comprises a gate electrode and an active layer, the active layer is located on a side of the gate electrode away from the base substrate, and 2 . A first insulating layer is disposed between the active layer and the gate;

Wherein, at least parts of the first pole and the second pole are located on the side of the active layer away from the base substrate, and are in direct contact with the active layer.

3 . The array substrate of claim 1 , wherein a second insulating layer is disposed between the thin film transistor and the color resist layer. 4 .

4 . The array substrate according to claim 1 , wherein a third insulating layer is further disposed between the pixel electrode and the color resist layer; and the pixel electrode is away from the side of the base substrate. 5 . An alignment layer is also provided.

5 . The array substrate according to claim 1 , wherein the data line, the first pole and the second pole are arranged in the same layer. 6 .

6. A method for fabricating an array substrate, comprising:

forming a thin film transistor and a data line on the base substrate, the thin film transistor has a first electrode and a second electrode, and the first electrode is connected to the data line;

A color resist layer is formed on the side of the thin film transistor away from the base substrate, and the edge of the color resist layer away from the first electrode has a notch through itself, and the notch and the second electrode are far away from the A part of the first pole is opposite and exposes part of the second pole;

A pixel electrode is formed on a side of the color resist layer away from the base substrate, and the pixel electrode is connected to the second electrode through the gap.

7. The method for fabricating an array substrate according to claim 6, wherein the forming the thin film transistors and the data lines on the base substrate comprises:

forming a gate electrode of a thin film transistor on the base substrate;

forming a first insulating layer covering the gate on the base substrate;

forming an active layer of the thin film transistor on a side of the first insulating layer away from the base substrate;

Data lines, first electrodes and second electrodes of thin film transistors are simultaneously formed on the first insulating layer away from the base substrate, and at least part of the first electrodes and the second electrodes are located in the active layer A side away from the base substrate and in direct contact with the active layer.

8 . The manufacturing method of the array substrate according to claim 6 , wherein before the color resist layer is formed on the side of the thin film transistor away from the base substrate, the manufacturing method further comprises: 8 .

A second insulating layer is formed on a side of the thin film transistor and the data line away from the base substrate.

9. The manufacturing method of the array substrate according to claim 6, wherein the manufacturing method further comprises:

Before forming the pixel electrode on the side of the color-resist layer away from the base substrate, forming a third insulating layer on the side of the color-resist layer away from the base substrate;

After the pixel electrode is formed on the side of the color resist layer away from the base substrate, an alignment layer is formed on the side of the pixel electrode away from the color resist layer.

10. A display device, characterized in that it comprises the array substrate according to any one of claims 1 to 5 and a counter substrate arranged in a cell-to-cell manner with the array substrate.