CN217157097U

CN217157097U - Double-bus circuit for realizing multi-master priority control output

Info

Publication number: CN217157097U
Application number: CN202123305873.8U
Authority: CN
Inventors: 李宁; 徐建华
Original assignee: Suzhou Hongxin Integrated Circuit Co ltd
Current assignee: Suzhou Hongxin Integrated Circuit Co ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-08-09
Anticipated expiration: 2031-12-27

Abstract

The utility model discloses a two bus circuit for realizing many master priority control output includes a plurality of masters, first bus circuit, second bus circuit and at least one slave, and the output of each master is connected with the input of first bus circuit, and the output of first bus circuit is connected with the input of second bus circuit, and the output of each master that corresponds on the second bus circuit all links to each other with at least one slave's input. The utility model discloses a set up two bus circuit, one of them bus circuit branch is used for priority to judge and export, and another bus circuit is used for the separation operation to the address to realize a plurality of masters simultaneous input and through the independent output purpose respectively after priority treatment, still can read each master required data in the slave through the buffer memory that sets up between second bus circuit and slave in addition.

Description

Double-bus circuit for realizing multi-master priority control output

Technical Field

The utility model relates to a double bus circuit for realizing many master priority control output belongs to chip logic circuit design technical field.

Background

In the using process of the logic circuit, if a plurality of control end masters exist, when the masters operate the slave, the phenomenon that the plurality of masters send requests to the same slave at the same time is avoided, generally, a bus matrix circuit is used to solve the problem, the same slave is sequentially accessed through the priority set by the bus matrix circuit, but the bus matrix can only output one line for the same slave, when in actual use, some special requirements are met sometimes, for example, the priority needs to be distributed but the plurality of masters need to independently output, and the data required by the respective masters are read, and at this time, the single bus matrix cannot be realized.

Disclosure of Invention

An object of the utility model is to provide a two bus circuit for realizing many master priority control output aims at solving the problem of a plurality of master independent outputs.

In order to achieve the above object, the utility model provides a following technical scheme: a dual bus circuit for realizing multi-master priority control output comprises a plurality of masters, a first bus circuit, a second bus circuit and at least one slave, wherein the output end of each master is connected with the input end of the first bus circuit, the output end of the first bus circuit is connected with the input end of the second bus circuit, and the output end of each corresponding master on the second bus circuit is connected with the input end of the at least one slave.

Further, the above dual-bus circuit for implementing a multi-master priority control output, wherein: the remaining slave is connected to an output terminal on the second bus circuit.

Further, the above dual-bus circuit for implementing a multi-master priority control output, wherein: for the slave connected to all the output terminals of the second bus circuit Arbiter _2, at least one line between the slave and the second bus circuit Arbiter _2 is provided with a buffer.

Further, the above dual-bus circuit for implementing a multi-master priority control output, wherein: the first bus circuit and the second bus circuit both comprise AHB buses and output modules, the AHB buses of the first bus circuit comprise input modules, decoding modules and priority modules, the AHB buses of the second bus circuit comprise input modules and decoding modules, the number of the input ends of the first bus circuit is equal to the number of the masters, the number of the output ends of the first bus circuit and the number of the input ends of the second bus circuit are both one, and the number of the output ends of the second bus circuit is equal to the number of the masters.

The utility model has the advantages that: the utility model discloses a set up two bus circuit, one of them bus circuit branch is used for priority to judge and export, and another bus circuit is used for the separation operation to the address to realize a plurality of masters simultaneous input and through the independent output purpose respectively after priority treatment, still can read each master required data in the slave through the buffer memory that sets up between second bus circuit and slave in addition.

Drawings

FIG. 1 is a schematic diagram of the circuit connection of the present invention;

FIG. 2 is a schematic view of another embodiment of the present invention;

fig. 3 is a schematic diagram of the internal structures of the first bus circuit and the second bus circuit in the embodiment of fig. 1.

Detailed Description

In order to further understand the contents, features and functions of the present invention, the following embodiments are illustrated and described in detail with reference to the accompanying drawings.

Referring to fig. 1 to 3, a dual-bus circuit for implementing multi-master priority control output according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1 to fig. 3, the utility model discloses a plurality of masters, first bus circuit, second bus circuit and at least one slave, the output of each master is connected with first bus circuit Arbiter _ 1's input, first bus circuit Arbiter _ 1's output is connected with second bus circuit Arbiter _ 2's input, second bus circuit Arbiter _ 2's output quantity equals with master quantity, the output of each master that corresponds on second bus circuit Arbiter _2 all links to each other with one of them slave's input, all the other slaves can select to link to each other with each output on second bus circuit Arbiter _2, also can select to link to each other with a certain output on second bus circuit Arbiter _ 2. At least one line between each maser output end and each slave corresponding to the second bus circuit Arbiter _2 is provided with a cache.

Example 1

As shown in fig. 1 and 3, there are two masters, two slave are provided, output terminals of the two masters are connected to the first bus circuit Arbiter _1, an output terminal of the first bus circuit Arbiter _1 is connected to an input terminal of the second bus circuit Arbiter _2, and since there are two masters, two communication lines are provided between the second bus circuit Arbiter _2 and the slave1, wherein a cache (cache) is connected between an output terminal of the second bus circuit Arbiter _2 corresponding to the master1 and an input terminal of the slave1, and data can be read from the slave through the cache, that is, data required by the master1, and the other data can be read through the slave 1. Of course, a cache may also be provided on another line.

In addition, since the connection between the second bus circuit and the slave1 can realize the independent output of the master1 and the master2 and read the corresponding required data, what connection method is adopted by the slave2 is not flexible, and the slave2 may be connected to one of the output terminals of the second bus circuit Arbiter _2 (i.e. the connection method in fig. 1), or the input terminal of the slave2 may be connected to two output terminals of the second bus circuit Arbiter _2 (not shown in fig. 1).

It should be noted that the number of masters may be greater than two, as long as a corresponding line is added between the second bus circuits Arbiter _2 and slave for outputting the extra data of the mat, which may specifically refer to the following embodiment.

Example 2

As shown in fig. 2, there are three masters, one slave is provided, output terminals of the three masters are connected to the first bus circuit Arbiter _1, an output terminal of the first bus circuit Arbiter _1 is connected to an input terminal of the second bus circuit Arbiter _2, and three output terminals are provided between the second bus circuit Arbiter _2 and the slave because of the three masters, wherein a cache (cache) is connected between an output terminal of the second bus circuit Arbiter _2 corresponding to the master1 and a corresponding input terminal of the slave, and between an output terminal of the second bus circuit Arbiter _2 corresponding to the master2 and a corresponding input terminal of the slave, and data can be read from the slave through the cache, that is, data required by the master1 and the second master2, and data required by the slave 3 are read through the slave. Of course, a buffer may also be provided on each communication line between the second bus circuit Arbiter _2 and each slave.

As shown in fig. 3, the first bus circuit Arbiter _1 and the second bus circuit Arbiter _2 both include an AHB bus and an output module, the AHB bus of the first bus circuit Arbiter _1 includes an input module, a decoding module, and a priority module, the AHB bus of the second bus circuit Arbiter _2 includes an input module and a decoding module, and the input module mainly functions to store address and control information from an input layer when transmission cannot reach a suitable shared slave immediately. The decoding module is used for determining the output required to complete the access; and the independent decoding modules enable each master to have independent address mapping. The priority module is used for setting the priority of each master, so that subsequent output is facilitated. The output module is used for selecting which master requests the corresponding slave according to the priority arbitration of the master. The number of the input terminals of the first bus circuit Arbiter _1 is equal to the number of the masters, the number of the output terminals of the first bus circuit Arbiter _1 and the number of the input terminals of the second bus circuit Arbiter _2 are both one, and the number of the output terminals of the second bus circuit Arbiter _2 is equal to the number of the masters.

The utility model provides a bus circuit accessible uses the coreconsultant instrument that generates instrument Design Wire to generate, and this instrument can be used for specially generating standard AMBA bus, and the parameter of the bus that generates can select in generating the interface. As shown in fig. 1 to 3, the first bus circuit Arbiter _1 and the second bus circuit Arbiter _2 are both a bus circuit that is a completed bus matrix generated by using a coreconsultant, an output of the first bus circuit Arbiter _1 is directly connected to an input of the second bus circuit Arbiter _2, two masters in fig. 1 are provided, when the two masters access one slave at the same time, the first bus circuit Arbiter _1 is used for judging the priority and then outputting, then the output data is input to the second bus circuit Arbiter _2, and the second bus circuit Arbiter _2 separates the data according to the address range.

Specifically, the priority determination method of the first bus circuit Arbiter _1 is as follows: the priority can be set in a priority module on the first bus circuit Arbiter _1, and is realized by setting a corresponding priority in the priority module on the first bus circuit Arbiter _1, such as inputting 01, which represents that the priority of master1 is greater than that of master 2; 10 represents that the master1 has a priority lower than that of master2, and the priority can also be selected to be a fixed priority or a polling priority when the tool generates a bus matrix, where the polling priority represents: the master priority of the first transmission is automatically reduced to the lowest, and the master priority of the subsequent transmission is gradually increased.

Can see through the above description, the utility model discloses set up two bus circuits, directly link to each other two bus matrix (bus circuit), the output of first bus circuit Arbiter _1 is the input of second bus circuit Arbiter _2, its principle also is split bus matrix's function, when a plurality of masters visit same slave simultaneously, first bus circuit Arbiter _1 only carries out priority and judges and export, second bus circuit Arbiter _2 then only carries out the separation operation to the address, the condition of the data independent output respectively that a bus circuit can't realize two masters has been solved, consequently, use two bus circuits to realize partial function respectively, thereby realize a plurality of masters and input respectively the output purpose after priority is handled simultaneously.

Of course, the above is only a typical example of the present invention, and besides, the present invention can also have other various specific embodiments, and all technical solutions adopting equivalent replacement or equivalent transformation are all within the scope of the present invention as claimed.

Claims

1. A dual bus circuit for implementing multiple master priority control outputs, characterized by: the master control circuit comprises a plurality of masters, a first bus circuit, a second bus circuit and at least one slave, wherein the output end of each master is connected with the input end of the first bus circuit, the output end of the first bus circuit is connected with the input end of the second bus circuit, and the output end of each corresponding master on the second bus circuit is connected with the input end of at least one slave.

2. The dual bus circuit for implementing multiple master priority control outputs of claim 1, wherein: the remaining slave is connected to an output terminal on the second bus circuit.

3. The dual bus circuit for implementing multiple master priority control outputs of claim 1, wherein: for the slave connected to all the output terminals of the second bus circuit Arbiter _2, at least one line between the slave and the second bus circuit Arbiter _2 is provided with a buffer.

4. The dual bus circuit for implementing multiple master priority control outputs of claim 1, wherein: the first bus circuit and the second bus circuit both comprise AHB buses and output modules, the AHB buses of the first bus circuit comprise input modules, decoding modules and priority modules, the AHB buses of the second bus circuit comprise input modules and decoding modules, the number of the input ends of the first bus circuit is equal to the number of the masters, the number of the output ends of the first bus circuit and the number of the input ends of the second bus circuit are both one, and the number of the output ends of the second bus circuit is equal to the number of the masters.