CN118113658A - System on chip, data read-write control method and electronic equipment - Google Patents
System on chip, data read-write control method and electronic equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
The application provides a system on a chip, a data read-write control method and electronic equipment, wherein the system on a chip comprises an arbitration unit, a storage unit, a communication interface and a clock unit, the arbitration unit is respectively connected with the storage unit, the communication interface and the clock unit, and the storage unit is connected with the clock unit; the arbitration unit receives the read-write instruction output by the communication interface and sends the read-write instruction to the storage unit; the arbitration unit determines a clock frequency selection signal according to the interface type of the communication interface and outputs the clock frequency selection signal to the clock unit, wherein the clock frequency selection signal is used for controlling the output frequency of the clock unit; the clock unit outputs a clock signal to the storage unit according to the clock frequency selection signal; the storage unit executes the read-write instruction according to the clock signal and outputs the data read-write result of the read-write instruction to the communication interface. The clock frequency can be adjusted corresponding to the initiator, the design area occupation ratio of the storage unit is reduced, and the access security performance of the system on chip is enhanced.
Description
Technical Field
The application relates to the technical field of storage, in particular to a system on a chip, a data read-write control method and electronic equipment.
Background
The application of the system on chip is more and more diversified, wherein communication between the system on chip and other sponsors is generally realized through communication interfaces, and each communication interface generally needs to set a memory to transmit and receive data. However, with the diversification of functions of the on-chip system, multiple communication interfaces need to be set for the on-chip system to cater to different access clock frequencies, so that the setting of the memory occupies more design space of the on-chip system, the area and the cost of the on-chip system are increased, and the access security performance of the on-chip system is lower.
Disclosure of Invention
The application provides a system-on-chip, a data read-write control method and electronic equipment, and aims to solve the technical problems that in the prior art, the system-on-chip needs to be provided with a plurality of communication interfaces in order to cater to different access clock frequencies, so that the arrangement of a memory occupies more design space of the system-on-chip, the area and the cost of the system-on-chip are increased, the access security performance of the system-on-chip is lower, and the design area occupation ratio of a memory unit is reduced.
In a first aspect, the present application provides a system on a chip, where the system on a chip includes an arbitration unit, a storage unit, a communication interface, and a clock unit, where the arbitration unit is connected with the storage unit, the communication interface, and the clock unit, and the storage unit is connected with the clock unit;
the arbitration unit receives a read-write instruction output by the communication interface and sends the read-write instruction to the storage unit;
The arbitration unit determines a clock frequency selection signal according to the interface type of the communication interface and outputs the clock frequency selection signal to the clock unit, wherein the clock frequency selection signal is used for controlling the output frequency of the clock unit;
The clock unit outputs a clock signal to the storage unit according to the clock frequency selection signal;
And the storage unit executes the read-write instruction according to the clock signal and outputs a data read-write result of the read-write instruction to the communication interface.
In a second aspect, the present application further provides a data read-write control method, applied to any one of the systems on a chip, where the system on a chip includes a communication interface, the method includes:
When a read-write instruction sent by the communication interface is received, confirming a clock frequency selection signal corresponding to the read-write instruction according to the interface type of the communication interface;
executing the read-write instruction according to the clock frequency selection signal, and feeding back a read-write result to the communication interface.
In one possible implementation manner of the present application, the determining, according to the interface type of the communication interface, the clock frequency selection signal corresponding to the read-write command includes:
if at least two read-write instructions are received, determining the read-write sequence of each read-write instruction according to the interface type of each communication interface;
And determining a clock frequency selection signal of each read-write instruction.
In a third aspect, the application also provides an electronic device comprising a system on chip as claimed in any one of the preceding claims
The application provides a system-on-chip, a data read-write control method and electronic equipment, wherein the system-on-chip comprises an arbitration unit, a storage unit, a communication interface and a clock unit, wherein the arbitration unit is respectively connected with the storage unit, the communication interface and the clock unit, and the storage unit is connected with the clock unit; the arbitration unit receives a read-write instruction output by the communication interface and sends the read-write instruction to the storage unit; the arbitration unit determines a clock frequency selection signal according to the interface type of the communication interface and outputs the clock frequency selection signal to the clock unit, wherein the clock frequency selection signal is used for controlling the output frequency of the clock unit; the clock unit outputs a clock signal to the storage unit according to the clock frequency selection signal; and the storage unit executes the read-write instruction according to the clock signal and outputs a data read-write result of the read-write instruction to the communication interface. Namely, the scheme is that the arbitration unit is arranged to receive the read-write instruction output by the communication interface, and different clock frequency selection signals for controlling the output frequency of the clock unit are determined according to the interface type of the communication interface, and further, the clock unit is arranged to output the clock signal to the storage unit according to the clock frequency corresponding to the clock frequency selection signal, and it is understood that the clock signal is output according to the frequency (clock frequency selection signal control) corresponding to the interface type of the communication interface, namely, the frequency of the storage unit receiving the clock signal is set to be the frequency corresponding to the clock frequency selection signal, and the frequency corresponding to the clock frequency selection signal, namely, the signal transmission frequency corresponding to the communication interface; after receiving the clock signal, the storage unit executes the read-write instruction sent by the arbitration unit, so that the read-write frequency of the storage unit can be adaptively adjusted corresponding to different interface types, namely, the system-on-chip can adaptively adjust the clock signal according to the data read-write rate requirements of different communication interfaces, a plurality of sponsors (a plurality of different types of communication interfaces) can share one storage unit, meanwhile, the accuracy and the rationality of the data read-write of the storage unit are ensured, the design quantity of the storage unit is reduced, the design area occupation ratio of the storage unit is further reduced, and meanwhile, the design cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of one of the modules of a system-on-chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another module of the system-on-chip according to an embodiment of the present application;
fig. 3 is a schematic flow chart of one embodiment of a data read-write control method according to the embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application. In order to enable those skilled in the art to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the present application in the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In describing embodiments of the present application, words such as "exemplary" or "such as" are used to mean illustrated, described, or described. Any embodiment or design described as "exemplary" or "such as" in an embodiment of the application is not necessarily to be construed as preferred or advantageous over another embodiment or design. The use of words such as "example" or "such as" is intended to present relative concepts in a clear manner.
In addition, the term "plurality" in the embodiments of the present application means two or more, and in view of this, the term "plurality" may be understood as "at least two" in the embodiments of the present application. "at least one" may be understood as one or more, for example as one, two or more. For example, including at least one means including one, two or more, and not limiting what is included, e.g., including at least one of A, B and C, then what may be included is A, B, C, A and B, A and C, B and C, or A and B and C.
It should be noted that, in the embodiment of the present application, "and/or" describe the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship.
Communication peripherals are widely arranged in a System On Chip (SOC) and a micro control unit (Micro controller Unit, MCU) to complete inter-Chip communication or intra-Chip communication. The MCU is also called a single-chip microcomputer or a single-chip microcomputer, and is configured to appropriately reduce the frequency and specification of a central processing unit, and to convert a memory, a counter, a USB (Universal Serial Bus, abbreviated as USB, i.e., a serial bus) to a serial bus standard, an a/D converter (an analog-to-digital converter, i.e., an a/D converter, or abbreviated as ADC, generally refers to an electronic component for converting an analog signal into a digital signal), and a UART (Universal Asynchronous Receiver/Transmitter: UART, universal asynchronous receiver/transmitter, is a universal serial data bus for asynchronous communications), PLC (Programmable Logic Controller, programmable logic controller is a digital operation electronic system designed specifically for use in an industrial environment), DMA (Direct Memory Access, direct memory access, which is a function provided by some computer bus architecture that enables data to be sent directly from additional devices, such as disk drives, to the memory of a computer motherboard) and other peripheral communication interfaces, even LCD (LASER CLADDING deposition) driver circuits, are integrated on a single chip, forming a chip-level computer. Some communication interfaces, such as CAN (CAN, controller Area Network, controller area network bus, which is a serial communication protocol bus for real-time application, CAN use twisted pair wires to transmit signals, and is one of the most widely used fieldbuses in the world), require a large amount of memory for message data transmission and reception, and the memory size is different according to different requirements of application scenes, and a system on a chip has a plurality of communication peripherals, so that the memory requirement is large, and if a large-capacity implementation is adopted, the cost is increased or the system area is not acceptable. Standing on a single MCU, i.e. the controller, is faced with the need to communicate with a plurality of other devices, and thus with the need for a plurality of memories for data transceiving. An MCU may include a plurality of CAN (bus standard interface), flexRay (FlexRay is a high-speed deterministic vehicle bus system with fault tolerance designed specifically for an in-vehicle lan), and other communication interfaces, and if each interface is allocated a sufficient memory unit, the chip area and cost will be greatly increased.
Therefore, the core of the application is to provide a system on a chip, which comprises an arbitration unit, a storage unit, a communication interface and a clock unit, wherein the arbitration unit is respectively connected with the storage unit, the communication interface and the clock unit, the storage unit is connected with the clock unit, the arbitration unit is used for receiving read-write instructions output by the communication interface, determining different clock frequency selection signals for controlling the output frequency of the clock unit according to the interface types of the communication interface, setting the clock unit to output clock signals to the storage unit according to the clock frequency corresponding to the clock frequency selection signals, further, after the clock signals are received by the storage unit, executing the read-write instructions sent by the arbitration unit according to the clock signals, realizing the adaptive adjustment of the read-write frequency of the storage unit corresponding to different interface types, so that a plurality of originators can share one storage unit, thereby reducing the design quantity of the storage unit, further reducing the design area ratio of the storage unit and reducing the cost of the system on a chip.
Referring to fig. 1, fig. 1 is a schematic structural diagram of one embodiment of a system on chip provided by an embodiment of the present application, specifically, the system on chip includes an arbitration unit 100, a communication interface 200, a storage unit 300, and a clock unit 400, where the arbitration unit 100 is connected to the storage unit 300, the communication interface 200, and the clock unit 400, and the storage unit 300 is connected to the clock unit 400;
The arbitration unit 100 receives the read-write command output by the communication interface 200, and sends the read-write command to the storage unit 300;
The arbitration unit 100 determines a clock frequency selection signal according to the interface type of the communication interface 200, and outputs the clock frequency selection signal to the clock unit 400, where the clock frequency selection signal is used to control the output frequency of the clock unit 400;
The clock unit 400 outputs a clock signal to the memory unit 300 according to the clock frequency selection signal;
The memory unit 300 executes the read-write command according to the clock signal, and outputs the data read-write result of the read-write command to the communication interface 200.
It is understood that the communication interface 200 may be used for a system-on-chip to communicate with an external controller, which may be other chips/systems-on-chip, etc. In some embodiments, the communication interface 200 may also be used for communication between internal subsystems of the system-on-chip, which may be, but are not limited to, peripheral subsystems, CPU subsystems, memory subsystems. By way of example, the communication interface 200 may be, but is not limited to being, a CAN interface, a FlexRay interface, an I2C interface, an I3C interface, an SPI interface, an eSPI interface, a QSPI interface.
It is understood that the arbitration unit 100, the memory unit 300, the communication interface 200, the clock unit 400 may be integrated on the system-on-chip as well as circuit elements, and the clock unit 400 may be a clock circuit, for example, the arbitration unit 100 may be an arbiter arbiter, and the memory unit 300 may be, but is not limited to, ROM, RAM, SRAM, FLASH, EEPROM.
Specifically, the read-write command includes a read command for controlling the erasing of the data of the memory cell 300 and a write command for controlling the writing of the data in the memory cell 300.
Wherein the clock frequency selection signal, i.e. the signal for controlling the output frequency of the clock unit 400, it is understood that the data read/write frequency of the memory unit 300 is controlled by the output clock signal of the clock unit 400, i.e. the clock frequency selection signal is used for controlling the data read/write frequency of the memory unit 300.
It can be understood that the clock frequencies of different initiators for completing the task requirements corresponding to different read/write instructions are different, that is, the data input/output transmission rates of the initiators are different, that is, the communication interfaces 200 with different data transmission frequencies and the storage units 300 with different data read/write frequencies need to be correspondingly set according to different access units. It should be noted that, the initiator is an object that can access the storage unit, and the initiator may be other controllers outside the system on chip, i.e. an external initiator; other subsystems internal to the system-on-chip, i.e., internal initiators, are also possible.
In the embodiment of the present application, an external initiator may communicate with a system on chip through a communication interface 200, an internal initiator may communicate with a storage unit through the communication interface 200, the arbitration unit 100 receives a read-write command output by the initiator based on the communication interface 200, determines a clock frequency selection signal according to an interface type for receiving the read-write command, sends the read-write command to the storage unit 300, and further, the clock unit 400 outputs a clock signal to the storage unit 300 according to the clock frequency selection signal, and after the storage unit 300 receives the read-write command, executes the read-write command according to a receiving frequency of the received clock signal.
Further, on the basis of the above embodiment, the present application further provides an embodiment of the arbitration unit 100 for processing a read-write instruction, in the embodiment of the present application, the arbitration unit 100 receives the read-write instruction output by the communication interface 200, and sends the read-write instruction to the storage unit 300, which specifically includes the steps of:
(1) If the arbitration unit 100 receives the read-write instructions output by at least two communication interfaces 200, determining the read-write sequence of the read-write instructions according to the interface type of each communication interface 200;
(2) The arbitration unit 100 sends each of the read/write instructions to the storage unit 300 according to the read/write order.
Specifically, in the embodiment of the present application, the communication interface 200 includes at least two, that is, at least two initiators may access the chip on a chip at the same time, in order to avoid confusion of reading and writing, the reading and writing instructions need to be ordered according to the interface type receiving the reading and writing instructions, the reading and writing sequence is determined, so that the reading and writing instructions are sent to the storage unit 300 according to the reading and writing sequence, further, a clock frequency selection signal is determined according to the reading and writing sequence, and the clock unit 400 is controlled to output a clock signal to the storage unit 300 according to the corresponding output clock signal, so that the reading and writing unit executes the corresponding reading and writing instructions according to the clock signal corresponding to the reading and writing sequence.
It may be appreciated that the arbitration unit 100 may determine the corresponding read-write sequence according to the preset priority corresponding to the type of the receiving port, and illustratively, when a plurality of initiators send read-write instructions to the arbitration unit 100 at the same time, the arbitration unit 100 determines the type of interface receiving the read-write instructions, determines who (the read-write instructions) is executed first according to the priority value of each preconfigured interface type, and further determines the read-write sequence of each read-write instruction.
Specifically, in one embodiment of the present application, if the arbitration unit 100 receives the read/write commands output by at least two communication interfaces 200, the read/write sequence of each read/write command is determined according to the interface type of each communication interface 200, which specifically includes the steps of:
(1) If the arbitration unit 100 receives the read-write instructions output by at least two communication interfaces 200, the priority corresponding to the interface type of each communication interface 200 is obtained according to a preset rule;
(2) And determining the reading and writing sequence of each reading and writing instruction according to the priority corresponding to the interface type of each communication interface 200.
The preset rule includes at least one relation group, each relation group includes an interface type and a priority, it can be understood that the expression form of the priority is not specifically limited, and the priority can be a level a, a level B … Z, etc., where the level a is the most preferred for reading and writing, and the level Z is the last for reading and writing; the priority may also be represented by a number from 0 to N, with the highest priority being achieved when the configuration value is 0 and, secondly, the smaller number achieving a higher priority when the value is 1.
Specifically, when multiple initiators send read-write instructions to the system on chip at the same time, the arbitration unit 100 determines the corresponding priority of each interface type by searching according to a preset rule, and then the priority orders all received read-write instructions, so as to obtain the read-write sequence of each read-write instruction.
Further, referring to fig. 2, fig. 2 is a schematic structural diagram of one embodiment of the system on chip provided by the present application, where M1 and M2 are communication interfaces 200 for characterizing an external initiator, a CPU is a communication interface 200 for characterizing a corresponding internal CPU initiator, can and FlexRay are communication interfaces 200 for characterizing other internal initiators, in one embodiment of the present application, the storage unit 300 includes at least two storage units 300, each storage unit 300 is connected to the arbitration unit 100, and each storage unit 300 is connected to the clock unit 400.
It may be understood that in this solution, the storage unit 300 may adopt a multi-bank structure, that is, the storage unit 300 is divided into multiple blocks, each bank block is one storage unit 300, so that each block can support a concurrent access mode, different storage units 300 can be used when different senders need to read and write data at the same time, and further, by setting each storage unit 300 to be connected with the clock unit 400, the clock unit 400 outputs a corresponding clock signal for the read and write command of each storage unit 300, so as to control each storage unit 300 to read and write data according to the same or different clock signals.
Further, the arbitration unit 100 may use a standard bus interconnect of multiple masters to one slaver to implement the connection to one memory unit 300. If the multi-Bank memory unit 300 is interconnected by a multi master-to-multi slaver standard bus, the clock unit 400 includes a plurality of output signals for outputting different clock signals.
Further, in the embodiment of the present application, the arbitration unit 100 sends each of the read/write instructions to the storage unit 300 according to the read/write sequence, and specifically includes the steps of:
(1) Acquiring a read-write execution state of each storage unit 300, wherein the read-write execution state comprises a read-write state and an idle state;
(2) The arbitration unit 100 sends each read-write instruction to the target storage unit 300 in the idle state according to the read-write sequence.
Specifically, in one embodiment of the present application, the arbitration unit 100 receives the read-write command output by the communication interface 200, obtains the read-write execution status of each storage unit 300, determines whether the storage unit 300 is executing the read-write command according to the read-write execution status, if the read-write execution status of the storage unit 300 is in an idle status, indicates that the storage unit 300 does not execute the read-write command, if the read-write command includes at least two read-write commands, determines the read-write sequence of the read-write command according to the above embodiment, and further sends each read-write command to the target storage unit 300 in the idle status according to the read-write sequence, so as to implement the step of concurrently accessing the storage unit 300 by multiple initiators.
It may be understood that if the read/write execution state of each memory unit 300 is a read/write state, the read/write command is controlled to be queued according to the read/write sequence, and when any memory unit 300 is detected to be released, the corresponding read/write command is executed according to the read/write sequence, and it may be understood that after the memory unit 300 is released (the read/write command is completed), the read/write state of the memory unit 300 is set to an idle state, so that the arbitration unit 100 determines the read/write execution state of the memory unit 300.
Specifically, in one embodiment of the present application, if there is only one read/write command, but the read/write execution state of the corresponding plurality of memory cells 300 is an idle state, the plurality of memory cells 300 in the idle state may be controlled to execute the read/write command, so as to improve the read/write efficiency.
In an exemplary embodiment of the present application, the storage unit 300 includes A, B, C, for example, an initiator corresponding to a CAN interface uses a memory a, an initiator corresponding to a FlexRay interface uses a memory B, an initiator corresponding to a CPU interface uses a memory C, after the initiator corresponding to the CAN interface writes the memory a, if more memory space is still needed, an alarm may be sent at the same time, notifying the CPU of a risk of space overflow, and the CPU schedules the schedule and waits for the memory B, C to be released for further use. When only one initiator is used, the multi-block storage unit 300 CAN be used simultaneously to rapidly complete data reading and writing, for example, when the initiator corresponding to the CAN interface transfers data with large load, the initiator CAN write the data into the memory A continuously, and in the process of writing the memory B, the initiator CAN initiate a task to read the data of the memory A simultaneously, so that the data processing efficiency CAN be greatly improved.
Further, on the basis of the above embodiment, the present application further provides a specific implementation scheme for determining a clock frequency selection signal according to the interface type of the communication interface 200, which specifically includes the steps of:
(1) If the interface type of the communication interface 200 is a preset interface type, extracting a target read-write type carried by a read-write instruction corresponding to the communication interface;
(2) Inquiring preset association information corresponding to the preset interface type, and acquiring clock frequency selection signals corresponding to the target read-write type, wherein the preset association information comprises at least two preset relation groups, and each preset relation group comprises a read-write type and a clock frequency selection signal.
It can be understood that, due to the diversity of the data interfaces, the interfaces corresponding to the same interface type may process data with different transmission rates corresponding to different read-write command requirements, so that such special interface types may be set as preset interface types, further, in order to determine a specific clock frequency selection signal of the preset interface type, association information may be preset corresponding to each preset interface type, and a correspondence between the preset interface type and the preset association information may be created, where the preset association information includes at least two preset relationship groups, and each preset relationship group includes one read-write type and one clock frequency selection signal.
Specifically, after the arbitration unit 100 receives the read-write instruction, it determines the interface type of the communication interface 200 that receives the read-write instruction, compares the interface type with a preset receiving type, if the interface type of the communication interface 200 is the preset interface type, further extracts the target read-write type carried by the target read-write instruction, acquires preset associated information corresponding to the preset interface type, queries the preset associated information, and acquires a clock frequency selection signal corresponding to the target read-write type.
Further, on the basis of the above embodiment, after the arbitration unit 100 receives the read/write command, it determines the interface type of the communication interface 200 that receives the read/write command, compares the interface type with a preset receiving type, and if the interface type of the communication interface 200 is not the preset interface type, queries a preset mapping table corresponding to the type and the selection signal, and obtains a clock frequency selection signal corresponding to the interface type of the communication interface 200.
Specifically, the preset mapping table corresponding to the type and the selection signal includes at least one mapping group, and each mapping group includes an interface type and a clock frequency selection signal with a mapping relationship.
It will be appreciated that the system on a chip may evaluate the storage performance requirements of the initiator corresponding to each communication interface 200, respectively, how much data volume needs to be processed in the shortest time, and create the clock frequency selection signal corresponding to the interface type according to the data processing volume. By way of example, the system on chip may evaluate the storage performance requirements of the initiator corresponding to the host data corresponding to the CAN interface, the FlexRay interface, the CPU interface, or other receiving ports, and consider that concurrent access tasks (read-write instructions) are executed serially, where the access storage unit 300 needs to meet the data rate requirements of each access unit, and by calculating, the system on chip design improves the access speed of the storage unit 300, where the access speed ensures that the data read-write instructions corresponding to a plurality of different communication devices CAN always be processed within a specified time, thereby meeting the data read-write requirements of different access units within the time of serial execution. Therefore, the clock frequency (clock signal) of the read-write memory unit 300 is designed to be flexibly selected for a plurality of gears to meet different demands of performance and power consumption. The read-write clock frequency implementation of the memory unit 300 supports manual or automatic adjustment, which is accomplished by providing different frequency gear selections by a user software configuration. The clock gear which is automatically adjusted to be matched with the data rate requirement is selected according to the peripheral type and the task type, and the specific method is as follows: the clock frequencies of the initiator corresponding to each interface type for completing different read-write task requirements are calculated in advance, the system clock unit 400 provides all gear frequencies for the storage unit 300 to read and write (i.e. outputs different clock signals for controlling the storage unit 300 to read and write), and when the arbitration unit 100 sees that the read-write instruction corresponds to the request for accessing the storage unit 300, the access clock frequency of the storage unit 300 is automatically switched to the clock frequency matched with the requirements (i.e. the control clock unit 400 outputs the clock signal corresponding to the corresponding clock selection signal). When executing the read-write command corresponding to different interface types, the clock signals required are different, for example, whether the CAN interface corresponding initiator performs data transmission with a CAN FD frame or a CAN2.0 respectively with how large data bytes are transmitted, and the like, the clock frequency requirements are different, at this time, the identification for distinguishing specific different data task types needs to be provided (that is, the CAN interface is connected with a preset interface, if the interface type of the communication interface 200 is the preset interface type, the target read-write type carried by the target read-write command is extracted), the clock frequency selection signal matching the requirements is judged and selected according to the task type identification, and the switching is automatically completed to output the corresponding clock signal.
Further, in one embodiment of the present application, each memory unit 300 is divided into at least two memory areas; that is, after the clipping unit receives the read-write command output by the communication interface 200, the method further includes the steps of:
(1) If the target storage area to be accessed corresponding to the read-write instruction is a preset storage area, acquiring a preset access list corresponding to the target storage area;
(2) Discarding the read-write instruction if the initiator corresponding to the read-write instruction does not belong to the access list;
(3) And if the initiator corresponding to the read-write instruction belongs to the access list, sending the read-write instruction to the storage unit 300.
That is, in order to ensure the security of the storage unit 300, access read-write level control may be set for different areas corresponding to the storage unit 300, for example, a certain initiator needs to access a preset storage area of the storage unit 300, and access can be performed only if an access condition is satisfied; for example, when the initiator may send a read/write instruction to the target storage area, if the target storage area to be accessed corresponding to the read/write instruction is a preset storage area, the arbitration unit 100 determines whether the initiator satisfies an access condition, if the condition is satisfied, the arbitration unit 100 determines that the initiator may initiate access to the corresponding target storage area (i.e., performs the step of sending the read/write instruction to the storage unit 300), and if the condition is not satisfied, the arbitration unit 100 intercepts the read/write instruction.
Specifically, the access condition may be an access permission, and by way of example, an initiator capable of accessing is defined for a certain preset storage area, a preset access list of the preset storage area is generated, when the access condition is applied, if the target storage area to be accessed corresponding to the read-write instruction is the preset storage area, the preset access list corresponding to the target storage area is obtained, and if the initiator corresponding to the read-write instruction does not belong to the access list, the initiator does not have the access permission for the target storage area, and the read-write instruction is discarded; if the initiator corresponding to the read-write instruction belongs to the access list, the initiator has access right to the target storage area, and the read-write instruction is sent to the storage unit 300.
Further, in order to avoid the dangerous initiator accessing the storage unit 300 from affecting the data security of the system on chip, different security levels may be set for different initiators, and in this embodiment, after the arbitration unit 100 receives the read/write command output by the communication interface 200, the method further includes the following steps:
(1) Searching a preset relation table corresponding to the initiator and the security level, and acquiring a target security level of the initiator corresponding to the read-write instruction;
(2) If the target security level is lower than a preset security level, acquiring a read-write password of the initiator corresponding to the read-write instruction;
(3) If the read-write password is the same as the preset storage password corresponding to the storage unit 300, the read-write instruction is sent to the storage unit 300.
It may be appreciated that different security level ratios may be set for different senders to create a corresponding preset relationship table, and when in use, the security level of each sender is confirmed by searching the relationship table, and when the security level is lower, the sender verification is performed by obtaining the read-write password corresponding to the read-write instruction, that is, the arbitration unit 100 may set a protection area for the storage unit 300 or a part of the area in the storage unit 300, specifically, set an opening of the storage area corresponding to the part of the address field as a protection area, and default to be a non-protection area. When the secure area is enabled, the arbitration unit 100 decides the security level of the initiator that sent the read/write instruction, and if it is decided that the security level of the initiator is higher, the access to the secure area is regarded as self-contained, and the access can be unconditionally passed. The memory cell 300 is normally read and written. If the security level is not sufficient, the access from the non-secure area is considered to be from passing through, and if the security detection mechanism is started, the access from the non-secure area is not allowed to pass through. That is, if access from an unsecure area is considered, access rights can only be obtained by secure decryption of the tag. The secure decryption and signature verification process is, for example, predefined good signature verification passwords (preset storage passwords) in advance, when the peripheral wants to read and write the storage unit 300, the peripheral writes the read and write passwords first, if the passwords are consistent, the storage unit 300 can be read and written, and if the read and write passwords are inconsistent with the preset passwords, the peripheral refuses to access. That is, if the read-write password is the same as the preset storage password corresponding to the storage unit 300, the verification is passed, and the read-write instruction is sent to the storage unit 300; the arbitration unit 100 further determines a clock frequency selection signal according to the interface type of the communication interface 200, and outputs the clock frequency selection signal to the clock unit 400, where the clock frequency selection signal is used to control the output frequency of the clock unit 400; the clock unit 400 outputs a clock signal to the memory unit 300 according to the clock frequency selection signal; the memory unit 300 executes the read-write command according to the clock signal, and outputs the data read-write result of the read-write command to the communication interface 200.
Further, in one embodiment of the present application, a hierarchical access mechanism may be set for the storage unit 300 to improve access security; specifically, the present application provides an implementation manner of executing the read-write instruction by the storage unit 300 according to the clock signal, where the implementation manner is applied to an implementation manner in which the read-write instruction corresponds to the read instruction, and the implementation manner includes the following steps:
(1) If the read-write instruction is a write instruction, executing the write instruction and detecting a write value of a first preset storage position;
(2) If the writing value is the same as the preset writing value of the first preset storage position, continuing to execute the writing instruction and detecting the writing value of a second preset storage position;
(3) If the writing value of the second preset storage position is the same as the preset writing value of the second preset storage position, continuing to execute the writing instruction and detecting the writing value of the third preset storage position until the writing of the writing data corresponding to the writing instruction is completed.
Namely, access rights can be obtained through multi-layer unlocking to realize protection of the storage unit 300 or a certain storage area, for example, when a write instruction is executed for a certain storage area, data is written from a first layer, when the first layer is written to a first preset storage position, a write value of the first preset storage position is read, if the write value is different from a preset write value of the first preset storage position, the execution of the read-write instruction is stopped, and read-write interception information or read-write failure information is fed back to an initiator; if the writing value is the same as the preset writing value of the first preset storage position, the first layer password verification is passed, the second layer data is written in successively, when the first layer is written in the second preset storage position, the writing value of the second preset storage position is read, if the writing value of the second preset storage position is the same as the preset writing value of the second preset storage position, the second layer password verification is passed, the writing instruction is executed continuously, the writing value of the third preset storage position is detected, until the writing data corresponding to the writing instruction is written in, namely, the first-stage locking register is added to the action of reading and writing a certain area, the second layer authority can be obtained only when the states of the first-stage locking registers are preset values, the third layer authority is added to the added locking register, namely, the second-stage locking register is obtained, and only when the second-stage locking register is set to be the preset value, the authority is modified/the first-stage locking register is read and the third-stage locking register is written in. And so on, more levels of authority control can be set, and only through the authorities of all levels, the authority for accessing the storage unit 300 can be finally obtained.
It will be appreciated that the communication interface 200 according to any of the above embodiments may be provided with an E2EECC error detection and correction mechanism to enhance data reliability. Common ECC support modes include DED(Double Error Detect)、SECDED(Single Error Correct Double Error Detect)、DECTED(Double Error Correct Triple Error Detect), which can be selected for support according to the system requirements. The ECC implementation is a general implementation in the industry, and not described herein, emphasis is placed on an integrated scheme that can support ECC and parity for data input and data output of the memory unit 300, and that completes data verification to enhance on-chip hardware communication reliability.
The embodiment of the application provides a system on a chip, which comprises an arbitration unit, a storage unit, a communication interface and a clock unit, wherein the arbitration unit is respectively connected with the storage unit, the communication interface and the clock unit, and the storage unit is connected with the clock unit; the arbitration unit receives a read-write instruction output by the communication interface and sends the read-write instruction to the storage unit; the arbitration unit determines a clock frequency selection signal according to the interface type of the communication interface and outputs the clock frequency selection signal to the clock unit, wherein the clock frequency selection signal is used for controlling the output frequency of the clock unit; the clock unit outputs a clock signal to the storage unit according to the clock frequency selection signal; and the storage unit executes the read-write instruction according to the clock signal and outputs a data read-write result of the read-write instruction to the communication interface. The method comprises the steps of setting an arbitration unit to receive a read-write command output by a communication interface, determining different clock frequency selection signals for controlling the output frequency of a clock unit according to the interface type of the communication interface, and further setting the clock unit to output the clock signal to a storage unit according to the clock frequency corresponding to the clock frequency selection signals.
Further, on the basis of the above embodiment, the present application also discloses a data read-write control method, where the data read-write control method is applied to the system on chip described in any one of the above embodiments, and the system on chip includes a communication interface, see fig. 3, and the method includes steps S301 to S302:
And S301, when a read-write instruction sent by the communication interface is received, confirming a clock frequency selection signal corresponding to the read-write instruction according to the interface type of the communication interface.
Specifically, when receiving a read-write instruction based on a communication interface, the system on a chip determines a target clock frequency selection signal corresponding to the read-write instruction according to the interface type of the communication interface corresponding to the read-write instruction, and the specific implementation mode is described in any one of the embodiments.
S302, executing the read-write instruction according to the clock frequency selection signal, and feeding back a read-write result to the communication interface.
Further, after the system on chip determines the clock frequency selection signal according to the interface type, the system on chip adjusts the output of the clock unit in the system on chip according to the clock frequency selection signal, controls the clock unit to output a pulse signal corresponding to the clock frequency selection signal to a storage unit of the system on chip, and the storage unit controls the execution of the read-write instruction according to the output frequency of the pulse signal.
Further, in one embodiment of the present application, according to the interface type of the communication interface, the clock frequency selection signal corresponding to the read-write command is confirmed, which includes the steps of:
(1) If at least two read-write instructions are received, determining the read-write sequence of each read-write instruction according to the interface type of each communication interface;
(2) And determining a clock frequency selection signal of each read-write instruction.
The specific implementation manner of the data read-write control method can refer to the detailed description of the foregoing embodiments, and will not be repeated here.
Furthermore, on the basis of the above embodiment, the present application further provides an electronic device, in which a system on chip is disposed, and in some embodiments, a part of a communication interface of the system on chip is disposed outside the electronic device, so that an external initiator of the electronic device can be connected with the system on chip based on the communication interface of the peripheral, and the external initiator can conveniently use a storage unit in the system on chip of the electronic device.
In the application, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred. For the apparatus disclosed in the examples, since it corresponds to the method disclosed in the examples, the description is relatively simple, and the relevant points are referred to in the description of the method section.
The system on chip, the data read-write control method and the electronic device provided by the embodiment of the application are described in detail, and specific examples are applied to the explanation of the principle and the implementation mode of the application, and the explanation of the above embodiment is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the ideas of the present application, the present description should not be construed as limiting the present application in summary.
Claims (13)
1. The system on a chip is characterized by comprising an arbitration unit, a storage unit, a communication interface and a clock unit, wherein the arbitration unit is respectively connected with the storage unit, the communication interface and the clock unit, and the storage unit is connected with the clock unit;
the arbitration unit receives a read-write instruction output by the communication interface and sends the read-write instruction to the storage unit;
The arbitration unit determines a clock frequency selection signal according to the interface type of the communication interface and outputs the clock frequency selection signal to the clock unit, wherein the clock frequency selection signal is used for controlling the output frequency of the clock unit;
The clock unit outputs a clock signal to the storage unit according to the clock frequency selection signal;
And the storage unit executes the read-write instruction according to the clock signal and outputs a data read-write result of the read-write instruction to the communication interface.
2. The system on a chip of claim 1, wherein the communication interfaces comprise at least two, the storage unit comprises one or more, each communication interface is respectively connected with the arbitration unit;
the arbitration unit receives the read-write instruction output by the communication interface and sends the read-write instruction to the storage unit, and the arbitration unit comprises:
If the arbitration unit receives the read-write instructions output by at least two communication interfaces, determining the read-write sequence of each read-write instruction according to the interface type of each communication interface;
The arbitration unit sends each read-write instruction to the storage unit according to the read-write sequence.
3. The system on a chip of claim 2, wherein if the arbitration unit receives the read-write instructions output by at least two of the communication interfaces, determining the read-write order of the read-write instructions according to the interface type of each of the communication interfaces comprises:
If the arbitration unit receives the read-write instructions output by at least two communication interfaces, acquiring the priority corresponding to the interface type of each communication interface according to a preset rule;
And determining the reading and writing sequence of each reading and writing instruction according to the priority corresponding to the interface type of each communication interface.
4. The system on a chip of claim 2, wherein the memory units comprise at least two memory units, each memory unit being respectively connected to the arbitration unit, each memory unit being respectively connected to the clock unit;
The arbitration unit sends each read-write instruction to the storage unit according to the read-write sequence, and the arbitration unit comprises:
Acquiring a read-write execution state of each storage unit, wherein the read-write execution state comprises a read-write state and an idle state;
and the arbitration unit respectively sends the read-write instructions to the target storage unit in the idle state according to the read-write sequence.
5. The system on a chip of claim 1, wherein the arbitration unit determines the clock frequency selection signal of the read/write instruction according to an interface type of the communication interface, comprising:
If the interface type of the communication interface is a preset interface type, extracting a target read-write type carried by a read-write instruction corresponding to the communication interface;
Inquiring preset association information corresponding to the preset interface type, and acquiring clock frequency selection signals corresponding to the target read-write type, wherein the preset association information comprises at least two preset relation groups, and each preset relation group comprises a read-write type and a clock frequency selection signal.
6. The system on a chip of claim 1, wherein the arbitration unit determines the clock frequency selection signal of the read/write instruction according to the interface type of the communication interface, comprising
If the interface type of the communication interface is not the preset interface type, inquiring a preset mapping table corresponding to the type and the selection signal, and acquiring a clock frequency selection signal corresponding to the interface type of the communication interface.
7. The system on a chip of claim 1, wherein the memory unit is internally divided into at least two memory areas;
after receiving the read-write instruction output by the communication interface, the arbitration unit further comprises:
If the target storage area to be accessed corresponding to the read-write instruction is a preset storage area, acquiring a preset access list corresponding to the target storage area;
Discarding the read-write instruction if the initiator corresponding to the read-write instruction does not belong to the access list;
And if the initiator corresponding to the read-write instruction belongs to the access list, executing the step of sending the read-write instruction to the storage unit.
8. The system on a chip of claim 1, wherein after the arbitration unit receives the read-write instruction output by the communication interface, further comprising:
searching a preset relation table corresponding to the initiator and the security level, and acquiring a target security level of the initiator corresponding to the read-write instruction;
if the target security level is lower than a preset security level, acquiring a read-write password of the initiator corresponding to the read-write instruction;
and if the read-write password is the same as the preset storage password corresponding to the storage unit, executing the step of sending the read-write instruction to the storage unit.
9. The system on a chip of any of claims 1-8, wherein the read-write instructions comprise at least one of a read instruction, a write instruction;
The memory unit executes the read-write instruction according to the clock signal, and the read-write instruction comprises:
If the read-write instruction is a write instruction, executing the write instruction and detecting a write value of a first preset storage position;
if the writing value is the same as the preset writing value of the first preset storage position, continuing to execute the writing instruction and detecting the writing value of a second preset storage position;
if the writing value of the second preset storage position is the same as the preset writing value of the second preset storage position, continuing to execute the writing instruction and detecting the writing value of the third preset storage position until the writing of the writing data corresponding to the writing instruction is completed.
10. The system on a chip of claim 9, wherein if the read-write instruction is a write instruction, after executing the write instruction and detecting the write value of the first preset storage location, further comprising:
If the writing value is different from the preset writing value of the first preset storage position, stopping executing the writing instruction and feeding back a writing failure signal.
11. A data read-write control method, characterized in that it is applied to a system on a chip according to any one of claims 1 to 10, the system on a chip including a communication interface, the method comprising:
When a read-write instruction sent by the communication interface is received, confirming a clock frequency selection signal corresponding to the read-write instruction according to the interface type of the communication interface;
executing the read-write instruction according to the clock frequency selection signal, and feeding back a read-write result to the communication interface.
12. The method for controlling data read-write according to claim 11, wherein said validating the clock frequency selection signal corresponding to the read-write command according to the interface type of the communication interface includes:
if at least two read-write instructions are received, determining the read-write sequence of each read-write instruction according to the interface type of each communication interface;
And determining a clock frequency selection signal of each read-write instruction.
13. An electronic device comprising the system on chip of any of claims 1-10.
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| CN119537303A (en) * | 2025-01-21 | 2025-02-28 | 山东云海国创云计算装备产业创新中心有限公司 | Video function system of storage application chip, storage application chip and server |
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| CN119537303A (en) * | 2025-01-21 | 2025-02-28 | 山东云海国创云计算装备产业创新中心有限公司 | Video function system of storage application chip, storage application chip and server |
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