CN216252695U - Sigma-Delta modulator circuit shared by operational amplifiers - Google Patents

Abstract

The utility model discloses a Sigma-Delta modulator circuit shared by operational amplifiers, wherein an adopted integrating circuit can realize the functions of 2 integrators by using only one integrator under the control of a two-phase non-overlapping clock frequency division module. The clock frequency division module divides an input clock into different small clocks, and the small clocks are used for controlling switches in the fully differential operational amplifier to realize sampling or integration operation at different stages. The integrating circuit has the low power consumption characteristic of a multi-stage single integrator, and plays an important role in reducing the occupied area of a chip and the overall power consumption and cost of a modulator.

Description

A Sigma-Delta Modulator Circuit Shared by Operational Amplifiers

technical field

The utility model relates to the technical field of integrated circuits, in particular to an operational amplifier sharing Sigma-Delta modulator circuit with low power consumption.

Background technique

The Sigma-Delta modulator receives the analog signal at the input end and passes through the integrator and quantizer, then reprocesses the data through the digital-to-analog converter of the feedback loop, and finally outputs a digital signal, which corresponds to the input analog signal and is discrete. Type sigma-delta modulators typically employ multiple switched capacitor integrators.

Utility model content

The utility model provides a sigma-delta modulator circuit shared by operational amplifiers, wherein the adopted integrating circuit can only use one integrator to realize the function of two integrators under the control of a dual-phase non-overlapping clock frequency dividing module. The clock frequency division module divides the input clock into different small clocks, and uses these small clocks to control the switches in the fully differential operational amplifier to realize sampling or integration operations at different stages. The integrator circuit has the characteristics of low power consumption of a multi-stage single integrator, and plays an important role in reducing the area occupied by the chip and reducing the overall power consumption and cost of the modulator.

The Sigma-Delta modulator circuit structure provided by the utility model:

Controllable switches 111-134, sampling capacitors 160, 170, 180 and 190, integrating capacitors 140, 150, 200 and 210, and a fully differential operational amplifier OP.

The first terminals of the controllable switches 117 and 118 are respectively connected to the current branches E10a and E10b, the first terminals of the controllable switches 119 and 120 are connected to the common mode voltage V _CM , and the second terminals of the controllable switches 117 and 119 are connected to the common mode voltage V CM . It is interconnected with the first end of the sampling capacitor 160, the second end of the controllable switches 118 and 120 is interconnected with the first end of the sampling capacitor 170, the second end of the sampling capacitor 160 is connected with the second end of the controllable switch 113, and the first end of the controllable switch 111. One terminal is interconnected, the second terminal of the sampling capacitor 170 is interconnected with the second terminal of the controllable switch 114 and the first terminal of the controllable switch 112, and the first terminals of the controllable switches 113 and 114 are connected to the common mode voltage V _CM , which can be The second terminal of the controllable switch 111, the second terminal of the controllable switch 125, and the first terminals of the controllable switches 115 and 127 are connected to the positive input terminal of the fully differential operational amplifier OP.

The second terminal of the controllable switch 112, the second terminal of the controllable switch 126 and the first terminals of the controllable switches 116, 128 are connected to the negative input terminal of the fully differential operational amplifier OP.

The first terminals of the controllable switches 123 and 121 are interconnected with the second terminal of the integrating capacitor 140, the first terminal of the integrating capacitor 140 is connected to the second terminal of the controllable switch 115, and the first terminals of the controllable switches 131 and 133 are connected to Common mode voltage V _CM , the second terminals of the controllable switches 123 and 131 are connected to the first terminal of the sampling capacitor 180 , the first terminal of the controllable switch 125 and the second terminal of the controllable switch 133 are connected to the second terminal of the capacitor 180 , The first terminal of the integrating capacitor 200 is connected to the second terminal of the controllable switch 127, the second terminals of the controllable switches 121 and 129 are connected to the negative output terminal of the fully differential operational amplifier OP, the second terminal of the integrating capacitor 200 and the controllable switch 129 The first terminal is connected to the output branch A30a.

The first terminals of the controllable switches 124 and 122 are interconnected with the second terminal of the integrating capacitor 150, the first terminal of the integrating capacitor 150 is connected to the second terminal of the controllable switch 116, and the first terminals of the controllable switches 132 and 134 are connected to Common mode voltage V _CM , the second terminals of the controllable switches 124 and 132 are connected to the first terminal of the sampling capacitor 190 , the first terminal of the controllable switch 126 and the second terminal of the controllable switch 134 are connected to the second terminal of the capacitor 190 , The first terminal of the integrating capacitor 210 is connected to the second terminal of the controllable switch 128 , the second terminals of the controllable switches 122 and 130 are connected to the positive output terminal of the fully differential operational amplifier OP, the second terminal of the integrating capacitor 210 and the controllable switch 130 The first terminal is connected to the output branch A30b.

Description of drawings

Fig. 1 shows the circuit schematic diagram of the present utility model;

Fig. 2 shows the sampling equivalent part of the present utility model in the traditional framework Sigma-Delta modulator;

Fig. 3 shows the integral equivalent part of the present utility model in the traditional framework Sigma-Delta modulator;

FIG. 4 shows a timing diagram of a clock frequency division module adopted in an embodiment of the present invention.

Detailed ways

In order to describe in detail the structural features, technical principles, the problems solved and the effects obtained by the present invention, a detailed description will be given below with reference to the embodiment of the modulator constructed according to FIG. 1 and in conjunction with the accompanying drawings.

When analyzing the structure of Fig. 1, it can be divided into two parts: the inner loop and the outer loop. The inner loop part starts from the input of the input signals Vi+ and Vi-, passes through the controllable switches 117, 118, and the sampling capacitors 160, 170 , and then passes through the controllable switches 117, 118. The switches 111 and 112 reach the fully differential operational amplifier OP, and 140 and 150 of the fully differential operational amplifier OP are integral capacitors of the inner loop, and the inner loop completes the sampling process from the input signal Vi1 to the sampling capacitor C _s1 in the traditional structure of FIG. 2 . The outer loop starts from the fully differential op amp OP outputs A130a and A130b in Figure 1, passes through the sampling capacitors 180, 190, the controllable switches 123, 124 and the controllable switches 125, 126, and then returns to the fully differential op amp OP. 200 and 210 of the differential operational amplifier OP are integral capacitors of the outer loop, and the outer loop completes the function of outputting from the first-stage integrator to the second-stage integrator in the traditional structure of FIG. 3 .

Specifically, when the differential input signal is input from the input terminals Vi+ and Vi-, at the moment n+1, when the phase of the clock circuit φ1 triggers the controllable switches 117 and 118 to close, the first sampling capacitor 160 and the second sampling capacitor 170 pair The input signal is sampled and stored in sampling capacitors 160 and 170 as charges, respectively. At the same time, the fully differential operational amplifier OP integrates the charges stored in the third sampling capacitor 180 and the fourth sampling capacitor 190 at time n through the fully differential operational amplifier OP, and then outputs them to A130a and A130b. The capacitors C _a1 , C _a2 and C _b on the summation circuit perform signal summation and finally send it to a one-bit quantizer to obtain an output digital code.

At time n+2, when the clock circuit φ2 phase triggers the controllable switches 111, 112, 121, 122, 123, and 124 to close, the first sampling capacitor 160 and the second sampling capacitor 170 transfer charges into the fully differential operational amplifier OP The integration operation is performed, and the integrated result will be directly sent to the third sampling capacitor ₁₈₀ and the fourth _sampling capacitor ₁₉₀ of the second stage . to the common mode potential (VCM).

By repeating the above process in this way, a modulator composed of two fully differential integrators can be implemented by the present invention to realize that one integrator completes the functions of two integrators under the control of the dual-phase non-overlapping clocks designed in FIG. 4 . This will greatly reduce the power consumption problem introduced by the number of fully differential integrators, and to a certain extent it also reduces the chip area.

Beneficial effects of the present invention:

Compared with the prior art, the utility model changes the connection mode of the sampling capacitor and the integrating capacitor of the fully differential integrator by redesigning the Sigma-Delta modulator circuit, and the front and rear of the branch where the sampling capacitor and the integrating capacitor are located are controlled by a controllable switch. , and finally achieve the purpose of sharing the fully differential integrator.

Claims (1)

1. A Sigma-Delta modulator circuit shared by operational amplifiers, the circuit comprising: controllable switches 111-134, sampling capacitors 160, 170, 180 and 190, integrating capacitors 140, 150, 200 and 210, and a fully differential operational amplifier OP; the first terminals of the controllable switches 117, 118 are connected to the current branches E10a and E10b, respectively, and the first terminals of the controllable switches 119, 120 are connected to the common-mode voltage V_CMSecond end points of the controllable switches 117 and 119 are interconnected with a first end point of the sampling capacitor 160, second end points of the controllable switches 118 and 120 are interconnected with a first end point of the sampling capacitor 170, a second end point of the sampling capacitor 160 is interconnected with a second end point of the controllable switch 113 and a first end point of the controllable switch 111, a second end point of the sampling capacitor 170 is interconnected with a second end point of the controllable switch 114 and a first end point of the controllable switch 112, and first end points of the controllable switches 113 and 114 are connected to the common-mode voltage V_CMThe second terminal of the controllable switch 111, the second terminal of the controllable switch 125 and the first terminals of the controllable switches 115 and 127 are connected to the positive input terminal of the fully differential operational amplifier OP; the second terminal of the controllable switch 112, the second terminal of the controllable switch 126 and the first terminals of the controllable switches 116, 128 are connected to the negative input of the fully differential operational amplifier OP; the first terminals of the controllable switches 123, 121 are interconnected with the second terminal of the integrating capacitor 140, the integrating capacitor 140 is connected to the second terminalOne terminal is connected to the second terminal of the controllable switch 115, and the first terminals of the controllable switches 131 and 133 are connected to the common mode voltage V_CMSecond end points of the controllable switches 123 and 131 are interconnected with a first end point of the sampling capacitor 180, a first end point of the controllable switch 125 and a second end point of the controllable switch 133 are interconnected with a second end point of the capacitor 180, a first end point of the integrating capacitor 200 is connected to a second end point of the controllable switch 127, second end points of the controllable switches 121 and 129 are connected to a negative output end of the fully differential operational amplifier OP, and a second end point of the integrating capacitor 200 and a first end point of the controllable switch 129 are connected to the output branch a30 a; first terminals of the controllable switches 124, 122 are interconnected with a second terminal of an integrating capacitor 150, the first terminal of the integrating capacitor 150 is connected to the second terminal of the controllable switch 116, and the first terminals of the controllable switches 132, 134 are connected to the common-mode voltage V_CMThe second terminals of the controllable switches 124, 132 are interconnected with the first terminal of the sampling capacitor 190, the first terminal of the controllable switch 126 and the second terminal of the controllable switch 134 are interconnected with the second terminal of the capacitor 190, the first terminal of the integrating capacitor 210 is connected to the second terminal of the controllable switch 128, the second terminals of the controllable switches 122, 130 are connected to the positive output terminal of the fully-differential operational amplifier OP, and the second terminal of the integrating capacitor 210 and the first terminal of the controllable switch 130 are connected to the output branch a30 b.

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