CN101414487B - Device and method for holding sampling - Google Patents

Abstract

The invention discloses a sample-and-hold device, which includes a first-stage sample-and-hold circuit and a second-stage sample-and-hold circuit. The input positive and negative terminals of the first-stage sample-and-hold circuit are connected to external signals, and the output The positive and negative terminals are coupled to the input positive and negative terminals of the second-stage sample-and-hold circuit, the first-stage sample-and-hold circuit has a first-stage operational amplifier that realizes amplification lower than one, and the second-stage sample-and-hold circuit has a The second-stage operational amplifier with multiple amplification, after the external signal is sampled, held and amplified by the first and second-stage sample-and-hold circuits, it is output from the positive and negative output terminals of the second-stage sample-and-hold circuit. The invention also discloses a sampling and holding method. As a basic signal processing module, the present invention is used for front-end processing of external input signals, and under the premise of realizing high reliability, the speed and precision of signal conversion are guaranteed with a simple structure.

Description

A sample-and-hold device and sample-and-hold method

【Technical field】

The invention relates to analog and digital signal processing, in particular to a sample-and-hold device and a sample-and-hold method.

【Background technique】

A sample-and-hold circuit (sample-and-hold) is also called a sample-and-hold amplifier. When the analog/digital conversion is performed on the analog signal, a certain conversion time is required. During this conversion time, the analog signal should remain basically unchanged, so as to ensure the conversion accuracy. The sample and hold circuit is the circuit that realizes this function.

Figure 1a shows a traditional sampling and holding circuit, in which the capacitor Cs is both a sampling capacitor and a holding capacitor. When in the sampling phase (sampling time), the switch controls the input and output of the operational amplifier to short-circuit, and the two inputs are also short-circuited at the same time, the switch connected to the external signal is turned on, and the capacitor samples the external signal level at this time. Then the switch that short-circuits the input and output is disconnected first, and then the switch that connects the two inputs is disconnected, and the level stored on the capacitor is no longer affected by the external signal. Connect the capacitor directly to the output during the hold phase (hold time) and the output settles. This method has a short settling time, but only doubles the magnification.

Figure 1b shows another traditional sample-and-hold circuit, in which two capacitors Cs in one group are sampling capacitors, and two capacitors Cf in the other group are holding capacitors. In the sampling phase, the sampling phase clock control switch short-circuits the input and output of the operational amplifier, and the two inputs are also short-circuited at the same time to generate a common-mode ground level. The switch connected to the external signal is turned on, and the two sets of capacitors are sampled at the same time. external signal level. Then the switch that short-circuits the input and output is disconnected first, and then the switch that connects the two inputs is disconnected. The level stored on the capacitor is no longer affected by the external signal, and the sampling terminals of the sampling capacitor and the holding capacitor are no longer connected together. During the hold phase, the sampling capacitor charge is set to zero, while the hold capacitor is connected to the output, causing charge transfer and establishing the output level. This structure can achieve greater than one-fold amplification, but the settling time is relatively long due to the effect of charge transfer.

Due to the improvement of application requirements, the sample-and-hold circuit module, which has a great impact on the overall performance, faces strict design requirements. High speed, high precision, high linearity, large dynamic range, low-voltage power supply and low power consumption have all become design requirements. important indicators. And these performances largely depend on the operational amplifier. The final result is that the design parameters of the operational amplifier are extremely demanding. The high parameters of the gain-bandwidth product, slew rate, output voltage range and power consumption make the design difficult. . Moreover, once a deviation occurs during the tape-out process, it will have a great impact on performance.

The strict overall performance index requirements for traditional sample-and-hold circuits determine the high standard of the operational amplifier itself. In this case, the operational amplifier needs to meet the requirements of high gain, high speed, large output range and other factors at the same time. In general, in order to achieve these design goals, the design of operational amplifiers is very expensive and difficult. Therefore, new solutions need to be sought.

【Content of invention】

The main purpose of the present invention is to solve the problems in the prior art, to provide a sample-and-hold device and a sample-and-hold method, which can utilize the existing simple operational amplifier module to realize the high-gain, high-speed operation that is harsh on the operational amplifier in the sample-and-hold circuit , large output range, high precision and reliability requirements.

To achieve the above object, the present invention provides a sample-and-hold device, which is characterized in that it includes a first-stage sample-and-hold circuit and a second-stage sample-and-hold circuit, and the input positive and negative terminals of the first-stage sample-and-hold circuit are connected to an external signal, the positive and negative output terminals of the first-stage sampling and holding circuit are coupled to the positive and negative input terminals of the second-stage sampling and holding circuit, and the first-stage sampling and holding circuit has a first A first-stage operational amplifier, the second-stage sample-and-hold circuit has a second-stage operational amplifier that can achieve higher than one-fold amplification, and the external signal is sampled, held, and amplified by the first and second-stage sample-and-hold circuits. , output from the positive and negative output terminals of the second-stage sample-and-hold circuit.

The output positive and negative terminals of the first-stage sample-and-hold circuit are directly connected to the input positive and negative terminals of the second-stage sample-and-hold circuit respectively, and the input positive and negative terminals of the second-stage sample-and-hold circuit are connected in series Connected to the switching device.

The first-stage sample-and-hold circuit further includes a first positive sampling capacitor, a first negative sampling capacitor, a first positive holding capacitor, and a first negative holding capacitor;

One end of the first positive sampling capacitor is coupled to the first input end of the first-stage sample-and-hold circuit and the first output end of the first-stage operational amplifier in a controllable on-off manner, and the other end is coupled to the first-stage operational amplifier. The first input terminal of the first-stage operational amplifier is coupled and coupled with the first output terminal of the first-stage operational amplifier through the first positive holding capacitor;

One end of the first negative sampling capacitor is coupled to the second input end of the first-stage sample-and-hold circuit and the second output end of the first-stage operational amplifier in a controllable on-off manner, and the other end is coupled to the second output end of the first-stage operational amplifier. The second input terminal of the first-stage operational amplifier is coupled and coupled with the second output terminal of the first-stage operational amplifier through the first negative holding capacitor;

The two ends of the first positive and negative storage capacitors can be controlled to be short-circuited.

The first and second input ends of the first-stage operational amplifier are bridged through a switch device.

The second-stage sample-and-hold circuit further includes a second positive sampling capacitor, a second negative sampling capacitor, a second positive holding capacitor, and a second negative holding capacitor;

One end of the second positive sampling capacitor is coupled to the first output end of the first-stage operational amplifier, and the other end is coupled to the first input end of the second-stage operational amplifier and one end of the second positive holding capacitor , and is coupled with the first output terminal of the second-stage operational amplifier in a controllable on-off manner, and the other end of the second positive holding capacitor is respectively connected to the first-stage operational amplifier in a controllable on-off manner. The first output end is coupled to the first output end of the second-stage operational amplifier;

One end of the second negative sampling capacitor is coupled to the second output end of the first-stage operational amplifier, and the other end is coupled to the second input end of the second-stage operational amplifier and one end of the second negative holding capacitor , and is coupled with the second output terminal of the second-stage operational amplifier in a controllable on-off manner, and the other end of the second negative holding capacitor is respectively connected to the first-stage operational amplifier in a controllable on-off manner The second output terminal is coupled to the second output terminal of the second-stage operational amplifier.

The first and second input ends of the second-stage operational amplifier are bridged through a switch device.

The magnification below 1 is 1/2 magnification, and the magnification above 1 is 2 times magnification.

The first-stage operational amplifier is a telescopic single-stage fully differential operational amplifier, and the second-stage operational amplifier is a two-stage fully differential operational amplifier.

The present invention also provides a sample-and-hold method, which is characterized in that: it includes a first-stage sample-and-hold stage and a second-stage sample-and-hold stage, and the holding time in the first-stage sample-and-hold stage corresponds to the sampling time in the second-stage sample-and-hold stage. time, the external signal is amplified by a multiple of less than one in the first-stage sample-and-hold stage, and the signal obtained by the previous stage is amplified by a multiple of one in the second-stage sample-and-hold stage, and the two-stage signal The superposition of the magnification meets the amplitude requirement for the sampling and holding of the external signal.

The output setup time allocated for the first sample and hold stage is shorter than the output setup time allocated for the second stage sample and hold stage.

The holding time of the first-stage sample-and-hold stage is equal to or substantially equal to the sampling time of the second-stage sample-and-hold stage, and the sampling time of the first-stage sample-and-hold stage is equal to or substantially equal to the holding time of the second-stage sample-and-hold stage.

The sampling time in the first-stage sample-and-hold stage ends in the following manner: first disconnect the DC path on the output side of the sampling capacitor, and then disconnect the first and second input terminals of the first-stage operational amplifier, Then the DC path of the sampling capacitor on the input side is disconnected; the sampling time in the second stage sampling and holding stage ends in the following manner: first the DC path of the sampling capacitor on the output side is disconnected, and then the The connection of the first and second input terminals of the second-stage operational amplifier is disconnected, and then the DC path connecting the sampling capacitor to the holding capacitor is disconnected.

The beneficial effect of the present invention compared with prior art is:

The present invention adopts a matching two-stage sample-and-hold circuit. Since the first-stage operational amplifier in the first-stage sample-and-hold circuit adopts a single-stage sleeve structure, the magnification is low, and emphasis is placed on realizing high speed, while the second-stage sample-and-hold circuit The second-stage operational amplifier adopts a two-stage structure to amplify with a high multiple, focusing on achieving high gain and large output range. In this way, the requirements for the overall performance of the sample-and-hold circuit can be realized through the cooperative work of the two parts, thereby avoiding the need to design a highly difficult operational amplifier and improving the overall reliability of the circuit.

Preferably, the first-stage operational amplifier adopts a sleeve-type single-stage fully differential operational amplifier, and the second-stage operational amplifier adopts a two-stage fully-differential operational amplifier. The sleeve-type single-stage operational amplifier has fast speed, low noise, simple structure and reliability. High performance, suitable for low voltage design, large gain of dual-stage operational amplifier, wide output range, low noise, simple structure, high reliability, suitable for low voltage design, through this structural design of the present invention, the simple structure can be realized operational amplifiers to meet the high demands of track-and-hold designs. Moreover, the two-stage operational amplifiers are low-noise structures, thus ensuring high linearity as a whole.

Since the two parts are directly connected in a pipelined manner, and in particular, such that the hold time of the first stage is equal to the sample time of the second stage, and the sample time of the first stage is equal to the hold time of the second part, the first stage due to the low amplification Multiple and high-speed operational amplifiers can set up the output in a short time, which means that the hold time can be extremely short, and correspondingly, due to the direct connection between the two parts of the circuit, its RC (resistance-capacitance) value is extremely small , which means that the sampling time of the second stage can be extremely short. Therefore, more time can be allocated to the sampling time of the first stage and the holding time of the second stage, thereby ensuring the high precision and reliability of the sample and hold circuit as a whole.

【Description of drawings】

Fig. 1a and Fig. 1b are prior art circuit principle diagrams;

Fig. 2 is the circuit schematic diagram of the embodiment of the present invention;

Fig. 3 is a circuit sequence diagram of an embodiment of the present invention;

Fig. 4a and Fig. 4b are the circuit principle diagrams of the first stage operational amplifier of the present invention;

5a and 5b are schematic circuit diagrams of the second-stage operational amplifier of the present invention.

The features and advantages of the present invention will be described in detail with reference to the accompanying drawings.

【Detailed ways】

Embodiment one:

Please refer to Figure 2, the entire sample-and-hold device is divided into two parts: the first-stage sample-and-hold circuit and the second-stage sample-and-hold circuit. The first-stage sampling and holding circuit and the second-stage sampling and holding circuit are controlled by the timing control circuit, so that the sampling phase of the first-stage sampling and holding circuit corresponds to the holding phase of the second-stage sampling and holding circuit, and the first-stage sampling and holding circuit The holding phase corresponds to the sampling phase of the second-stage sampling and holding circuit, so that the two work together. When the first-stage sample-and-hold circuit is in the sampling phase, its positive and negative output terminals are short-circuited (does not affect sampling), and the second-stage sample-and-hold circuit enters the hold phase at the same time. When the first-stage sample-and-hold circuit is in the hold phase, the second-stage sample-and-hold circuit samples the output signal of the first stage. Pipeline work is formed between the two stages.

The first-stage sample-and-hold circuit consists of the first-stage operational amplifier A1, four peripheral capacitors and seven switches. The peripheral capacitors are the first positive sampling capacitor C1sp, the first negative sampling capacitor C1sn, the first positive holding capacitor C1hp, and the first negative holding capacitor C1hn. The seven peripheral switches use CMOS (Complementary Metal-Oxide Semiconductor, Complementary Metal Oxide Semiconductor) The switch device includes two switches 1tt, two switches 1 and one switch 1t. Wherein, one end of the first positive sampling capacitor C1sp and the first negative sampling capacitor C1sn are respectively connected to the first and second input ends of the first-stage operational amplifier A1, and the other end of the first positive sampling capacitor C1sp is connected to the first The input positive terminal of the first-stage sampling and holding circuit is coupled, and at the same time, the first output terminal of the first-stage operational amplifier A1 is coupled through the switch 2, and the other end of the first negative sampling capacitor C1sn is connected to the input negative terminal of the first-stage sampling and holding circuit through the switch 1. terminal coupled, and coupled with the second output terminal of the first-stage operational amplifier A1 through the switch 2 at the same time. The first positive holding capacitor C1hp and the first negative holding capacitor C1hn are connected across the first input terminal, the output terminal and the second input terminal and the output terminal of the first-stage operational amplifier A1 respectively. Both ends of the first positive holding capacitor C1hp are connected in parallel to the switch 1tt, and both ends of the first negative holding capacitor C1hn are connected in parallel to the switch 1tt. The first and second input ends of the first-stage operational amplifier A1 are bridge-coupled through a switch 1t, so that a common-mode ground is generated when the phase is sampled.

The switch control signal controls the on-off of the switch 1 connected to the positive input terminal of the first-stage sampling and holding circuit to control the input of the external signal Vip, and the control signal controls the switch 1 connected to the negative input terminal of the first-stage sampling and holding circuit To control the input of the external signal Vin, another group of switches 2 connects the first positive sampling capacitor C1sp and the first negative sampling capacitor C1sn to the first stage respectively under the action of the switch control signal The two ends of the first input and output and the second input and output of the operational amplifier A1 are respectively controlled and connected across the two ends of the first positive holding capacitor C1hp and the first negative holding capacitor C1hn to realize the sampling phase sum Keep charging and discharging relative to the capacitance at the input and output terminals of the first-stage operational amplifier A1.

The first-stage operational amplifier A1 of this embodiment is a telescopic single-stage fully differential operational amplifier, and a switched capacitor circuit is used inside to construct a common-mode negative feedback network.

The second-stage sample-and-hold circuit is composed of the second-stage operational amplifier A2, four peripheral capacitors and seven switches. The second-stage operational amplifier A2 adopts a simple two-stage fully differential operational amplifier. The peripheral capacitors are the second positive sampling capacitor C2sp, the second negative sampling capacitor C2sn, the second positive holding capacitor C2hp, and the second negative holding capacitor C2hn. The seven switches include two switches 2tt, two switches 2 and one switch 2t. Wherein, one end of the second positive sampling capacitor C2sp is coupled to the first output end of the first-stage operational amplifier A1, and the other end is coupled to the first input end of the second-stage operational amplifier A2 and one end of the second positive holding capacitor C2hp, and Coupled with the first output end of the second-stage operational amplifier A2 through the switch 2tt, the other end of the second positive holding capacitor C2hp is coupled with the first output end of the first-stage operational amplifier A1 through the switch 2, and connected with the second-stage operational amplifier A1 through the switch 1 The first output end of the operational amplifier A2 is coupled; one end of the second negative sampling capacitor C2sn is coupled with the second output end of the first-stage operational amplifier A1, and the other end is coupled with the second input end of the second-stage operational amplifier A2, the second negative One end of the holding capacitor C2hn is coupled, and coupled with the second output end of the second-stage operational amplifier A2 through the switch 2tt, and the other end of the second negative holding capacitor C2hn is coupled with the second output end of the first-stage operational amplifier A1 through the switch 2, And coupled with the second output end of the second-stage operational amplifier A2 through the switch 1 . The first and second input ends of the second-stage operational amplifier A2 are bridge-coupled through a switch 2t to generate a common-mode ground level.

The second positive sampling capacitor C2sp and the second negative sampling capacitor C2sn are constantly connected to the first and second input terminals of the second-stage operational amplifier A2; under the action of the switch control signal, the second positive holding capacitor C2hp and the second negative holding capacitor C2hn In the sampling phase, a switch 2 is connected in parallel to the two ends of the second positive sampling capacitor C2sp and the second negative sampling capacitor C2sn, and in the holding phase, a switch 1 is connected across the first input of the second-stage operational amplifier A2, Between the output terminals and between the second input and output terminals. The two switches 2tt respectively control the connection of the first input and output terminals and the connection of the second input and output terminals of the second-stage operational amplifier A2 under the action of the switch control signal. Output signals Vop and Von of the sample-and-hold device are output from the first and second output terminals of the second-stage operational amplifier A2.

The second-stage operational amplifier A2 of this embodiment is a dual-stage fully differential operational amplifier, the first stage of which uses a transistor voltage divider resistor to form a common-mode negative feedback, and the second stage of which uses a switched capacitor network.

The first-stage sample-and-hold circuit is connected to the second-stage sample-and-hold circuit in the following manner: the first and second output terminals of the first-stage operational amplifier A1 are respectively coupled to the first and second input terminals of the second-stage operational amplifier A2, The first and second sample-and-hold circuits are directly connected, and actually operate in a pipelined structure. In addition, the first and second output terminals of the first-stage operational amplifier A1 are bridged by a switch 1, and the switch 1 can be connected to the first and second outputs of the first-stage operational amplifier A1 under the action of the switch control signal. The terminal is short-circuited to the two input terminals of the second-stage sample-and-hold circuit. Since the second-stage sample-and-hold circuit is just in the hold state when the first-stage sample-and-hold circuit is sampling, for this embodiment, the establishment of the output signal of the second-stage sample-and-hold circuit requires its two input terminals to be short-circuited, and the switch 1 Closure fulfills exactly this requirement. In addition, the closing of the switch 1 can also make the output differential signal of the first-stage sample-and-hold circuit return to zero.

Compared with the traditional sample and hold circuit, the advantages of the present invention are reflected in the following aspects.

As shown in FIG. 1a, the sample-and-hold circuit only has two capacitors Cs that are both sampling capacitors and holding capacitors. This structure can only achieve double magnification. The first-stage sample-and-hold circuit shown in FIG. 2 adds a set of first positive holding capacitor C1hp and first negative holding capacitor C1hn across the two ends of the operational amplifier on the basis of the circuit shown in FIG. 1a. In the sampling phase phase, the first positive holding capacitor C1hp and the first negative holding capacitor C1hn are respectively short-circuited by the switch 1tt, and there is no charge on the capacitors. In the holding phase, the first positive holding capacitor C1hp, the first negative holding capacitor C1hn, the first positive sampling capacitor C1sp, and the first negative sampling capacitor C1sn share the charge and build the output level, which is realized by the first stage operational amplifier A1 A magnification of a factor less than one. The structure of the second-stage sampling and holding circuit is the same as the sampling and holding circuit shown in Figure 1b. The two-stage sample-and-hold circuit adopts the above two circuit structures, and due to the existence of the switch 1 between the two outputs of the front-stage circuit and the two inputs of the subsequent-stage circuit, when the first-stage sample-and-hold circuit is in the sampling phase, the second-stage sample-and-hold circuit is in the sampling phase. A hold circuit allows for output setup. Therefore, under the action of the switch control signal, the first and second sample-and-hold circuits can realize the pipeline operation of sampling and holding functions, and generate the final output.

The magnification required by the sample-and-hold device of the present invention can be realized by adjusting the sizes of multiple capacitors in the two-stage sample-and-hold circuit. When there are different magnification requirements, since there are multiple capacitors available for adjustment in the circuit, the overall magnification of the sample-and-hold device of the present invention can be greater than one or less than one. Relatively speaking, the traditional structure can only realize the adjustment within a single range or the adjustment within a range. In the application where the magnification is one, the first-stage operational amplifier A1 in the first-stage sample-and-hold circuit of the present invention adopts a 1/2 multiple operational amplifier, and the second-stage operational amplifier A1 adopts a double multiple operational amplifier, which can make the circuit All capacitors are of the same size, and no additional capacitors are required, which brings convenience to circuit construction. And for the second-stage sample-and-hold circuit, the relatively large magnification makes its design requirements easier to realize. Especially the 1/2 magnification of the first part makes the output range of the first part and the input range of the second part both smaller, thus leaving more room for the compromise design of various performance parameters.

Generally speaking, the structure of the first-stage sample-and-hold circuit is simple and fast, but the amplification factor is small. In the second-stage sample-and-hold circuit, a dual-stage operational amplifier is used to make the gain and output range large. When the first stage When the magnification factor is 1/2 and the second stage magnification factor is 2, the amplitude of the final output result is consistent with the external input signal. Although the operational amplifier of the dual-stage structure is slow, because the input signal amplitude of the second-stage sample-and-hold circuit is only half of the external input signal amplitude, and because the first-stage operational amplifier A1 adopts a high-speed telescopic structure operation The structure of the amplifier and the first-stage sample-and-hold circuit makes the output response time short, so the first-stage sample-hold circuit can achieve a very high settling speed. Therefore, the combination of the first and second stages can generally achieve a relatively short settling time for large signals, shortening the overall settling time when using traditional designs.

Fig. 4a and Fig. 4b are circuit diagrams of the first-stage operational amplifier of the present invention. Among them, Fig. 4a is the main module of the operational amplifier, and Fig. 4b is the bias circuit of the operational amplifier. The sleeve structure operational amplifier has high speed, low noise, simple design, suitable for low voltage design, and high reliability. The switched capacitor network records the ideal bias in the sampling phase, and feedbacks and corrects it in the amplifying phase, with no static power consumption and wide adjustment range. The bias circuit composed of the mirror current source can keep constant under the large external voltage fluctuation.

5a and 5b are circuit diagrams of the second-stage operational amplifier of the present invention. Among them, Fig. 5a is the main module of the operational amplifier, and Fig. 5b is the bias circuit of the operational amplifier. The double-stage structure has large gain, wide output range and low noise. In addition, the dual-stage fully differential operational amplifier preferably used in this circuit is suitable for low-voltage design and has high reliability. The first stage adopts the transistor divider resistance in the linear region as the feedback circuit, which has a simple structure, and the second stage adopts a switched capacitor network with excellent performance.

It is precisely because the operational amplifiers of the two parts are of different types and focus on different performance indicators respectively, so the design is very simple, especially in the low voltage structure, it can still maintain high reliability. Moreover, the preferred operational amplifiers of the sample-and-hold circuit of the present invention are of low-noise structure, thereby ensuring high linearity as a whole.

In addition, in the first and second sample-and-hold circuits, each switch around the operational amplifier is preferably a CMOS switch, and its on-resistance value fluctuates less with the change of the sampling signal voltage, so that the overall linearity is better.

As another aspect of the present invention, the present invention also proposes a sample-and-hold method, which includes a first-stage sample-and-hold stage and a second-stage sample-and-hold stage connected in a pipelined manner, and the holding time in the first-stage sample-and-hold stage corresponds to Based on the sampling time in the second sample-and-hold stage, the external signal is amplified at a low multiple in the first-stage sample-and-hold stage, and the signal obtained from the previous stage is amplified at a high multiple in the second-stage sample-and-hold stage. The superimposition of the multi-stage signal magnification meets the amplitude requirements for the sampling and holding of the external signal.

FIG. 3 is a circuit sequence diagram of this embodiment. Correspondingly, the first-stage sample-and-hold stage is executed on the first-stage sample-and-hold circuit of the present invention, and the second-stage sample-and-hold stage is executed on the second-stage sample-and-hold circuit of the present invention. The holding time of the first-stage sampling and holding circuit is equal to the sampling time of the second-stage sampling and holding circuit, and the sampling time of the first-stage sampling and holding circuit is equal to the holding time of the second-stage sampling and holding circuit. The first-stage sample-and-hold circuit can be established in a short time because of its low amplification factor and high-speed operational amplifier, which means that its first-stage hold time can be extremely short. With the same second sampling time, due to the direct connection between the first and second sampling and holding circuits, the extremely small RC (resistor capacitance) value means that the sampling time can be extremely short. Therefore, more time can be allocated to the sampling time of the first stage and the hold time of the second stage, thereby ensuring the overall high precision of the sample and hold.

Since the output of the first-stage sample-and-hold circuit of the present invention establishes quickly, while the output of the second-stage sample-and-hold circuit establishes relatively slowly and is related to the final output, the time of the entire cycle can be further distributed unequally. By adjusting the clock signal, the control assigns a shorter output setup time to the first stage and a longer output setup time to the second stage. Through the reasonable allocation of the two-stage setup time, the overall high speed of sampling and holding is realized. For example, for an application with a sampling frequency of 40MHz, a period is 25ns. Considering the rising and falling edges of the clock and the non-overlapping of the clock, the sampling phase time of the first-stage sampling and holding circuit can be set to 15.5ns, and the holding phase time is 6.5ns. Correspondingly, the sampling phase time of the second-stage sampling and holding circuit is set to 6.5 ns, and the holding phase time is 15.5 ns.

At the same time, in order to eliminate the influence of the charge injection effect, the switch connected to the sampling capacitor is further controlled at a specific timing, so that the charge in the sampling capacitor is not affected by the outside before the external signal is disconnected. See Figure 3 for the timing relationship of controlling the on-off of each switch, and this relationship ensures the elimination of the charge injection effect. In the following, the output of the first-stage sample-and-hold circuit is established, that is, the first stage is described by the control signals phase1, phase1t, and phase1tt of the switch groups 1, 1t, and 1tt during the transition from the sampling phase to the holding phase. Since the two switches 1 controlled by phase1 connected to the external signal will cause non-ideal differential signals due to the charge injection effect when they are turned off, so the two switches 1tt controlled by phase1tt are turned off before this, so that the sampling in the first stage The DC path at one end of the capacitor is broken. The charging and discharging of the capacitor requires a DC path at both ends at the same time, so the capacitor charge starts to be conserved at this time, and the disconnection of the two switches 1 controlled by phase1 cannot be affected. During the disconnection process of the two switches 1tt controlled by phase1tt, theoretically only common-mode signals are introduced due to the consistency of the two switches 1tt controlled by phase1tt, but in practice a small amount of differential-mode signals exist due to the difference. The disconnection of the two switches 1t controlled by phase1t is between phase1 and phase1tt, and the connection is still guaranteed after the switch 1tt controlled by phase1tt is disconnected, eliminating the possibility of differential mode signals.

The present invention is a basic module for signal processing, which can perform front-end processing on externally input analog signals. It plays an important role in some applications, especially in analog-to-digital converters, and largely determines the linearity of the entire circuit degree and dynamic range. Applying the circuit proposed by the invention can effectively guarantee the speed and precision of analog-to-digital conversion.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. A sample-and-hold device, characterized in that: comprise a first-stage sample-and-hold circuit and a second-stage sample-and-hold circuit, the input positive and negative terminals of the first-stage sample-and-hold circuit are connected to external signals, and the first stage The output positive and negative terminals of the first-stage sample-and-hold circuit are coupled to the input positive and negative terminals of the second-stage sample-and-hold circuit, and the first-stage sample-and-hold circuit has a first-stage operational amplifier that realizes amplification with a multiple of less than one, so The second-stage sample-and-hold circuit has a second-stage operational amplifier that realizes amplification with a multiple greater than one. After the external signal is sampled, held, and amplified by the first and second-stage sample-and-hold circuits, it is transmitted from the second stage to The output positive and negative terminals of the first-stage sample-and-hold circuit are output; the output positive and negative terminals of the first-stage sample-and-hold circuit are directly connected to the input positive and negative terminals of the second-stage sample-and-hold circuit, and the second-stage A switching device is connected in series between the input positive and negative terminals of the sample and hold circuit. 2. sample-and-hold device as claimed in claim 1, is characterized in that: The first-stage sample-and-hold circuit further includes a first positive sampling capacitor, a first negative sampling capacitor, a first positive holding capacitor, and a first negative holding capacitor; One end of the first positive sampling capacitor is coupled to the input positive end of the first-stage sample-and-hold circuit and the first output end of the first-stage operational amplifier in a controllable on-off manner, and the other end is coupled to the first-stage operational amplifier. The first input terminal of the first-stage operational amplifier is coupled and coupled with the first output terminal of the first-stage operational amplifier through the first positive holding capacitor; One end of the first negative sampling capacitor is coupled with the input negative end of the first-stage sample-and-hold circuit and the second output end of the first-stage operational amplifier in a controllable on-off manner, and the other end is coupled with the first-stage operational amplifier. The second input terminal of the first-stage operational amplifier is coupled and coupled with the second output terminal of the first-stage operational amplifier through the first negative holding capacitor; The two ends of the first positive and negative storage capacitors can be controlled to be short-circuited. 3. The sample-and-hold device according to claim 2, characterized in that: the first and second input terminals of the first-stage operational amplifier are bridged by a switch device. 4. The sample-and-hold device according to any one of claims 1 to 3, characterized in that: The second-stage sample-and-hold circuit further includes a second positive sampling capacitor, a second negative sampling capacitor, a second positive holding capacitor, and a second negative holding capacitor; One end of the second positive sampling capacitor is coupled to the first output end of the first-stage operational amplifier, and the other end is coupled to the first input end of the second-stage operational amplifier and one end of the second positive holding capacitor , and is coupled with the first output terminal of the second-stage operational amplifier in a controllable on-off manner, and the other end of the second positive holding capacitor is respectively connected to the first-stage operational amplifier in a controllable on-off manner. The first output end is coupled to the first output end of the second-stage operational amplifier; One end of the second negative sampling capacitor is coupled to the second output end of the first-stage operational amplifier, and the other end is coupled to the second input end of the second-stage operational amplifier and one end of the second negative holding capacitor , and is coupled with the second output terminal of the second-stage operational amplifier in a controllable on-off manner, and the other end of the second negative holding capacitor is respectively connected to the first-stage operational amplifier in a controllable on-off manner The second output terminal is coupled to the second output terminal of the second-stage operational amplifier. 5. The sample-and-hold device according to claim 4, characterized in that: the first and second input ends of the second-stage operational amplifier are bridged by a switch device. 6 . The sample-and-hold device according to claim 4 , wherein the amplification with a multiple smaller than 1 is 1/2 magnification, and the magnification with a multiple greater than 1 is 2-fold magnification. 7. The sample-and-hold device according to claim 4, wherein the first-stage operational amplifier is a telescopic single-stage fully differential operational amplifier, and the second-stage operational amplifier is a two-stage fully differential operational amplifier. 8. A sample-and-hold method, characterized in that: comprise a first-order sample-and-hold stage and a second-order sample-and-hold stage, the holding time in the first-order sample-and-hold stage corresponds to the sampling time in the second-order sample-and-hold stage, In the first-stage sample-and-hold stage, the external signal is amplified with a multiple of less than one, and in the second-stage sample-and-hold stage, the signal obtained in the previous stage is amplified with a multiple greater than one. The two-stage signal amplification factor The superposition of meets the amplitude requirements for the sample and hold of the external signal; the output setup time allocated for the first sample and hold stage is shorter than the output setup time allocated for the second stage sample and hold stage. 9. The sample-and-hold method as claimed in claim 8, characterized in that: the hold time of the first-stage sample-and-hold stage is equal to or substantially equal to the sample time of the second-stage sample-hold stage, and the sample time of the first-stage sample-hold stage It is equal to or substantially equal to the hold time of the second-stage sample-and-hold stage.

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