CN215644467U

CN215644467U - Semiconductor chip structure and chip-on-film packaging structure

Info

Publication number: CN215644467U
Application number: CN202120770116.9U
Authority: CN
Inventors: 黄巧伶; 游腾瑞; 曾德修
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2020-08-25
Filing date: 2021-04-15
Publication date: 2022-01-25
Anticipated expiration: 2031-04-15
Also published as: TWM611894U

Abstract

The utility model provides a semiconductor chip structure and a chip-on-film packaging structure, wherein the semiconductor chip structure comprises a substrate, a plurality of output bump groups and a plurality of input bump groups. The substrate is formed with a driver circuit. Each of the plurality of output bump groups includes a plurality of output bumps, wherein two adjacent output bump groups of the plurality of output bump groups arranged along the longitudinal direction of the substrate respectively include output bumps The number difference between is less than or equal to 50. The plurality of input bump groups are disposed between two adjacent output bump groups arranged along the lateral direction of the substrate among the plurality of output bump groups.

Description

Semiconductor chip structure and chip-on-film packaging structure

Technical Field

The utility model relates to a semiconductor chip structure and a chip-on-film packaging structure.

Background

As electronic products are being developed to have features such as miniaturization, high speed, and high pin count, the packaging technology of Integrated Circuits (ICs) is also evolving in this direction, and the driving ICs on the display are no exception. The chip on film packaging process can provide the above functions, can be used for a flexible circuit board, and is suitable for packaging a driving chip of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), and the like.

Flip chip packaging generally refers to bonding a chip to a substrate through a metal conductor with an active surface facing down after the chip is flipped over. When applied to a flexible substrate such as a flexible printed circuit board, the Chip can be fixed On a Film and electrically connected to the flexible substrate only by a metal conductor, and thus is called a Chip On Film (COF).

With the increasing demand of the market for the resolution of the display, the number of pins of the driving chips increases, and in addition to the manufacturing process capability of the thin film package, the utilization of the circuit design, the size of the driving chips, and other considerations, the existing display panel usually needs to use two driving chips to be packaged on the same thin film, and because the wiring space between the two driving chips is not sufficient, the input/output bumps on the driving chips need to be configured in an asymmetric manner to vacate more wiring space, however, the above-mentioned special configuration can reduce the sharing of the driving chips, and easily causes the problem of uneven stress distribution.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to a semiconductor chip structure and a chip-on-film package structure, which can improve the sharing (compatibility) and the area utilization of a driver chip, and can improve the uneven stress distribution of the driver chip.

To achieve the above object, a semiconductor chip structure of the present invention includes a substrate, a plurality of output bump groups and a plurality of input bump groups. The substrate is formed with a driver circuit. The plurality of output bump groups each include a plurality of output bumps, wherein a difference in number between the output bumps included in each of the plurality of output bump groups is less than or equal to 50. The plurality of input bump groups are arranged between two adjacent output bump groups arranged in the plurality of output bump groups along the transverse direction of the substrate.

In an embodiment of the present invention, a difference in number between output bumps included in each of two adjacent output bump groups of the plurality of output bump groups arranged along the longitudinal direction of the substrate is less than or equal to 50.

In an embodiment of the present invention, the plurality of output bump groups include a plurality of first output bump groups and a plurality of second output bump groups respectively arranged in parallel with each other along a lateral direction of the substrate.

In an embodiment of the present invention, a difference between the number of output bumps included in each of the plurality of first output bump groups and the number of output bumps included in each of the plurality of second output bump groups is less than or equal to 50.

In an embodiment of the utility model, the plurality of input bump groups are respectively disposed between the plurality of first output bump groups and between the plurality of second output bump groups.

In an embodiment of the utility model, the number of the output bumps included in each of the plurality of output bump groups is between 100 and 300.

In an embodiment of the present invention, a pitch between the plurality of output bumps is less than or equal to 20 micrometers.

The chip on film package structure of the present invention includes one of the semiconductor chip structures described above and a film substrate. The semiconductor chip structure is arranged on the upper surface of the film base material and is electrically connected with the film base material.

In an embodiment of the utility model, the number of the semiconductor chip structures is plural, and the plural semiconductor chip structures are arranged on the film substrate in parallel.

In an embodiment of the utility model, the film substrate includes a plurality of output signal lines respectively connected to the plurality of output bumps, wherein a pitch between the plurality of output signal lines is between 18 micrometers and 25 micrometers.

In an embodiment of the present invention, the chip on film package structure further includes a heat dissipation film, and further attached to a lower surface of the film substrate opposite to the upper surface.

In an embodiment of the utility model, the heat dissipation film is further attached to the main surface and covers the semiconductor chip structure.

In an embodiment of the present invention, the heat dissipation membrane includes a heat dissipation aluminum membrane or a heat dissipation graphite membrane.

Based on the above, the advantage of the present invention is that the semiconductor chip structure reduces the distance between any two adjacent output bumps in each output bump group, so that each output bump group can be symmetrically configured, and the number of output bumps in each output bump group can be approximately similar (the number difference of each group is within 50), thereby reducing the problem of uneven stress distribution of the semiconductor chip structure, and improving the sharing and area utilization of the semiconductor chip structure. Moreover, the output bump groups are symmetrically arranged, so that the volume of the semiconductor chip structure can be reduced, and the yield of the semiconductor chip structure in a unit wafer can be improved.

The utility model has the advantages that the semiconductor chip structure is arranged on the film substrate to form the chip-on-film packaging structure, so that the space between two adjacent output bumps in the semiconductor chip structure is reduced, the whole width of the semiconductor chip structure is reduced, the wiring space among the semiconductor chip structures on the film substrate is increased, and the safety and the reliability of the chip-on-film packaging structure are improved.

In order to make the aforementioned and other features and advantages of the utility model more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic bottom view of a semiconductor chip structure according to an embodiment of the present invention;

FIG. 2 is a schematic top view of a chip on film package structure according to an embodiment of the utility model;

FIG. 3 is a schematic cross-sectional view of a chip on film package structure according to an embodiment of the utility model;

fig. 4 is a schematic cross-sectional view of a chip on film package structure according to another embodiment of the utility model.

Detailed Description

The foregoing and other technical and scientific aspects, features and utilities of the present invention will be apparent from the following detailed description of various embodiments, which is to be read in connection with the accompanying drawings. Directional terms as referred to in the following examples, for example: "upper", "lower", "front", "rear", "left", "right", etc., are simply directions with reference to the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. Also, in the following embodiments, the same or similar components will be given the same or similar reference numerals.

Fig. 1 is a bottom view of a semiconductor chip structure according to an embodiment of the utility model. Referring to fig. 1, in some embodiments, a semiconductor chip structure 100 includes a substrate 110, a plurality of output bump groups 120, and a plurality of input bump groups 130. The substrate 110 may be a bulk silicon substrate, although other semiconductor materials including group III, group IV, and group V elements may also be used. In other embodiments, the substrate 110 may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or other possible semiconductor substrates. In certain embodiments, the substrate 110 may include semiconductor components, such as germanium (Ge), or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

In some embodiments, the substrate 110 has formed therein a driving circuit configured to have a wiring that applies a voltage to or electrically connects semiconductor components such as transistors, capacitors and/or diodes and the like. In some embodiments, the semiconductor chip structure 100 may include various types. For example, in the present embodiment, the semiconductor chip structure 100 may be a driving chip of a display, and the driving circuit may be a circuit for generating a driving signal for driving a display panel. Of course, the present invention is not limited thereto, and the driving circuit may include various types of circuits performing functions according to the type of the semiconductor chip structure. For example, in other embodiments, the semiconductor chip structure may be other types of chips, such as a memory chip, and the driving circuit may be a circuit including a memory cell and its peripheral circuits. In some embodiments, the semiconductor chip structure 100 may include an active surface and a back surface opposite to the active surface, which is illustrated in fig. 1 as the active surface of the semiconductor chip structure 100, having a plurality of bumps for bonding with external electronic components.

In some embodiments, the plurality of output bump sets 120 may include two adjacent

output bump sets

122, 124 arranged along the longitudinal direction D1 of the substrate 110. In some embodiments, the output bump set 120 may include a plurality of first output bump sets 122 and a plurality of second output bump sets 124, wherein the plurality of first output bump sets 122 and the plurality of second output bump sets 124 may be respectively arranged parallel to each other along the transverse direction D2 of the substrate 110, for example, the plurality of first output bump sets 122 are arranged along the transverse direction D2 of the substrate 110, and the plurality of second output bump sets 124 may be arranged parallel to the first output bump sets 122. Specifically, the first output bump group 122 may be, for example, a plurality of output bump groups located in a first row of the substrate 110, and the second output bump group 124 may be, for example, a plurality of output bump groups located in a second row of the substrate 110. The

output bump sets

122, 124 may each include a plurality of output bumps. For example, the first output bump group 122 may each include a plurality of

output bumps

1221, 1222, and the second output bump group may each include a plurality of

output bumps

1241, 1242.

In some embodiments, the input bump set 130 is disposed between two adjacent output bump sets of the plurality of output bump sets 120 arranged along the transverse direction D2 of the substrate 110. In other words, the plurality of input bump groups 130 are respectively disposed between two adjacent first output bump groups 122 arranged along the transverse direction D2 of the substrate 110 and between two adjacent second output bump groups 124 arranged parallel to the first output bump groups 122. Further, the input bump set 130 may include a first input bump set 132 (including a plurality of input bumps 1321) and a second input bump set 134 (including a plurality of input bumps 1341), wherein the first input bump set 132 is disposed between two adjacent first output bump sets 122 arranged along the transverse direction D2 of the substrate 110, and the second input bump set 134 is disposed between two adjacent second output bump sets 124 arranged along the transverse direction D2 of the substrate 110.

In some embodiments, the pitch P1 between any two adjacent output bumps in each output bump group 120 may be less than or equal to about 20 microns. Under such a configuration, the number difference between the

output bumps

1221, 1222, 1241, 1242 included in each of the plurality of output bump groups 120 (including the output bump groups 122, 124) is less than or equal to 50. That is, the number of output bumps constituting each output bump group is substantially similar, and the difference between the numbers is less than or equal to 50. In some embodiments, the number of the

output bumps

1221, 1222, 1241, 1242 included in each of the output bump groups 120 may be between about 100 and 300. Further, in some embodiments, the two adjacent

output bump groups

122 and 124 of the output bump group 120 arranged along the longitudinal direction D1 of the substrate 110 each include a substantially similar number of output bumps, and the difference between the numbers is less than or equal to about 50. That is, the difference between the number of

output bumps

1221, 1222 included in each of the first output bump group 122 and the number of

output bumps

1241, 1242 included in each of the second output bump group 124 is less than or equal to 50. For example, the number of the

output bumps

1221 and 1222 is about 250, and the number of the

output bumps

1241 and 1242 is about 200, respectively, however, the above values are only for illustration and the utility model is not limited thereto.

Under the above configuration, the semiconductor chip structure 100 of the present embodiment reduces the pitch P1 between any two adjacent output bumps in each of the

output bump groups

122 and 124 to be less than or equal to 20 μm, so as to increase the installation space of the input bump group 130, and allow the input bump group 130 to be respectively disposed between the first output bump groups 122 and the second output bump groups 124, rather than being disposed on only one side (e.g., the lower side) of the semiconductor chip structure 100. Therefore, the

output bump groups

122 and 124 can be symmetrically arranged, and the number of the output bumps 1221, 1222, 1241 and 1242 in the

output bump groups

122 and 124 can be substantially similar (the number difference of each group is within 50), so that the problem of non-uniform stress distribution of the semiconductor chip structure 100 can be reduced, and the commonality and the area utilization rate of the semiconductor chip structure 100 can be improved.

In addition, the symmetrical arrangement of the

output bump groups

122 and 124 can minimize the space between two adjacent output bump groups arranged along the lateral direction D2, thereby reducing the overall width of the semiconductor chip structure 100 and increasing the aspect ratio of the semiconductor chip structure 100. In the present embodiment, the width W1 of the semiconductor chip structure 100 is reduced by about 500 microns to about 1000 microns, and the length L1 of the semiconductor chip structure 100 is increased by about 50 microns to about 200 microns. Moreover, the

output bump groups

122 and 124 are symmetrically arranged, so that the volume of the semiconductor chip structure 100 can be reduced, and the yield of the semiconductor chip structure 100 per wafer can be increased, i.e., more semiconductor chip structures 100 can be produced (cut) per wafer.

Fig. 2 is a schematic top view of a chip on film package structure according to an embodiment of the utility model. Referring to fig. 1 and fig. 2, in some embodiments, the semiconductor chip structure may be disposed on the upper surface of the film substrate 200 and electrically connected to the film substrate 200 to form the chip-on-film package structure 10 shown in fig. 2. In the present embodiment, the number of the semiconductor chip structures disposed on the film substrate 200 may be multiple (two are shown, but not limited thereto), that is, the chip-on-film package 10 may include a plurality of

semiconductor chip structures

100a and 100b disposed on the film substrate 200, and the

semiconductor chip structures

100a and 100b are disposed on the film substrate 200 in parallel. The structural configuration of the

semiconductor chip structures

100a, 100b (e.g., the configuration of the

output bump groups

120a, 120b and the

input bump groups

130a, 130 b) may be the same or at least similar to the structural configuration of the semiconductor chip structure 100 (e.g., the configuration of the output bump groups 120 and the input bump groups 130).

In some embodiments, the

semiconductor chip structures

100a and 100b may be electrically connected to the pins (e.g., outer pins and inner pins) of the film substrate 200 respectively by using flip chip bonding technology, but the utility model is not limited thereto. In some embodiments, the film substrate 200 can be a flexible substrate, and the material can be, for example, an organic transparent material, such as polyolefins, poly-sulfuryl, polyalcohols, polyesters, rubbers, thermoplastic polymers, thermosetting polymers, polyaromatic hydrocarbons, polymethyl propionyl acid methyl esters, polycarbonates, other suitable materials, derivatives thereof, or combinations thereof, but the utility model is not limited thereto.

In some embodiments, the film substrate 200 may correspondingly include a plurality of

output signal lines

210a, 210b respectively connected to the

output bump groups

120a, 120b of the

semiconductor chip structures

100a, 100 b. The film substrate 200 may further include a plurality of

input signal lines

220a, 220b respectively connected to the

input bump groups

130a, 130b of the

semiconductor chip structures

100a, 100 b. Moreover, the distance between two adjacent

output signal lines

210a and 210b may be between about 18 microns and about 25 microns. That is, in response to the pitch P1 between two adjacent output bumps in the

semiconductor chip structures

100a and 100b being reduced (less than or equal to 20 microns), the pitch between two corresponding adjacent

output signal lines

210a and 210b on the film substrate 200 may also be reduced to about 18 microns to about 25 microns. In some embodiments, the pitch P1 between two adjacent output bumps in the

semiconductor chip structures

100a and 100b is reduced to reduce the overall width of the semiconductor chip structure 100, thereby increasing the routing space between the two

semiconductor chip structures

100a and 100b on the film substrate 200. In addition, the distance between two corresponding adjacent

output signal lines

210a, 210b on the film substrate 200 is also reduced, and the number of traces between the

semiconductor chip structures

100a, 100b can be greatly increased, so that the arrangement of the output bumps in the

semiconductor chip structures

100a, 100b can be more flexible and can be designed symmetrically, and the sharing and area utilization rate of the

semiconductor chip structures

100a, 100b can be improved.

Fig. 3 is a schematic cross-sectional view of a chip on film package structure according to an embodiment of the utility model. Referring to fig. 3, in some embodiments, the above-mentioned chip-on-film package structure 10 may further include a heat dissipation film 400 attached to the lower surface of the film substrate 200 to help the chip-on-film package structure 10 dissipate heat. In the present embodiment, the semiconductor chip structure 100 (or the semiconductor chip structures 100a/100b) can be flip-chip bonded to the upper surface of the film substrate 200 through the i/o bumps 120/130 and electrically connected to the i/o signal lines 210/220 of the film substrate 200. The heat dissipation film 400 is disposed on the lower surface opposite to the upper surface. Also, the semiconductor chip structure 100 may at least partially overlap the heat dissipation film 400 when viewed from the top.

In some embodiments, the heat dissipation film 400 may further include a heat dissipation layer 410, an adhesive layer 420, and a protection layer 430, wherein the heat dissipation layer 410 may be attached to the lower surface of the film substrate 200 through the adhesive layer 420, and the protection layer 430 may completely cover the heat dissipation layer 410. In the embodiment, the passivation layer 430 may include an insulating film, and the heat dissipation layer 410 may include a metal (copper) foil, aluminum or graphite film, i.e., the heat dissipation film includes a heat dissipation copper film, a heat dissipation aluminum film or a heat dissipation graphite film, but the utility model is not limited thereto. In the present embodiment, as shown in fig. 3, the size of the protection layer 430 may be approximately larger than the size of the heat dissipation layer 410, and a protection distance is maintained between the outline of the protection layer 430 and the outline of the heat dissipation layer 410. Similarly, as shown in fig. 3, the size of the protective layer 430 is larger than that of the adhesive layer 420, and a protective distance is maintained between the outline of the protective layer 430 and the outline of the adhesive layer 420. That is, the protection layer 430 includes a boundary region surrounding the boundary of the heat dissipation layer 410 and the adhesive layer 420. Thus, when the heat dissipation film 400 is pressed to be attached to the film substrate 200, the problem of adhesive overflow can be avoided.

Fig. 4 is a schematic cross-sectional view of a chip on film package structure according to another embodiment of the utility model. Referring to fig. 3, in some embodiments, the number of the heat dissipation films may be multiple, and the number of the heat dissipation films may include a heat dissipation film 400a and a heat dissipation film 400b, which may have the same or at least similar structures as the heat dissipation films 400 described in the previous embodiments. The heat dissipation film 400a may include a heat dissipation layer 410a, an adhesive layer 420a and a protection layer 430a as described in the previous embodiments, and may be disposed (attached) on the lower surface of the film substrate 200, and the heat dissipation film 400b may be disposed on the upper surface of the film substrate 200 and cover the semiconductor chip structure 100. In detail, in the present embodiment, the chip on film package structure 10 may further include a solder mask layer 300 covering a portion of the i/o signal line 210/220, and the heat dissipation film 400b may cover (be attached to) the semiconductor chip structure 100 and the solder mask layer 300. The heat dissipation film 400b may also include a heat dissipation layer 410b, an adhesive layer (not shown), and a protection layer 430b, wherein the heat dissipation layer 410b may be attached to the semiconductor chip structure 100 and the solder mask layer 300 through the adhesive layer, and the protection layer 430b may cover the heat dissipation layer 410 b. In the present embodiment, the protection layer 430b may include an insulating film, and the heat dissipation layer 410b may include a metal (copper) foil, aluminum, or a graphite film, but the present invention is not limited thereto.

In summary, the semiconductor chip structure of the present invention reduces the distance between any two adjacent output bumps in each output bump group, so that each output bump group can be symmetrically configured, and the number of output bumps in each output bump group can be substantially similar (the number difference of each group is within 50), thereby reducing the problem of uneven stress distribution of the semiconductor chip structure, and improving the sharing and area utilization of the semiconductor chip structure. Moreover, the output bump groups are symmetrically arranged, so that the volume of the semiconductor chip structure can be reduced, and the yield of the semiconductor chip structure in a unit wafer can be improved.

The semiconductor chip structure is arranged on the film substrate to form the chip-on-film packaging structure, so that the space between two adjacent output bumps in the semiconductor chip structure is reduced, the whole width of the semiconductor chip structure is reduced, the wiring space among the semiconductor chip structures on the film substrate is increased, and the safety and the reliability of the chip-on-film packaging structure are improved. In addition, the chip on film package structure may further include a heat dissipation film attached to the upper and/or lower surface of the film substrate to help the chip on film package structure dissipate heat.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor chip structure, comprising:

a substrate in which a driver circuit is formed;

a plurality of output bump groups each including a plurality of output bumps, wherein a difference in number between the output bumps included in each of the plurality of output bump groups is less than or equal to 50; and

and the input bump groups are arranged between two adjacent output bump groups arranged in the plurality of output bump groups along the transverse direction of the substrate.

2. The semiconductor chip structure according to claim 1, wherein a difference in number between output bumps included in each of two adjacent output bump groups of the plurality of output bump groups arranged along the longitudinal direction of the substrate is less than or equal to 50.

3. The semiconductor chip structure according to claim 1, wherein the plurality of output bump groups comprises a plurality of first output bump groups and a plurality of second output bump groups respectively arranged in parallel with each other along a lateral direction of the substrate.

4. The semiconductor chip structure of claim 3, wherein a difference in number between the output bumps included in each of the first plurality of output bump groups and the output bumps included in each of the second plurality of output bump groups is less than or equal to 50.

5. The semiconductor chip structure of claim 3, wherein the plurality of input bump groups are respectively disposed between the plurality of first output bump groups and between the plurality of second output bump groups.

6. The semiconductor chip structure of claim 1, wherein the plurality of output bump groups each include between 100 and 300 output bumps.

7. The semiconductor chip structure of claim 1, wherein a pitch between the plurality of output bumps is less than or equal to 20 microns.

8. A chip-on-film package structure, comprising:

a semiconductor chip structure according to one of the semiconductor chip structures of claims 1 to 7; and

the semiconductor chip structure is arranged on the upper surface of the film base material and is electrically connected with the film base material.

9. The chip on film package structure of claim 8, wherein the number of the semiconductor chip structures is plural, and the plural semiconductor chip structures are disposed on the film substrate in parallel.

10. The chip on film package structure of claim 8, wherein the film substrate comprises a plurality of output signal lines respectively connected to the plurality of output bumps, and a pitch between the plurality of output signal lines is between 18 microns and 25 microns.

11. The chip on film package structure of claim 8, further comprising a heat dissipation film attached to a lower surface of the film substrate opposite to the upper surface.

12. The chip on film package structure of claim 11, wherein the heat dissipation film is further attached to the upper surface and covers the semiconductor chip structure.

13. The chip on film package structure of claim 11, wherein the heat dissipation film comprises a heat dissipation aluminum film or a heat dissipation graphite film.