CN215069937U - WLP packaging device of infrared sensor - Google Patents
WLP packaging device of infrared sensor Download PDFInfo
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- CN215069937U CN215069937U CN202120802632.5U CN202120802632U CN215069937U CN 215069937 U CN215069937 U CN 215069937U CN 202120802632 U CN202120802632 U CN 202120802632U CN 215069937 U CN215069937 U CN 215069937U
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Abstract
The utility model relates to an infrared sensor WLP packaging device, which comprises a lower wafer, a plurality of chips formed on the end surface of the lower wafer, an upper wafer covered above the lower wafer, and a plurality of supporting salient points formed between the lower wafer and the upper wafer; the lower wafers and the upper wafers corresponding to the chips are fixedly sealed and welded through welding fluxes, and fixed vacuum gaps are formed by combining the supporting action of the supporting salient points inside the chips; the utility model discloses mainly be applied to infrared sensor, have a fixed clearance through supporting the bump messenger between last wafer and the lower wafer, play the supporting role in the sealing and welding process under vacuum environment, avoid traditional equipment control to have the problem of error and high homogeneity, effectively improve the product yield, preparation convenient and fast saves the cost.
Description
Technical Field
The utility model relates to an infrared sensor wafer level encapsulation technical field, in particular to infrared sensor WLP encapsulates device.
Background
The infrared sensor chip needs to work in a high vacuum environment, so that the requirement on the sealing and welding air tightness is high, if the solder does not reach a proper thickness, the air tightness is poor, even air leakage is caused, tin overflow is possible to cause the yield to be reduced, and the performance of the chip is further influenced; in the prior art, equipment is used for controlling the height of solder, the equipment control has the problems of error and height uniformity, the yield is low, and the increase of a control module can cause the increase of equipment cost; consequently the utility model discloses an infrared sensor WLP encapsulates device has been developed to solve the problem that exists among the prior art, through the retrieval, not discover with the utility model discloses same or similar technical scheme.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the purpose is: the utility model provides an infrared sensor WLP packaging device to solve the problem that the solder thickness control is improper when wafer level packaging in the prior art, and easily causes the performance of chip to descend.
The technical scheme of the utility model is that: an infrared sensor WLP packaging device comprises a lower wafer, a plurality of chips formed on the end face of the lower wafer, an upper wafer covering the upper part of the lower wafer, and a plurality of supporting salient points formed between the lower wafer and the upper wafer; the lower wafers and the upper wafers corresponding to the chips are fixedly sealed and welded through welding fluxes, and the inner parts of the lower wafers and the upper wafers are combined with the supporting action of the supporting salient points to form fixed vacuum gaps.
Preferably, the support bumps are formed by planting balls on the chips, and each chip is provided with a PAD area for planting the balls.
Preferably, the support bump formed by the ball implantation is one of gold balls, tin balls, copper balls or alloys formed by any combination of the gold balls, the tin balls and the copper balls, and the melting point of the support bump is higher than that of the solder.
Preferably, the supporting salient points are formed by etching the lower end face of the upper wafer, and the chip corresponding to the supporting salient points is provided with a supporting area for the supporting salient points to abut against.
Preferably, the support salient points are formed by growing metal layers on the lower end surface of the upper wafer alone, the upper end surface of the lower wafer alone or on the upper end surface of the upper wafer and the upper end surface of the lower wafer together, and when the support salient points are positioned on the upper wafer, a support area for the support salient points to abut against is arranged on the chip corresponding to the lower wafer.
Preferably, the solder is in an annular band structure or an annular structure formed by surrounding a plurality of points, and is arranged on the upper end surface of the lower wafer or the lower end surface of the upper wafer, and gold-plated layers are arranged on the upper end surface of the lower wafer and the lower end surface of the upper wafer which are opposite to the solder.
Preferably, the thickness of the solder is greater than the height of the support bump.
Preferably, the position where the supporting bump abuts against or is connected with the chip is located on an inner region of the solder, or an outer region of the solder, or a gold plating layer opposite to the solder.
Preferably, a getter is arranged on the lower end face of the upper wafer.
Compared with the prior art, the utility model has the advantages that:
(1) the utility model discloses mainly be applied to infrared sensor, have a fixed clearance through supporting the bump messenger between last wafer and the lower wafer, play the supporting role in the sealing and welding process under vacuum environment, avoid traditional equipment control to have the problem of error and high homogeneity, effectively improve the product yield, preparation convenient and fast saves the cost.
(2) The supporting salient points can be formed by implanting balls on part of the chip, can also be formed by etching the lower end face of the upper wafer, and can also be formed by singly growing metal layers on the lower end face of the upper wafer, singly growing metal layers on the upper end face of the lower wafer, or jointly growing metal layers on the lower end face of the upper wafer and the upper end face of the lower wafer; because the solder is required to be thermally melted at high temperature to connect the upper wafer and the lower wafer, and the supporting bumps are required to be always used for supporting in the process, the melting point of the supporting bumps formed by the ball planting is required to be higher than that of the solder.
(3) And the getter is arranged on the lower end face of the upper wafer, so that the vacuum degree in the chip is effectively ensured in the sealing and welding process, and the product performance is further improved.
Drawings
The invention will be further described with reference to the following drawings and examples:
fig. 1 is a schematic structural diagram of an infrared sensor WLP package device according to embodiment 1 of the present invention;
fig. 2 is an enlarged view of a partial structure of an infrared sensor WLP package device in embodiment 1 at a in fig. 1;
fig. 3 is a schematic structural diagram of a single chip formed on a lower wafer according to embodiment 1 of the present invention, wherein the solder has an annular band structure;
fig. 4 is a schematic structural diagram of a single chip formed on a lower wafer according to embodiment 1 of the present invention, wherein the solder is in a ring-shaped structure surrounded by dots;
fig. 5 is an enlarged view of a partial structure of the upper wafer and the lower wafer according to embodiment 1 of the present invention when the upper wafer and the lower wafer are not sealed;
fig. 6 is an enlarged view of a partial structure of an upper wafer and a lower wafer in the sealing process according to embodiment 1 of the present invention;
fig. 7 is an enlarged view of a partial structure of an upper wafer and a lower wafer according to embodiment 2 of the present invention when the upper wafer and the lower wafer are not sealed;
fig. 8 is an enlarged view of a partial structure of an upper wafer and a lower wafer in the sealing process according to embodiment 2 of the present invention;
fig. 9 is an enlarged view of a partial structure of an upper wafer and a lower wafer according to embodiment 3 of the present invention when the upper wafer and the lower wafer are not sealed;
fig. 10 is an enlarged view of a partial structure of the upper wafer and the lower wafer according to embodiment 3 of the present invention during the sealing process.
Wherein: 1. the manufacturing method comprises the following steps of a lower wafer, 2, a chip, 3, an upper wafer, 4, supporting bumps, 5, solder, 6, a PAD area, 7, a gold-plated layer, 8 and a vacuum gap.
Detailed Description
The following detailed description is made in conjunction with specific embodiments of the present invention:
example 1
As shown in fig. 1 and 2, an infrared sensor WLP package device includes a lower wafer 1, a plurality of chips 2 formed on an end surface of the lower wafer 1 by a process, an upper wafer 3 covering the lower wafer 1, and a plurality of support bumps 4 formed between the lower wafer 1 and the upper wafer 3; the lower wafer 1 and the upper wafer 3 corresponding to the chips 2 are fixedly sealed and welded through the solder 5, and the inner parts of the lower wafer and the upper wafer are combined with the supporting action of the supporting salient points 4 to form a fixed vacuum gap 8.
In the present embodiment, as shown in fig. 3, the supporting bumps 4 are formed by mounting balls on the chips 2, that is, 4a in the drawing, each chip 2 is provided with a PAD area 6 for mounting balls, the PAD area 6 is not connected to a circuit on the chip 2, but ball mounting does not need to be performed on each chip 2, and the number of the ball mounting is not limited; the supporting salient points 4a formed by the embedded balls are made of one of gold balls, tin balls, copper balls or alloys formed by any combination of the gold balls, the tin balls and the copper balls, the melting point of the supporting salient points 4a is higher than that of the solder 5, and the supporting salient points 4a cannot play an effective supporting role when the solder 5 is hot melted is avoided.
As shown in fig. 3, the solder 5 may be in an annular band structure, as shown in fig. 4, or in an annular structure surrounded by dots, and when the solder is melted by heat, all the dot structures are also melted by heat to form a whole; the solder 5 can be arranged on the upper end surface of the lower wafer 1 or the lower end surface of the upper wafer 3, and the thickness of the solder 5 is larger than the height of the supporting salient points 4 a; as shown in fig. 5, gold plating layers 7 are provided on both the upper end surface of the lower wafer 1 and the lower end surface of the upper wafer 3 facing the solder 5.
In the present embodiment, the specific position of the ball-planting on the chip 2 is not limited, and the schematic diagram of the area inside the solder 5 is shown in the figure, and the area outside the solder 5, or the gold-plated layer 7 opposite to the solder 5 can be used.
When the upper wafer 3 and the lower wafer 1 are connected in a sealing and welding mode, the sealing and welding are carried out in a vacuum environment, meanwhile, a getter is arranged on the lower end face of the upper wafer 3, the vacuum degree in the chip 2 is effectively guaranteed in the sealing and welding process, and the product performance is further improved; as shown in fig. 6, the height of the vacuum gap 8 between the two is the same as that of the supporting bump 4a, and the solder 5 is higher than that of the supporting bump 4a, so that the solder 5 overflows to both sides during the thermal melting process, and fills the joint between the upper wafer 3 and the lower wafer 1, thereby effectively ensuring the air tightness of the vacuum gap 8.
Example 2
The present embodiment is different from embodiment 1 in that: as shown in fig. 7, the supporting bumps 4 are formed by etching the lower end surface of the upper wafer 3, i.e., 4b in the figure, and the corresponding chip 2 is provided with a supporting area for the supporting bumps 4b to abut against, and the supporting bumps 4b do not need to be arranged corresponding to each chip 2, and only need to be uniformly distributed between the upper wafer 3 and the lower wafer 1; as shown in fig. 8, when the upper wafer 3 and the lower wafer 1 are sealed and connected, the supporting bumps 4b are used as supports, and the solder 5 still overflows to both sides and fills the space between the upper wafer 3 and the lower wafer 1 at the connection position.
In the present embodiment, the specific position where the supporting bump 4b abuts against the chip 2 is not limited, and may be on the inner side region of the solder 5, the outer side region of the solder 5, or the gold-plated layer 7 opposite to the solder 5, which is schematically illustrated in the figure as being in the inner side region of the solder 5.
Example 3
The present embodiment is different from embodiment 1 in that: as shown in fig. 9, the support bumps 4 are formed by growing a metal layer on the lower end surface of the upper wafer 3 alone, or on the upper end surface of the lower wafer 1 alone, or on both the lower end surface of the upper wafer 3 and the upper end surface of the lower wafer 1, i.e. 4c in the figure, a schematic diagram of the support bumps 4c on the upper wafer 3 or the lower wafer 1 is shown by a dotted line structure in the figure, and when the support bumps 4c are on the upper wafer 3, a support region for the support bumps 4c to abut against is disposed on the chip 2 corresponding to the lower wafer 1; the number of the supporting bumps 4c is not limited, and the supporting bumps do not need to be arranged corresponding to each chip 2; as shown in fig. 10, when the upper wafer 3 and the lower wafer 1 are sealed and connected, the supporting bumps 4c are used as supports, and the solder 5 still overflows to both sides and fills the space between the upper wafer 3 and the lower wafer 1 at the connection position.
In the present embodiment, the specific position where the supporting bump 4c is connected to or abutted against the chip 2 is not limited, and may be on the inner side region of the solder 5, the outer side region of the solder 5, or the gold-plated layer 7 opposite to the solder 5, and the figure shows a schematic view of the outer side region of the solder 5.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. It is obvious to a person skilled in the art that the invention is not limited to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention, and that the embodiments are therefore to be considered in all respects as exemplary and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. An infrared sensor WLP packaged device, characterized in that: the chip packaging structure comprises a lower wafer, a plurality of chips formed on the end face of the lower wafer, an upper wafer covered above the lower wafer, and a plurality of supporting salient points formed between the lower wafer and the upper wafer; the lower wafers and the upper wafers corresponding to the chips are fixedly sealed and welded through welding fluxes, and the inner parts of the lower wafers and the upper wafers are combined with the supporting action of the supporting salient points to form fixed vacuum gaps.
2. An infrared sensor WLP package device as recited in claim 1, wherein: the supporting salient points are formed by planting balls on the chips, and each chip is provided with a PAD area for planting the balls.
3. An infrared sensor WLP package device as recited in claim 2, wherein: the supporting salient points formed by the embedded balls are made of one of gold balls, tin balls, copper balls or alloys formed by any combination of the gold balls, the tin balls and the copper balls, and the melting point of the supporting salient points is higher than that of the solder.
4. An infrared sensor WLP package device as recited in claim 1, wherein: the supporting salient points are formed by etching the lower end face of the upper wafer, and supporting areas for the supporting salient points to abut against are arranged on the corresponding chips.
5. An infrared sensor WLP package device as recited in claim 1, wherein: the supporting salient points are formed by growing metal layers on the lower end face of the upper wafer alone, the upper end face of the lower wafer alone or on the upper end face of the upper wafer and the upper end face of the lower wafer together, and when the supporting salient points are positioned on the upper wafer, a supporting area for the supporting salient points to abut against is arranged on the chip corresponding to the lower wafer.
6. An infrared sensor WLP package device as recited in claim 2, 4 or 5, wherein: the welding flux is in an annular band structure or an annular structure formed by surrounding a plurality of points, and is arranged on the upper end surface of the lower wafer or the lower end surface of the upper wafer, and gold-plated layers are arranged on the upper end surface of the lower wafer and the lower end surface of the upper wafer which are opposite to the welding flux.
7. An infrared sensor WLP package device as recited in claim 6, wherein: the thickness of the solder is greater than the height of the supporting bump.
8. An infrared sensor WLP package device as recited in claim 6, wherein: the position where the supporting salient point is abutted or connected with the chip is positioned on the inner side area of the solder, or the outer side area of the solder, or the gold plating layer opposite to the solder.
9. An infrared sensor WLP package device as recited in claim 2, 4 or 5, wherein: and a getter is arranged on the lower end face of the upper wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120802632.5U CN215069937U (en) | 2021-04-19 | 2021-04-19 | WLP packaging device of infrared sensor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120802632.5U CN215069937U (en) | 2021-04-19 | 2021-04-19 | WLP packaging device of infrared sensor |
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| CN215069937U true CN215069937U (en) | 2021-12-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113161304A (en) * | 2021-04-19 | 2021-07-23 | 江苏鼎茂半导体有限公司 | WLP packaging device of infrared sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113161304A (en) * | 2021-04-19 | 2021-07-23 | 江苏鼎茂半导体有限公司 | WLP packaging device of infrared sensor |
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Effective date of registration: 20220829 Address after: 311501 building A1, no.299 Qiushi Road, Tonglu Economic Development Zone, Tonglu County, Hangzhou City, Zhejiang Province Patentee after: Hangzhou Haikang Micro Shadow Sensing Technology Co.,Ltd. Address before: No.13 workshop, Dongjing industrial square, No.8 Dongfu Road, Loufeng, Suzhou Industrial Park, Jiangsu Province, 215000 Patentee before: JIANGSU DINGMAO SEMICONDUCTOR Co.,Ltd. |