CN214068715U - System-in-package structure and electronic equipment - Google Patents
System-in-package structure and electronic equipment Download PDFInfo
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- CN214068715U CN214068715U CN202023026674.9U CN202023026674U CN214068715U CN 214068715 U CN214068715 U CN 214068715U CN 202023026674 U CN202023026674 U CN 202023026674U CN 214068715 U CN214068715 U CN 214068715U
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- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000004806 packaging method and process Methods 0.000 claims abstract description 39
- 239000004033 plastic Substances 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000000465 moulding Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 11
- 238000003466 welding Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004984 smart glass Substances 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 229920000840 ethylene tetrafluoroethylene copolymer Polymers 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a system level packaging structure and electronic equipment, include: a substrate base plate; a plurality of first passive devices and at least one chip are attached to one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate; the plastic packaging layer is positioned on one side, away from the substrate, of the chip, covers at least one chip, and is hollowed out at a position, corresponding to at least one first passive device, of the plastic packaging layer; and a second passive device is stacked at the hollow part and connected with the first passive device through an external terminal. The utility model provides a technical scheme through piling up first passive device and second passive device mutually and realizing the encapsulation, avoids first passive device and second passive device to expand the subsides dress on the substrate base plate and appear the great problem of area occupied, and then effectively solves the great problem of system level packaging structure area occupied that prior art exists, has optimized system level packaging structure's size.
Description
Technical Field
The utility model relates to a packaging technology field, more specifically say, relate to a system level packaging structure and electronic equipment.
Background
With the continuous development of integrated circuit technology, electronic products are increasingly developing toward miniaturization, intellectualization, high performance and high reliability. The integrated circuit package not only directly affects the performance of the integrated circuit, the electronic module and even the complete machine, but also restricts the miniaturization, low cost and reliability of the whole electronic system.
In substrate type packaging, for example, SIP (System In a Package System In Package) has the characteristics of high flexibility, high integration level, relatively low cost, small area, high frequency, high speed and short production period, and the SIP packaging technology can be widely applied to the fields of industrial application and internet of things, and also has a very wide market In the fields of mobile phones, smart watches, smart bracelets, smart glasses and the like. By applying the SIP system miniaturization design, the system design can be simplified and the equipment miniaturization can be met in a multi-element integration mode. The advantages of portability, wireless performance and instantaneity of the product can be increased without changing the appearance. But the existing SIP structure occupies a large area.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a system in package structure and electronic equipment effectively solves the great problem of system in package structure area occupied that prior art exists, has optimized system in package structure's size.
In order to achieve the above purpose, the utility model provides a technical scheme as follows:
a system in a package structure, comprising:
a substrate base plate;
a plurality of first passive devices and at least one chip are attached to one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate;
the plastic packaging layer is positioned on one side, away from the substrate, of the chip, covers the at least one chip, and is hollowed out at a position, corresponding to the at least one first passive device, of the plastic packaging layer;
and a second passive device is stacked at the hollow part and connected with the first passive device through the external terminal.
Optionally, the chip includes a first sub-chip to an nth sub-chip, where N is an integer equal to or greater than 2;
the first sub-chip to the Nth sub-chip are sequentially stacked and attached to one side of the substrate base plate.
Optionally, the molding layer includes at least one of silicon dioxide and epoxy resin.
Optionally, a welding metal layer is further disposed on one side of the external terminal, which is away from the substrate base plate.
Optionally, the solder metal layer comprises a tin metal layer.
Optionally, the external terminal is a copper pillar.
Optionally, the plurality of first passive devices are disposed around the at least one chip.
Optionally, the substrate base plate is a circuit board.
Correspondingly, the utility model also provides an electronic equipment, electronic equipment includes foretell system level packaging structure.
Compared with the prior art, the utility model provides a technical scheme has following advantage at least:
the utility model provides a system level packaging structure and electronic equipment, include: a substrate base plate; a plurality of first passive devices and at least one chip are attached to one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate; the plastic packaging layer is positioned on one side, away from the substrate, of the chip, covers the at least one chip, and is hollowed out at a position, corresponding to the at least one first passive device, of the plastic packaging layer; and a second passive device is stacked at the hollow part and connected with the first passive device through the external terminal.
According to the above, the utility model provides a technical scheme piles up the realization encapsulation mutually through with first passive device and second passive device, avoids first passive device and second passive device to expand the dress on the substrate base plate and appear the great problem of area occupied, and then effectively solves the great problem of system level packaging structure area occupied that prior art exists, has optimized system level packaging structure's size.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a system-level packaging method according to an embodiment of the present invention;
FIGS. 2-6 are schematic views of the respective steps in FIG. 1;
fig. 7 is a schematic structural diagram of an intermediate process of a system-in-package structure according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a system-in-package structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As described In the background art, for example, the SIP (System In a Package System In Package) In the substrate type Package has the characteristics of high flexibility, high integration level, relatively low cost, small area, high frequency, high speed, and short production period, and the SIP packaging technology can be widely applied to the fields of industrial application and internet of things, and also has a very wide market In the fields of mobile phones, smart watches, smart bracelets, smart glasses, and the like. By applying the SIP system miniaturization design, the system design can be simplified and the equipment miniaturization can be met in a multi-element integration mode. The advantages of portability, wireless performance and instantaneity of the product can be increased without changing the appearance. But the existing SIP structure occupies a large area.
Based on this, the embodiment of the utility model provides a system level packaging method and structure and electronic equipment effectively solves the great problem of system level packaging structure area occupied that prior art exists, has optimized system level packaging structure's size.
In order to achieve the above object, embodiments of the present invention provide the following technical solutions, which are described in detail with reference to fig. 1 to 8.
Referring to fig. 1, a flow chart of a system-in-package method according to an embodiment of the present invention is shown, wherein the method includes:
s1, providing a substrate base plate.
S2, mounting a plurality of first passive devices and at least one chip on one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate.
And S3, forming a plastic package layer covering the first passive device and the at least one chip.
And S4, forming a hollow at the position of the plastic packaging layer corresponding to at least one first passive device.
S5, stacking a second passive device at the hollow-out position, wherein the second passive device is connected with the first passive device through the external terminal.
It should be noted that, the embodiment of the present invention provides a after forming the plastic packaging layer covering the first passive device and the chip, it is necessary to form a hollow portion corresponding to at least one first passive device on the plastic packaging layer, i.e. the plastic packaging layer exposes the at least one passive device, and the second passive device is stacked on the first passive device, and finally the first passive device and the second passive device are stacked in the vertical direction.
It can be understood, the embodiment of the utility model provides a technical scheme piles up the realization encapsulation mutually through with first passive device and second passive device, avoids first passive device and second passive device to expand the dress and appear the great problem of area occupation on the substrate base plate horizontal direction, and then effectively solves the great problem of system level packaging structure area occupation that prior art exists, has optimized system level packaging structure's size.
The system-in-package method provided by the embodiment of the present invention is described in more detail below with reference to fig. 2 to 6, and fig. 2 to 6 are schematic structural diagrams corresponding to the steps in fig. 1.
As shown in fig. 2, corresponding to step S1, a substrate 100 is provided.
In an embodiment of the present invention, the substrate provided by the present invention can be a circuit board. Wherein one side surface of substrate base plate is used for pasting the components and parts, and the opposite side surface of substrate base plate can set up external pin etc. to this the utility model discloses do not do specific restriction.
As shown in fig. 3, corresponding to step S2, a plurality of first passive devices 210 and at least one chip 220 are mounted on one side of the substrate 100, wherein the first passive devices 210 include external terminals 211 facing away from the substrate 100.
The utility model provides a first passive device can be for resistance, electric capacity, inductance etc. to this needs carry out the concrete design according to practical application and select, the utility model discloses do not specifically restrict. The embodiment of the utility model provides a when first passive device pastes dress with the substrate base plate, can directly paste the pad pin department of adorning in this side of substrate base plate for first passive device realizes the electricity with the circuit of substrate base plate and is connected.
The embodiment of the utility model provides an external terminal deviates from substrate base plate one side still is provided with the welding metal level, and wherein external terminal can be the copper post, and wherein the copper post deviates from substrate base plate one side and can also have electroplated welding metal level to in the welding of piling up of follow-up second passive device. Wherein the solder metal layer may be a tin metal layer. Furthermore, the embodiment of the utility model provides an external terminal can be single terminal, still can be for the combination of a plurality of terminals, to this needs carry out concrete design according to the type of first passive device etc. the utility model discloses do not do specific restriction.
In an embodiment of the utility model, the utility model provides a during chip and substrate base plate subsides dress, can pass through mode subsides such as adhesive with the chip in this side of substrate base plate, then realize the electricity of chip and substrate base plate's circuit through routing modes such as bonding wire and be connected, to this the utility model discloses do not specifically restrict equally. And, the embodiment of the utility model provides a first passive component can be the mode setting that encircles the chip, carries out concrete design according to practical application to this needs.
The embodiment of the utility model provides a do not do specific restriction to the subsides dress precedence order of the first passive device that provides and chip and substrate base plate, need specifically select according to practical application. Optionally, mounting a plurality of first passive devices and at least one chip on one side of the substrate base plate, includes: and mounting a plurality of first passive devices on one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate. And mounting a chip on one side of the substrate base plate, which is provided with the first passive device. And connecting the chip with the substrate base plate through a bonding wire.
In an embodiment of the present invention, the one or more chips provided by the present invention include a first sub-chip to an nth sub-chip, where N is an integer equal to or greater than 2; wherein a chip is mounted on one side of the substrate base plate, comprising: sequentially stacking and mounting the first sub-chip to the Nth sub-chip on one side of the substrate base plate; and respectively connecting the first sub-chip to the Nth sub-chip with the substrate base plate through bonding wires. The multiple sub-chips are stacked, so that the occupied area of the chips can be reduced, and the occupied area of the system-in-package structure is further reduced. As shown in fig. 3, the chip 220 provided in the embodiment of the present invention may include a first sub-chip 221 and a second sub-chip 222, wherein the first sub-chip 221 and the second sub-chip 222 are stacked, and the first sub-chip 221 and the second sub-chip 222 are connected to the substrate 100 through a bonding wire 223.
As shown in fig. 4, corresponding to step S3, a molding layer 300 is formed to cover the first passive device 210 and the chip 220.
In an embodiment of the present invention, the plastic package layer includes at least one of silicon dioxide and epoxy resin. Further, the utility model provides a plastic envelope layer still includes some microelement, reaches the purpose that improves the sealed effect of plastic envelope layer, to this microelement type the utility model discloses do not specifically restrict.
As shown in fig. 5, corresponding to step S4, a hollow is formed at a position of the molding layer 300 corresponding to at least one of the first passive devices 210.
The embodiment of the utility model provides a need get rid of the part that the plastic envelope layer corresponds at least one first passive device and form the fretwork, this fretwork is the headspace that is used for piling up the second passive device promptly. Optionally, when the first passive device provided in the embodiment of the present invention is located at the edge of the system in package structure, the hollow portion may also extend to the outer side of the edge, so as to facilitate stacking of the second passive device. The embodiment of the present invention provides a plurality of first passive devices, which can be disposed around the at least one chip, and therefore the present invention is not limited thereto.
The embodiment of the utility model provides a can adopt and form the fretwork to modes such as plastic envelope sculpture promptly the plastic envelope corresponds at least one first passive device department forms the fretwork, include: adopt etching process to be in the plastic envelope layer corresponds at least one first passive device department forms the fretwork, the embodiment of the utility model provides a do not do specific restriction to etching process, need carry out the selection of specific technology according to the concrete material of plastic envelope layer. Or before forming a molding layer covering the first passive device and the chip, the method further comprises: arranging a shielding protective film on one side of at least one first passive device, which is far away from the substrate base plate; and removing the shielding protective film to remove the part of the plastic packaging layer corresponding to at least one first passive device to form the hollow part. With reference to fig. 7, the embodiment of the present invention can cover the surface of the first passive device 210 deviating from the substrate base plate 100 side by shielding the protection film 310 before forming the plastic package layer 300, and the protection film 310 is reserved to take off the handle-like structure, and then after forming the plastic package layer 300, the protection film 310 is covered by the handle-removing skill through reservation, and the plastic package portion on the protection film 310 is taken off to form a hollow-out.
In an embodiment of the present invention, the material of the shielding protection film includes at least one of ETFE and PET.
As shown in fig. 6, corresponding to step S5, a second passive device 400 is stacked at the hollow, and the second passive device 400 is connected to the first passive device 210 through the external connection terminal 211.
The utility model provides a passive device of second can be for resistance, electric capacity, inductance etc. and carry out the concrete design according to practical application and select to this needs, the utility model discloses do not specifically restrict. Therefore, the first passive device and the second passive device are stacked to realize packaging, and the problem that the first passive device and the second passive device are spread on the substrate and are pasted on the substrate to cause large occupied area is avoided.
Based on same utility model design, the embodiment of the utility model provides a system level packaging structure is still provided, and system level packaging structure adopts the method preparation that an above-mentioned arbitrary embodiment provided to form, and wherein, system level packaging structure includes:
a base substrate 100.
A plurality of first passive devices 210 and at least one chip 220 are mounted on one side of the substrate 100, wherein the first passive devices 210 include external terminals 211 facing away from the substrate 100.
The molding compound layer 300 is located on a side of the chip 220 away from the substrate base plate 100, the molding compound layer 300 covers the at least one chip 220, and a position of the molding compound layer 300 corresponding to the at least one first passive device 210 is hollowed out.
A second passive device 400 is stacked at the hollow portion, and the second passive device 400 is connected to the first passive device 210 through the external terminal 211.
In an embodiment of the present invention, the substrate provided by the present invention can be a circuit board, and the circuit board can be a printed circuit board, which is not limited by the present invention.
It can be understood that the utility model provides a plastic envelope covers substrate base plate has the exposed surface of first passive device and chip one side, and the plastic envelope corresponds at least one first passive device department and still sets up to the fretwork, for follow-up second passive device headspace that piles up. The embodiment of the utility model provides a technical scheme through piling up first passive device and second passive device mutually and realizing the encapsulation, avoids first passive device and second passive device to expand the subsides dress and appear the great problem of area occupation on the substrate base plate, and then effectively solves the great problem of system level packaging structure area occupation that prior art exists, has optimized system level packaging structure's size.
The utility model provides a first passive device can be for resistance, electric capacity, inductance etc. to this needs carry out the concrete design according to practical application and select, the utility model discloses do not specifically restrict. The embodiment of the utility model provides a when first passive device pastes dress with the substrate base plate, can directly paste the pad pin department of adorning in this side of substrate base plate for first passive device realizes the electricity with the circuit of substrate base plate and is connected.
And, the utility model provides a second passive device can be for resistance, electric capacity, inductance etc. to this needs carry out concrete design according to practical application and select, the utility model discloses do not specifically restrict. Therefore, the first passive device and the second passive device are stacked to realize packaging, and the problem that the first passive device and the second passive device are spread on the substrate and are pasted on the substrate to cause large occupied area is avoided.
Optionally, the utility model provides an external terminal deviates from substrate base plate one side still is provided with the welding metal level, and wherein external terminal can be the copper post, wherein the copper post deviates from substrate base plate one side can also be electroplated with the welding metal level to the welding of piling up of follow-up second passive device. Wherein the solder metal layer may be a tin metal layer. Furthermore, the embodiment of the utility model provides an external terminal can be single terminal, still can be for the combination of a plurality of terminals, to this needs carry out concrete design according to the type of first passive device etc. the utility model discloses do not do specific restriction.
In an embodiment of the utility model, the utility model provides a during chip and substrate base plate subsides dress, can pass through the subsides such as adhesive with the chip and adorn in this side of substrate base plate, then realize the electricity of chip and substrate base plate's circuit through routing modes such as bonding wire and be connected, to this the utility model discloses do not specifically restrict equally. And, the embodiment of the utility model provides a first passive component can be the mode setting that encircles the chip, carries out concrete design according to practical application to this needs.
One or more chips provided by the utility model can be of a single sub-chip structure; or, one or more chips provided by the embodiments of the present invention may further include a plurality of sub-chips, that is, the chip provided by the present invention includes a first sub-chip to an nth sub-chip, where N is an integer equal to or greater than 2; in the direction from the substrate base plate to the chip, the first sub chip to the Nth sub chip are sequentially stacked and attached to one side of the substrate base plate; the first sub-chip to the Nth sub-chip are respectively connected with the substrate through bonding wires, wherein the plurality of sub-chips are stacked to reduce the occupied area of the chip, and further reduce the occupied area of the system-in-package structure. As shown in fig. 8, the chip 220 provided by the embodiment of the present invention may include a first sub-chip 221 and a second sub-chip 222, wherein the first sub-chip 221 and the second sub-chip 222 are stacked, and the first sub-chip 221 and the second sub-chip 222 are connected to the substrate 100 through a bonding wire 223.
In any of the above embodiments of the present invention, the plastic package layer provided by the present invention includes at least one of silicon dioxide and epoxy resin. Further, the utility model provides a plastic envelope layer still includes some microelement, reaches the purpose that improves the sealed effect of plastic envelope layer, to this microelement type the utility model discloses do not specifically restrict.
Based on same utility model design, the embodiment of the utility model provides an electronic equipment is still provided, electronic equipment includes the system level packaging structure that an above-mentioned arbitrary embodiment provided.
The embodiment of the utility model provides a system level encapsulation method and structure and electronic equipment, include: providing a substrate base plate; mounting a plurality of first passive devices and at least one chip on one side of the substrate, wherein the first passive devices comprise external terminals on one side deviating from the substrate; forming a molding layer covering the first passive device and the at least one chip; forming a hollow-out at a position of the plastic packaging layer corresponding to at least one first passive device; and stacking a second passive device at the hollow-out part, wherein the second passive device is connected with the first passive device through the external terminal.
According to the above, the embodiment of the utility model provides a technical scheme piles up the realization encapsulation mutually through with first passive device and second passive device, avoids first passive device and second passive device to expand the dress and appear the great problem of area occupied on the substrate base plate, and then effectively solves the great problem of system level packaging structure area occupied that prior art exists, has optimized system level packaging structure's size.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A system in a package structure, comprising:
a substrate base plate;
a plurality of first passive devices and at least one chip are attached to one side of the substrate base plate, wherein the first passive devices comprise external terminals deviating from one side of the substrate base plate;
the plastic packaging layer is positioned on one side, away from the substrate, of the chip, covers the at least one chip, and is hollowed out at a position, corresponding to the at least one first passive device, of the plastic packaging layer;
and a second passive device is stacked at the hollow part and connected with the first passive device through the external terminal.
2. The system-in-package structure according to claim 1, wherein the chip comprises a first sub-chip to an Nth sub-chip, N being an integer equal to or greater than 2;
the first sub-chip to the Nth sub-chip are sequentially stacked and attached to one side of the substrate base plate.
3. The system-in-package structure according to claim 1, wherein the molding compound layer comprises at least one of silicon dioxide and epoxy.
4. The system-in-package structure according to claim 1, wherein a solder metal layer is further disposed on a side of the external terminal facing away from the substrate.
5. The system-in-package structure according to claim 4, wherein the solder metal layer comprises a tin metal layer.
6. The system-in-package structure of claim 1, wherein the external terminals are copper pillars.
7. The system-in-package structure according to claim 1, wherein the plurality of first passive devices are disposed around the at least one chip.
8. The system-in-package structure of claim 1, wherein the substrate base plate is a circuit board.
9. An electronic device, characterized in that the electronic device comprises a system-in-package structure according to any of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023026674.9U CN214068715U (en) | 2020-12-15 | 2020-12-15 | System-in-package structure and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023026674.9U CN214068715U (en) | 2020-12-15 | 2020-12-15 | System-in-package structure and electronic equipment |
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| Publication Number | Publication Date |
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| CN214068715U true CN214068715U (en) | 2021-08-27 |
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| CN202023026674.9U Active CN214068715U (en) | 2020-12-15 | 2020-12-15 | System-in-package structure and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112509932A (en) * | 2020-12-15 | 2021-03-16 | 上海艾为电子技术股份有限公司 | System-level packaging method and electronic equipment |
| CN115050706A (en) * | 2022-07-25 | 2022-09-13 | 维沃移动通信有限公司 | Chip packaging structure, electronic equipment and packaging method of chip packaging structure |
-
2020
- 2020-12-15 CN CN202023026674.9U patent/CN214068715U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112509932A (en) * | 2020-12-15 | 2021-03-16 | 上海艾为电子技术股份有限公司 | System-level packaging method and electronic equipment |
| CN115050706A (en) * | 2022-07-25 | 2022-09-13 | 维沃移动通信有限公司 | Chip packaging structure, electronic equipment and packaging method of chip packaging structure |
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