CN213783270U

CN213783270U - RF switch circuit, RF front-end architecture and antenna device

Info

Publication number: CN213783270U
Application number: CN202023348994.6U
Authority: CN
Inventors: 蓝焕青; 李海著; 奉靖皓; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Ruishi Chuangxin Chongqing Technology Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-07-23
Anticipated expiration: 2030-12-31

Abstract

In order to overcome the problem that the radio frequency switch circuit in the prior art is easily damaged due to uneven voltage borne by the transistors, the utility model provides a radio frequency switch circuit, a radio frequency front-end structure and an antenna device. The utility model provides a radio frequency switch circuit, which divides the stacked N transistors into a first switch network and a second switch network, and sets gate resistors connected in parallel in the first switch network, and connects the gate resistors in the second switch network. There are two resistance distribution methods of gate-to-gate resistance between each transistor in the network and its predecessor transistor; it avoids the first n transistors in the transistor stack that are close to the input end from being overwhelmed due to the excessive voltage borne. breakdown phenomenon. It ensures that the voltage division borne by each transistor in the next N-n transistors is uniform, and the voltage division borne by each transistor is not too large, and also prevents the transistor from being struck due to the excessive voltage borne by the transistor. wear phenomenon occurs.

Description

Radio frequency switch circuit, radio frequency front end framework and antenna device

Technical Field

The utility model relates to a radio frequency front end architecture field especially indicates the radio frequency switch circuit on the radio frequency front end architecture.

Background

As shown in fig. 1, in communication terminal 1000, wireless communication is realized by built-in antenna device 100. As shown in fig. 2, the conventional antenna apparatus 100 generally includes a baseband module 4, an rf transceiver module 2, an rf front-end architecture 1, and an antenna link module 3; the baseband module 4 is used for performing digital baseband signal processing and performing encoding and decoding of digital baseband signals; the radio frequency transceiver module 2 is configured to perform conversion between a digital baseband signal and an analog radio frequency signal, process the digital baseband signal sent by the baseband module 4 into a radio frequency analog signal and send the radio frequency analog signal to the radio frequency front end architecture 1, or receive the radio frequency analog signal transmitted by the radio frequency front end architecture 1, convert the radio frequency analog signal into a digital baseband signal and send the digital baseband signal to the baseband module 4; the radio frequency front end architecture 4 selects to send a radio frequency analog signal to the antenna link module 3 or receive a radio frequency analog signal from the antenna link module 3, so as to realize the processing of amplifying, filtering and the like of the radio frequency analog signal. The antenna link module 3 includes an external antenna to receive or transmit the radio frequency analog signal.

With the development of mobile communication technology, a situation that multiple communication standards coexist appears, and therefore, the radio frequency front end architecture 1 integrates radio frequency power amplifiers of multiple modes and frequency bands, selects a required power amplifier through a radio frequency switch circuit, and establishes a signal receiving and transmitting channel to realize switching among different communication networks. Currently, most of the existing radio frequency front end architectures 1 include a plurality of radio frequency switch circuits, and each radio frequency switch circuit is formed by connecting a plurality of switch devices in series. Because the voltages born by each switching device (transistor) in the radio frequency switching circuit are inconsistent, the voltage division born by each transistor is uneven, and the radio frequency switching circuit is easy to damage due to the uneven voltage born by each switching device (transistor) in the radio frequency switching circuit.

SUMMERY OF THE UTILITY MODEL

For overcoming the radio frequency switch circuit among the prior art and undertake the problem that the uneven easy radio frequency switch circuit that leads to of voltage damages because of the transistor, the utility model provides a radio frequency switch circuit, radio frequency front end framework and antenna device.

The utility model discloses a radio frequency switch circuit on the one hand, including input end, output end and transistor stack; the transistor stack comprises N transistors connected in series between the input and output terminals in sequence;

the first transistor to the nth transistor from the input terminal constitute a first switching network; the N +1 th transistor to the Nth transistor form a second switch network;

the first switch network further comprises n grid resistors; one end of each grid resistor is connected to the grid of each transistor in the first switch network, and the other ends of the grid resistors are connected with each other to form a common connection node;

and an inter-gate resistor is connected in series between the gates of two adjacent transistors in the second switch network.

Further, the gate of any one of the transistors is connected to a gate power supply.

Further, the resistance values of the gate resistors are the same, and the resistance values of the inter-gate resistors are the same.

Further, the resistance value of the gate resistor is larger than that of the inter-gate resistor.

Further, the inter-gate resistor is connected in series between the (n + 1) th transistor in the first switch network and the nth transistor in the first switch network.

Further, N is equal to or greater than 5.

Further, the number of transistors in the second switching network is greater than the number of transistors in the first switching network.

Further, the area of each transistor in the first switch network is larger than the area of each transistor in the second switch network.

The utility model discloses a radio frequency front end framework is disclosed in the second aspect, radio frequency front end framework is foretell radio frequency switch circuit.

A third aspect of the present invention discloses an antenna apparatus, including a baseband module, a radio frequency transceiver module, a radio frequency front end architecture, and an antenna link module; the radio frequency front end architecture is the radio frequency front end architecture described above.

The utility model discloses an antenna device, improved to the radio frequency switch circuit in its radio frequency front end framework, divide into first switch network and second switch network with each N transistor that piles up, and set up the grid resistance of parallel connection in the first switch network, concatenate two kinds of resistance distribution modes of the inter-grid resistance between the grid of each transistor in the second switch network; so that the transistor in the first switching network still generates a partial gate current I due to the gate resistance_gDue to gate current I_gThereby reducing the source-drain current I through each transistor_DSI.e. the source-drain voltage V of each transistor in the first switching network is reduced_DSThereby realizing that the source-drain voltage V born by the first n transistors close to the input end in the transistor stack is reduced_DSAnd the phenomenon that the first n transistors close to the input end in the transistor stack are broken down due to the overlarge voltage born by the transistors is avoided. The series-connected inter-gate resistors are arranged in the second switch network, so that the phenomenon that gate current Ig of each transistor in the second switch network leaks can be inhibited, namely, the source-drain voltage V of each transistor in the second switch network is ensured_DSThe same is true. Therefore, on one hand, the transistor close to the input end can be prevented from bearing overlarge source-drain voltage, the phenomenon that the first N transistors close to the input end in the transistor stack are broken down due to overlarge borne voltage is avoided, meanwhile, the fact that the partial pressure borne by each transistor in the last N-N transistors is even is also guaranteed, the partial pressure borne by each transistor is not overlarge, and the phenomenon that the transistors are broken down due to the overlarge borne voltage is also avoided.

Drawings

Fig. 1 is a schematic view of a communication terminal disclosed in the prior art;

fig. 2 is a schematic view of an antenna arrangement disclosed in the prior art;

FIG. 3 is a schematic diagram of another radio frequency switch circuit of applicants' improvement;

FIG. 4 is a schematic diagram illustrating voltage distributions experienced by transistors in the RF switch circuit of FIG. 5;

fig. 5 is a schematic diagram of a radio frequency switch circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of voltage distributions sustained by transistors in the rf switch circuit corresponding to fig. 5.

1000, a communication terminal; 2000. a base station; 100. an antenna device;

1. a radio frequency front end architecture; 2. a radio frequency transceiver module; 3. an antenna link module; 4. a baseband module;

11. a first switching network; 12. a second switching network;

m1, a first transistor; m2, a second transistor; mn, n-th transistor; mn +1, n +1 transistor; MN, Nth transistor;

r1, a first resistor; r2, a second resistor; rn, nth resistor; rn +1 and n +1 resistance; RN and Nth resistors; p, common connection nodes; in, input terminal (radio frequency signal input terminal); out, output (radio frequency signal output); vg, gate power supply.

Detailed Description

In order to make the technical problem, technical solution and advantageous effects solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to further explain the present invention in detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and to simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

As shown in fig. 3, as an improvement to the prior art, the applicant also stacked N transistors (M1-MN) in series, and connected a resistor in series between the gates of two adjacent transistors, that is, the gates of two adjacent transistors are connected through a resistor. In this way, as shown in fig. 4, the generation of the gate current I per transistor can be suppressed_gTo ensure that the voltage carried by each transistor is substantially the same, but it can be seen that the voltage carried by each transistor remains at a high voltage of 4.9 volts, which is also susceptible to breakdown due to excessive voltage carried by the transistor.

Example 1

The present embodiment specifically explains the communication terminal 1000, the antenna device 100, the radio frequency front end architecture 1 and the radio frequency switch circuit disclosed in the present invention.

Also, as shown in fig. 1, the communication terminal 1000 provided in this example is substantially the same as the communication terminal framework in the related art. Which also enables wireless communication with the antenna device in the base station via the built-in antenna device 100. The antenna device 100 in the communication terminal 1000 implements, through its internal modules, external transmission of radio frequency signals in a relevant frequency band and reception of radio frequency signals in a relevant frequency band sent by an antenna device on a base station. Of course, the communication terminal 1000 may include not only the antenna apparatus 100, but also other modules, such as a processor, a user interface, a memory, and the like. The communication terminal is, for example, a Personal Digital Assistant (PDA), a cellular phone, a card in a notebook computer, a wireless tablet computer, or the like. In this example, antenna device 100 will be described below only with respect to the angle of view of communication terminal 1000.

As shown in fig. 2, the antenna apparatus 100 in this example also includes a baseband module 4, an rf transceiver module 2, an rf front-end architecture and an antenna link module 3; the key point in this example is to improve the rf switch circuit in the rf front-end architecture 1, which will be described in detail below.

As shown In fig. 5, the rf switch circuit provided In this embodiment includes an rf signal input terminal (input terminal In for short), an rf signal output terminal (output terminal Out for short) and a transistor stack; the transistor stack comprises N transistors connected In series between the input terminal In and the output terminal Out In sequence; in this example, the transistors are named as a first transistor M1, second transistors M2, … …, an nth transistor Mn, an N +1 th transistors Mn +1, … …, an nth transistor Mn, and the like In this order from an input terminal In to an output terminal Out. The first transistor M1, the second transistors M2, … …, the nth transistor Mn, the (N + 1) th transistors Mn +1, … …, and the nth transistor Mn are connected in series. Here, the series connection of the transistors described herein means that the sources S and the drains D of the adjacent transistors are connected. For example, In this example, the drain D of the first transistor M1 is used as the input terminal In, the drain D of the second transistor M2 is connected to the source S of the first transistor, the drain D of the third transistor M3 is connected to the sources S and … … of the second transistor M2, and so on, the drain D of the Nth transistor MN is connected to the source S of the Nth-1 transistor MN-1; wherein, the source S of the Nth transistor MN is used as the output terminal Out. Of course, according to the different types of transistors, on the contrary, the source of the first transistor M1 is used as the input terminal In, the source S of the second transistor M2 is connected to the drain D of the first transistor M1, the source S of the third transistor M3 is connected to the drains D, … … of the second transistor M2, and so on, the source S of the nth transistor MN is connected to the drain D of the N-1 th transistor MN-1; here, the drain D of the nth transistor MN may be used as the output terminal Out.

In this example, the first transistor M1 through the nth transistor Mn from the input terminal In constitute the first switching network 11; the second switching network 12 is formed from the (N + 1) th transistor Mn +1 to the nth transistor Mn;

the first switch network 11 further includes n gate resistors; one end of each gate resistor is connected to the gate G of each transistor in the first switch network 11, and the other ends are connected to each other to form a common node P; the gate resistances may be considered as being connected in parallel. That is, the first switch network 11 includes a first transistor M1, a second transistor M2, a … …, an nth transistor Mn, and n gate resistors connected in parallel.

For convenience of description, the n gate resistors are named as a first resistor R1, a second resistor R2, and a … … nth resistor Rn;

a gate resistor is connected in series between the gates G of the transistors in the second switch network 12. Preferably, a gate-to-gate resistor is also connected in series between the n +1 th transistor and the n-th transistor. At this time, N-N inter-gate resistors are included (if the inter-gate resistors are not connected in series between the (N + 1) th transistor and the nth transistor, the number of the inter-gate resistors is N-N-1); for convenience of description, the N-N inter-gate resistors are named as N +1 th resistor Rn +1, … …, nth resistor Rn, etc. In other words, an inter-gate resistor is connected in series between each transistor in the second switch network 12 and the gate G of the previous transistor adjacent to the transistor; as explained further herein, the gate G of the (N + 1) th transistor Mn +1 is connected to the common node P of the first switch network 11 through an inter-gate resistor, and an inter-gate resistor is connected between the adjacent gates G of the (N + 1) th transistor Mn +1 to the nth transistor Mn.

In a specific embodiment, the gate G of any one of the transistors in the transistor stack may be connected to a gate power supply Vg. The transistor stack includes N transistors. N does not generally have a certain range, and may be determined according to actual conditions, for example, N is greater than or equal to 5. The first N transistors typically form the first switching network 11 and the remaining N-N transistors form the second switching network 12. For example: n is 6, the first 2 transistors form the first switching network 11, and the remaining N-N4 transistors form the second switching network 12, and the number of transistors in the second switching network 12 is generally greater than the number of transistors in the first switching network 11. I.e. said N-N is greater than N.

For the inter-gate resistor and the gate resistor, it is generally recommended that the resistance range is several K to 100K, and preferably, the resistance values of the gate resistors are the same, and the resistance values of the inter-gate resistors are the same.

Further, preferably, the resistance of the gate resistor is larger than the resistance of the inter-gate resistor. For example, the resistance value of the gate resistor ranges from 30K Ω to 50K Ω, for example, the resistance value of the gate resistor is 40K or 50K Ω; the resistance range of the inter-gate resistor is 10K omega-20K omega, for example, the resistance of the gate resistor is 10K omega or 20K omega.

As shown in fig. 6, in this example, the value of the number n of transistors in the first switch network 11 determines the source-drain voltage that the nth transistor can withstand. The skilled person can select the appropriate number by wanting to control the result. For example, in this example, the source-drain voltage is controlled to be 4.5 v, so that the source-drain voltage borne by each transistor in the second switch network 12 is controlled to be 4.5 v, and the source-drain voltage is relatively low, so that the transistor is not easily damaged.

Preferably, the area of each transistor in the first switch network 11 is larger than the area of each transistor in the second switch network 12. By increasing the area of each transistor in the first switch network 11, the larger the area of the transistor is, the larger the parasitic capacitance generated by the transistor is, and the smaller the source-drain voltage across the transistor is. In this way the source-drain voltage across each transistor in the first switching network 11 is reduced.

Preferably, the number of transistors in the second switching network 12 is greater than the number of transistors in the first switching network 11.

In this example, assume that N is 5, N2; in this embodiment, the gates G of the first 2 transistors in the transistor stack are connected to the inter-gate resistors, for example, the gate G of the first transistor M1 is connected to the first resistor R1, and the gate G of the second transistor M2 is connected to the second resistor R2, at this time, the first transistor M1 and the second transistor M2 still generate the partial gate current I_gDue to gate current I_gThereby reducing the source-drain current I after passing through the first transistor M1 and the second transistor M2_DSTo further reduce the source-drain voltages V1 and V2 of the first and second transistors M1 and M2_DSI.e. the voltage V assumed by the first 2 transistors of the transistor stack close to the input terminal In is reduced_DSThe first 2 transistors In the transistor stack close to the input terminal In are prevented from being broken down due to the excessive voltage borne.

By connecting the gates of the last 3 transistors with the gate G of the previous transistor through an inter-gate resistor, for example, the gate G of the second transistor M2 connected with the second resistor R2 is connected with the gate G of the third transistor M3 through the third resistor R3, the gate of the third transistor M3 is connected with the gate G of the fourth transistor M4 through the fourth resistor R4, and the gate of the fourth transistor M4 is connected with the gate G of the fifth transistor M5 through the fifth resistor R5. The gate current I generated by the third transistor M3 can be completely suppressed due to the inter-gate resistance (i.e., the fourth resistor R3) in the second switch network 12_gThe fourth resistor R4 can completely suppress the gate current I of the fourth transistor M4_gThe fifth resistor R5 can completely suppress the gate current I of the fifth transistor M5_gThe source-drain voltage V of the third transistor M3 is ensured_DSSource-drain voltage V of fourth transistor M4_DSAnd the source-drain voltage V of the fifth transistor M5_DSThe same, i.e. ensuring the source-drain voltage V of each of the last 3 transistors_DSThe same, thus ensuring that the voltage division undertaken by each of the last 3 transistors is the same.

In summary, the communication terminal disclosed in the present application improves the rf switch circuit in the rf front end architecture of the antenna device, and stacks N rf switchesThe transistors are divided into a first switch network 11 and a second switch network 12, grid resistors connected in parallel are arranged in the first switch network 11, and two resistor distribution modes of the grid resistors are connected in series between the grids between each transistor and the previous transistor in the second switch network; so that its transistors in the first switching network 11 still generate a partial gate current I due to the setting of the gate resistance_gDue to gate current I_gThereby reducing the source-drain current I through each transistor_DSI.e. the source-drain voltage V of each transistor in the first switching network 11 is reduced_DSI.e. the source-drain voltage V borne by the first n transistors in the transistor stack close to the input is reduced_DSAnd the phenomenon that the first n transistors close to the input end in the transistor stack are broken down due to the overlarge voltage born by the transistors is avoided. Series-connected inter-gate resistors are provided in the second switching network 12, which make it possible to suppress the occurrence of a gate current I in the transistors of the second switching network 12_gI.e. the source-drain voltage V of each transistor in the second switching network 12 is guaranteed_DSThe same is true. Therefore, on one hand, the transistor close to the input end In can be prevented from bearing too large source-drain voltage V_DSThe phenomenon that the first N transistors close to the input end in the transistor stack are broken down due to overlarge borne voltage is avoided, meanwhile, the fact that the partial voltage borne by each transistor in the last N-N transistors is even is guaranteed, the partial voltage borne by each transistor is not overlarge, and the phenomenon that the transistors are broken down due to the overlarge borne voltage is also avoided.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A radio frequency switch circuit, comprising an input terminal, an output terminal and a transistor stack; the transistor stack comprises N transistors sequentially connected in series between the input terminal and the output terminal;

It is characterized in that the first transistor from the input terminal to the nth transistor constitutes a first switch network; the n+1th transistor to the Nth transistor constitutes a second switch network;

Wherein, the first switch network further includes n gate resistors; one end of each gate resistor is connected to the gate of each transistor in the first switch network, and the other end is connected to each other to form a common node ;

An inter-gate resistance is connected in series between the gates of two adjacent transistors in the second switching network.

2 . The radio frequency switch circuit according to claim 1 , wherein the gate of any one of the transistors is connected to a gate power supply. 3 .

3 . The radio frequency switch circuit according to claim 1 , wherein the resistance values of the gate resistors are the same, and the resistance values of the inter-gate resistors are the same. 4 .

4 . The radio frequency switch circuit according to claim 1 , wherein the resistance value of the gate resistor is greater than the resistance value of the inter-gate resistor. 5 .

5 . The radio frequency switch circuit according to claim 1 , wherein the gate-to-gate resistance is connected in series between the n+1th transistor in the first switch network and the nth transistor in the first switch network. 6 . .

6 . The radio frequency switch circuit according to claim 1 , wherein N is greater than or equal to 5. 7 .

7 . The radio frequency switch circuit of claim 1 , wherein the number of transistors in the second switch network is greater than the number of transistors in the first switch network. 8 .

8 . The radio frequency switch circuit according to claim 1 , wherein the area of each transistor in the first switch network is larger than that of each transistor in the second switch network. 9 .

9 . A radio frequency front-end architecture, wherein the radio frequency front-end architecture comprises the radio frequency switch circuit according to any one of claims 1 to 7 .

10 . An antenna device, comprising a baseband module, a radio frequency transceiver module, a radio frequency front-end architecture and an antenna link module; wherein the radio frequency front-end architecture is the radio frequency front-end architecture of claim 9 .