CN217985025U - Radio frequency switch circuit - Google Patents
Radio frequency switch circuit Download PDFInfo
- Publication number
- CN217985025U CN217985025U CN202221405114.0U CN202221405114U CN217985025U CN 217985025 U CN217985025 U CN 217985025U CN 202221405114 U CN202221405114 U CN 202221405114U CN 217985025 U CN217985025 U CN 217985025U
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrode
- bias
- control
- radio frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Images
Landscapes
- Electronic Switches (AREA)
Abstract
A radio frequency switching circuit, comprising: a plurality of stages of transistors cascaded between the rf input port and the rf output port, the transistors including at least a first control electrode, a first electrode, and a second electrode; a bias circuit for the first control electrode, for providing a bias voltage to the first control electrode of each transistor; the bias circuit for the first control electrode includes: a first gate bias resistor connected between the first gate nodes of each adjacent transistor, and a configuration resistor connected between the first gate and the first gate node of each transistor; with one first gate node for each transistor. The switching speed between the on and off of the radio frequency switch circuit can be increased, and the switching time between the on and off of the radio frequency switch circuit is shortened.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a radio frequency switch circuit.
Background
With the continuous development of wireless mobile communication technology, radio frequency switches are also applied more and more, and the performance of the radio frequency switches also directly affects the performance of devices. The radio frequency switch is a switch for signals in the communication field, is provided with a signal input port and a signal output port, and is used for switching on or off the signal input port and the signal output port so as to switch a signal path. Isolation, insertion loss, switching time, power processing capability, harmonic performance and the like are important performance indexes of the radio frequency switch, and the quality of the radio frequency switch can be evaluated through the indexes.
Taking the switching time as an example, the switching time of the radio frequency switch (from on to off, or from off to on) is an important performance index, and when the switching time is too slow, the user experience is directly affected; therefore, the performance index of the switching time of the rf switch needs to be improved and enhanced.
Disclosure of Invention
In order to shorten the switching time of the rf switch, the present application provides an rf switch circuit, which is described in detail below.
According to a first aspect, an embodiment provides a radio frequency switch circuit, including a radio frequency input port, a radio frequency output port, an N-stage transistor cascaded between the radio frequency input port and the radio frequency output port, a gate bias circuit, a body bias circuit, a source-drain bias circuit, and a control terminal group;
the radio frequency input port is used for inputting radio frequency signals;
the radio frequency output port is used for outputting radio frequency signals;
the transistor comprises a grid electrode, a body electrode, a first electrode and a second electrode, wherein if the first electrode is a source electrode, the second electrode is a drain electrode, and if the first electrode is a drain electrode, the second electrode is a source electrode; the transistors are cascaded with their neighboring transistors by their first or second poles; n is an integer greater than or equal to 2;
the grid biasing circuit is used for providing a biasing voltage for the grid of each transistor; the gate bias circuit includes: the circuit comprises N grid nodes, N-1 grid bias resistors and N configuration resistors, wherein each grid node corresponds to a transistor; the grid electrode of each transistor is connected with the grid electrode node corresponding to the transistor through one configuration resistor; the grid bias resistor is connected between grid nodes corresponding to adjacent transistors in each group of transistors;
the body electrode bias circuit is used for providing bias voltage for the body electrode of each transistor;
the source-drain electrode bias circuit is used for providing bias voltage for the source electrode and the drain electrode of each transistor;
the control end group is used for receiving control signals; the control signal is used for controlling bias voltages provided by the body electrode bias circuit, the grid electrode bias circuit and the source drain electrode bias circuit to the body electrode, the grid electrode, the source electrode and the drain electrode of each transistor so as to control the on and off of the transistors.
In one embodiment, the body bias circuit comprises: each body electrode node corresponds to one transistor, the body electrode bias resistor is connected between the body electrode nodes corresponding to the adjacent transistors in each group of transistors, and the body electrode of each transistor is directly connected with the body electrode node corresponding to the transistor.
In one embodiment, the body bias circuit comprises: n bias transistors, one for each transistor; the grid electrode, the body electrode and the first electrode of the bias transistor are connected to the grid electrode node of the corresponding transistor, and the second electrode of the bias transistor is connected to the body electrode of the transistor of the corresponding stage; or the grid electrode, the body electrode and the first electrode of the bias transistor are connected to the body electrode of the corresponding transistor, and the second electrode of the bias transistor is connected to the grid electrode node of the corresponding transistor.
In one embodiment, the source-drain bias circuit includes: and the source-drain bias resistors are connected between the first electrode and the second electrode of each transistor.
In one embodiment, the set of control terminals includes a first control terminal, and the gate bias circuit further includes a gate common resistor; one end of the grid common resistor is connected with a grid node corresponding to the Nth-stage transistor, and the other end of the grid common resistor is connected with the first control end.
In one embodiment, the control terminal group comprises a second control terminal, and the body bias circuit further comprises a gate common resistor; one end of the body electrode common resistor is connected with a body electrode node corresponding to the Nth-stage transistor, and the other end of the body electrode common resistor is connected with the second control end.
According to a second aspect, an embodiment provides a radio frequency switching circuit comprising:
the radio frequency input port is used for inputting radio frequency signals;
a radio frequency output port for outputting a radio frequency signal;
a plurality of stages of transistors cascaded between the rf input port and the rf output port, the transistors including at least a first control electrode, a first electrode, and a second electrode;
a bias circuit for the first control electrode, for providing a bias voltage to the first control electrode of each transistor; the bias circuit for the first control electrode includes: a first gate bias resistor connected between the first gate nodes of adjacent transistors, one first gate node for each transistor; and a configuration resistor connected between the first control electrode of each transistor and the first control electrode node;
a bias circuit for the first and second poles for providing a bias voltage to the first and second poles of each transistor;
the control end group is used for receiving control signals; the control signal is used for controlling the bias voltage provided by each bias circuit to each transistor so as to control the on and off of the transistors.
In one embodiment, the transistor further comprises a second gate; the radio frequency switch circuit further comprises a bias circuit for the second control electrode for providing a bias voltage to the second control electrode of each transistor.
In one embodiment, the bias circuit for the second gate comprises: and a second gate bias resistor connected between the second gates of adjacent transistors.
In one embodiment, the bias circuit for the second gate comprises: a bias transistor provided for each transistor; the transistor of each stage corresponds to a bias transistor;
the first pole, the first control pole and the second control pole of the bias transistor are connected to the first control pole node of the transistor of the corresponding stage, and the second pole of the bias transistor is connected to the second control pole of the transistor of the corresponding stage; or the first electrode, the first control electrode and the second control electrode of the bias transistor are all connected to the second control electrode of the transistor of the corresponding stage, and the second electrode of the bias transistor is connected to the first control electrode node of the transistor of the corresponding stage.
In one embodiment, the bias circuit for the first and second poles comprises: a first diode bias resistor connected between the first and second poles of each transistor.
In one embodiment, the control terminal group includes a first control terminal;
the bias circuit for the first control electrode further comprises a first control electrode common resistor; one end of the first control electrode common resistor is connected with a first control electrode node corresponding to the transistor of any stage, and the other end of the first control electrode common resistor is connected with the first control end; the transistor of any stage is the transistor of the last stage.
In one embodiment, the control terminal group includes a second control terminal;
the bias circuit for the second control electrode further comprises a second control electrode common resistor; one end of the second control electrode common resistor is connected with the second control electrode of the transistor at any stage, and the other end of the second control electrode common resistor is connected with the second control end; the transistor of any stage is the transistor of the last stage.
In one embodiment, the multi-level transistor is at least a three-level transistor, at least a four-level transistor, or at least a five-level transistor.
According to the radio frequency switch circuit of the embodiment, the switching speed between the on and off of the radio frequency switch circuit can be increased, and the switching time between the on and off of the radio frequency switch circuit is shortened.
Drawings
FIG. 1 is a schematic diagram of an embodiment of an RF switch circuit;
FIG. 2 is a schematic diagram of an embodiment of an RF switch circuit;
FIG. 3 is a schematic diagram of an embodiment of an RF switch circuit;
FIG. 4 is a schematic diagram of an embodiment of an RF switch circuit;
FIG. 5 is a schematic diagram of an embodiment of an RF switch circuit;
fig. 6 is a schematic structural diagram of an rf switch circuit according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The ordinal numbers used herein for the components, such as "first," "second," etc., are used merely to distinguish between the objects described, and do not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.
As shown in fig. 1 and fig. 2, the two structures of the rf switch are realized by a transistor M 1 To transistor M N The N transistors are cascaded, and are biased to be in a conducting or disconnecting state through related grid electrode, body electrode and source drain electrode biasing circuits under the control of direct current bias voltage 1 and direct current bias voltage 2, so that the radio frequency port 1 and the radio frequency port 2 are connected or disconnected.
The switching time or switching time of the radio frequency switch is an important performance index; for example, in Time Division Duplex (TDD) communication mode, too slow a switching time directly affects communication quality and user experience. Taking the structure shown in fig. 2 as an example, by changing the voltage values of the dc bias voltage 1 and the dc bias voltage 2 in fig. 2 (the dc bias voltage 1 and the dc bias 2 are control signals of the rf switch shown in fig. 2), the voltages of the gate and the body of each transistor can be changed, so as to realize the on state of the rf switch from off to on and the on state from on to off. Transistor M in RF switch design to reduce insertion loss 1 To transistor M N Is large and thus the gate parasitic capacitance is also large, plus the gate bias resistance R G The effect of the radio frequency switch is that the charging and discharging time of the grid electrode of the transistor is longer, and the charging and discharging time of the grid electrode of the transistor determines the switching time of the radio frequency switch; the parasitic capacitance of the body of the transistor is small compared with that of the grid electrodeThe poles switch faster than the gates, so body pole switching does not typically affect the total switching time. The method for improving the switching time of the radio frequency switch may be: (1) Reducing transistor M in fig. 2 1 To transistor M N Thereby reducing gate parasitic capacitance, but the reduced size of the transistor can affect the insertion loss of the rf switch; (2) Reducing gate bias resistance R G But this will have an impact on the harmonic performance of the radio frequency switch.
Based on the above research and invention, the applicant proposes a radio frequency switch circuit, which is described in detail below.
Referring to fig. 3 and 4, the rf switch circuit of some embodiments includes an rf input port 1, an rf output port 2, and a multi-stage transistor M 1 To M N (ii) a In some embodiments, N is an integer greater than or equal to 1; in some embodiments, N is an integer greater than or equal to 2; in some embodiments, N is an integer greater than or equal to 3; in some embodiments, N is an integer greater than or equal to 4; in some embodiments, N is an integer greater than or equal to 5; in some embodiments, N is an integer greater than or equal to 6; the specific value of N can be changed and set according to the requirements of the rf switch circuit in practical applications.
In some embodiments, the transistor includes at least a first pole, a second pole, and a first control pole. It should be noted that the transistor in the present application may be a transistor with any structure, such as a Bipolar Junction Transistor (BJT) or a Field Effect Transistor (FET). When the transistor is a bipolar transistor, the first control electrode of the transistor refers to a grid electrode of the bipolar transistor, the first electrode can be a collector electrode or an emitter electrode of the bipolar transistor, the corresponding second electrode can be an emitter electrode or a collector electrode of the bipolar transistor, and in the practical application process, the emitter electrode and the collector electrode can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, the first control electrode refers to a gate electrode of the field effect transistor, the first electrode may be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode may be a source electrode or a drain electrode of the field effect transistor. The radio frequency switching circuit of some embodiments further includes a bias circuit 10 for the first control pole, a bias circuit 30 for the first pole and the second pole, and a set of control terminals 50.
In some embodiments, the transistor includes a first pole, a second pole, a first control pole, and a second control pole; in some embodiments, the first and second control poles may be opposing; for example, in some embodiments, when the transistor is a field effect transistor, the first control electrode can be a gate electrode, and the second control electrode can be a body electrode; in some embodiments, when the first control electrode is a body electrode, the second control electrode is a gate electrode. The radio frequency switch circuit in some embodiments may include a bias circuit 20 for the second control pole in addition to the bias circuit 10 for the first control pole, the bias circuit 30 for the first and second poles, and the set of control terminals 50.
The circuit configurations are explained in more detail below.
The radio frequency input port 1 is used for inputting radio frequency signals, and the radio frequency output port 2 is used for outputting radio frequency signals; while the multi-stage transistor M 1 To M N Then cascaded between the rf input port 1 and the rf output port 2, specifically, transistors cascaded with their neighboring transistors through their first or second poles, it can be understood that: for any one transistor, when the transistor is connected with the first pole or the second pole of the previous stage transistor through the first pole, the transistor is connected with the first pole or the second pole of the next stage transistor through the second pole; similarly, for any one transistor, when it is connected with the first pole or the second pole of the previous stage transistor through the second pole, the transistor is connected with the first pole or the second pole of the next stage transistor through the first pole; when the transistor is a first-stage transistor, the first-stage transistor is a transistor close to the radio frequency input port 1, the input pole of the first-stage transistor is connected with the radio frequency input port 1, the input pole is a first pole or a second pole, when the first pole of the first-stage transistor is used as the input pole to be connected with the radio frequency input port 1, the second pole of the first-stage transistor is connected with the first pole or the second pole of the second-stage transistor, and when the second pole of the first-stage transistor is used as the input pole to be connected with the radio frequency input port 1, the second pole of the first-stage transistor is connected with the first pole or the second pole of the second-stage transistorOne pole of the transistor is connected with the first pole or the second pole of the transistor of the second stage; similarly, when the transistor is the transistor of the last stage, the transistor of the last stage is the transistor close to the rf output port 2, and the output pole thereof is connected to the rf output port 2, and the output pole thereof is the first pole or the second pole thereof, when the first pole of the transistor of the last stage (for example, the nth stage) is connected as the output pole to the rf output port 2, the second pole thereof is connected to the first pole or the second pole of the transistor of the last but one stage (for example, the N-1 st stage), and when the second pole of the transistor of the last stage (for example, the nth stage) is connected as the output pole to the rf output port 2, the first pole thereof is connected to the first pole or the second pole of the transistor of the last but one stage (for example, the N-1 st stage).
Multi-stage transistor M 1 To M N Ending from the radio frequency input port 1 to the radio frequency output port 2, sequentially forming a first-stage transistor M 1 Second stage transistor M 2 823060, 823080, N-1 st transistor M N-1 Nth transistor M N 。
The bias circuit 10 for the first gate is used for each transistor (referred to as multi-stage transistor M) 1 To M N ) Provides a bias voltage.
In some embodiments, bias circuit 10 includes a plurality of transistors M connected in adjacent pairs 1 To M N ) A first gate bias resistance between the first gate nodes; with one first gate node for each transistor.
In some embodiments, a transistor (referred to as a multi-level transistor M) 1 To M N ) The first control electrode of the transistor is connected with a first control electrode node corresponding to the transistor through a configuration resistor; that is, the bias circuit 10 includes N-1 first gate bias resistors and N configuration resistors; a first control electrode bias resistor is connected between the first control electrode nodes of the adjacent transistors, and a configuration resistor is connected between the first control electrode of each transistor and the first control electrode node.
By introducing the configuration resistor, the voltage rise time of the corresponding transistor can be adjusted, so that the voltage of the first control electrode of each transistor can be simultaneously raised in the switching process from off to on (namely, conducting) of the radio frequency switch circuit, and when the voltage of the first control electrode exceeds the corresponding threshold voltage, the corresponding transistor is conducted, so that the radio frequency switch circuit is conducted, and each transistor does not need to be sequentially conducted like the radio frequency switch circuit shown in fig. 2 and the like; therefore, the speed of switching the radio frequency switch circuit from off to on and then conducting is increased by introducing the configuration resistor, and the time of switching the radio frequency switch circuit from off to on and then conducting is shortened.
The bias circuit 20 for the second gate is used for each transistor (referred to as multi-stage transistor M) 1 To M N ) The second gate of (a) provides a bias voltage.
In some embodiments, the bias circuit 20 includes a plurality of transistors M connected in adjacent pairs (referred to as multi-level transistors M) 1 To M N ) A second gate bias resistance between the second gate nodes of the transistors of (1); wherein each transistor corresponds to a second gate node; the second gates of the transistors are directly connected to the corresponding second gate nodes of the transistors, in other words, the bias circuit 20 comprises a second gate bias resistor connected between the second gates of each adjacent transistor.
In some embodiments, bias circuit 20 is included for each transistor (referred to as multi-level transistor M) 1 To M N ) A bias transistor each configured; with the transistors of each stage corresponding to a bias transistor. In some embodiments, the first pole, the first gate, and the second gate of the bias transistor are all connected to the first gate node of the transistor of the corresponding stage, and the second pole of the bias transistor is connected to the second gate of the transistor of the corresponding stage. In some embodiments, the first, first and second gates of the bias transistor are all connected to the second gate of the transistor of the corresponding stage, and the second gate of the bias transistor is connected to the first gate node of the transistor of the corresponding stage.
By introducing the bias transistors, the transistors (referred to as multi-stage transistors M) of the corresponding stages of the bias transistors can be reduced when the radio frequency switch circuit is switched from on to off 1 To M N ) The magnitude of the voltage rise due to leakage current.
The biasing circuit 30 for the first and second poles is used for each transistor (referred to as multi-stage transistor M) 1 To M N ) Provides a bias voltage.
The above are some descriptions of the bias circuits such as the bias circuit 10, the bias circuit 20, and the bias circuit 30.
The control terminal set 50 is used for receiving control signals for controlling the bias circuits (such as the bias circuit 10, the bias circuit 20 and the bias circuit 30) to the transistors (referring to the multi-stage transistor M) 1 To M N ) To control the turn-on and turn-off of the respective transistors.
In some embodiments, the set of control terminals 50 includes a first control terminal; the bias circuit 10 further comprises a first gate common resistance; one end of the first control electrode common resistor is connected with the transistor of any stage (namely, the multi-stage transistor M) 1 To M N Any one of) the first control electrode nodes, and the other end is connected with the first control end. In some embodiments, the transistor of any one of the above stages is the last stage transistor, i.e., the nth stage transistor M N Therefore, one end of the common resistor of the first control electrode is connected with the transistor of the last stage, i.e. the Nth stage transistor M N The corresponding first control electrode node is connected, and the other end of the corresponding first control electrode node is connected with the first control end.
In some embodiments, the set of control terminals 50 includes a second control terminal; the bias circuit 20 further includes a second common resistor having one end connected to the transistor of any stage (i.e., the multi-stage transistor M) 1 To M N Any of the above) corresponding second gate node or second gate node, and the other end is connected to the second control end. In some embodiments, the transistor of any one of the above stages is the last stage transistor, i.e., the nth stage transistor M N Therefore, one end of the second control electrode common resistor is connected with the transistor of the last stage, i.e., the Nth stage transistor M N The corresponding second control electrode node or second control electrode is connected, and the other end is connected with the second control end.
In some embodiments, the set of control terminals 50 includes two control terminals (e.g., a first control terminal and a second control terminal); for example, in the case where the bias circuit 20 is implemented by a second gate bias resistor, the control terminal group 50 may include two control terminals. In some embodiments where the control terminal set 50 includes two control terminals:
the bias circuit 10 for the first control electrode further includes a first control electrode common resistor, one end of which is connected to a transistor of any one stage, for example, a transistor of the last stage, that is, an nth stage transistor M N The corresponding first control electrode node is connected, and the other end of the corresponding first control electrode node is connected with one control end (such as a first control end);
the bias circuit 20 for the second gate further includes a second gate common resistor having one end connected to a transistor of any one stage, for example, a transistor of the last stage, that is, an nth stage transistor M N The corresponding second gate node or second gate is connected to the other control terminal (e.g., second control terminal).
In some embodiments, the set of control terminals 50 includes one control terminal; for example, in the case where the bias circuit 20 is implemented by a bias transistor, the control terminal set 50 may include only one control terminal. In some embodiments where the control terminal group 50 includes only one control terminal: the bias circuit 10 for the first control electrode further includes a first control electrode common resistor, one end of which is connected to the transistor of the last stage, i.e., the nth stage transistor M N The corresponding first control electrode node is connected, and the other end of the first control electrode node is connected with the control end.
Following with a multi-stage transistor M 1 To M N The transistor is an MOS transistor, and the first control electrode is explained as a grid electrode; in such an embodiment, the bias circuit 10 for the first control electrode is essentially a gate bias circuit 10, the gate bias circuit 10 being used for each transistor (referred to as multi-stage transistor M) 1 To M N Transistor(s) provides a bias voltage; the biasing circuits 30 for the first and second poles are essentially source drain biasing circuits 30, the source drain biasing circuits 30 being forFor each transistor (referred to as multi-stage transistor M) 1 To M N Transistor(s) provide a bias voltage. When transistor (refers to multi-stage transistor M) 1 To M N Transistor(s) when the second control electrode is further included, the second control electrode will not be described as the body electrode, and in such an embodiment, the bias circuit 20 for the second control electrode is substantially the body bias circuit 20, and the body bias circuit 20 is used for each transistor (referred to as the multi-stage transistor M) 1 To M N Transistor (iii) provides a bias voltage to the body, and the bias circuits will be described below.
In some embodiments, the gate bias circuit 10 includes: n grid nodes, N-1 grid bias resistors and N configuration resistors, wherein each grid node corresponds to one transistor (namely a multistage transistor M) 1 To M N The transistor in (b), one of the gate bias resistors is connected between the gate nodes corresponding to the respective adjacent transistors, and the gate of each transistor is connected to the gate node corresponding to the transistor via one of the arrangement resistors.
In some embodiments, the body bias circuit 20 includes: n individual body node and N-1 individual body bias resistors, each body node corresponding to a transistor (referred to as multi-stage transistor M) 1 To M N The transistors in each group of transistors) are connected with one body electrode bias resistor between body electrode nodes corresponding to each adjacent transistor in each group of transistors, and the body electrode of each transistor is directly connected with the body electrode node corresponding to the transistor, in other words, one body electrode bias resistor is connected between the body electrodes of each adjacent transistor in each group of transistors; this is an example of implementing the body bias circuit 20 by a body bias resistor.
In some embodiments, the body bias circuit 20 includes: n biasing transistors, each transistor (referred to as a multi-stage transistor M) 1 To M N The transistor) corresponding to one of the bias transistors; in some embodiments, the gate, body and first pole of the bias transistor are all connected to the transistors of the corresponding stage (referred to as multi-stage transistor M) 1 To M N Transistor) with a second pole of the bias transistor connected to the transistor of the corresponding stageA body pole; in some embodiments, the gate, body and first pole of the bias transistor are all connected to the body of the transistor of the corresponding stage, and the second pole of the bias transistor is connected to the gate node of the transistor of the corresponding stage.
In some embodiments, source drain bias circuit 30 includes: n source-drain bias resistors, each transistor (referred to as a multi-stage transistor M) 1 To M N Transistor (ii) has one of the source-drain bias resistors connected between the first and second poles.
In some embodiments, the set of control terminals 50 includes a first control terminal; the gate bias circuit 10 further comprises a gate common resistor R GC (ii) a Grid common resistance R GC And a transistor of an arbitrary stage such as an Nth-stage transistor M N Is connected to the gate node of the gate common resistor R GC The other end of the first control terminal is connected with the first control terminal.
In some embodiments, the set of control terminals 50 includes a second control terminal; the body bias circuit 20 further includes a body common resistor R BC (ii) a Body pole common resistance R BC And a transistor of an arbitrary stage such as the Nth stage transistor M N Is connected with the body pole, and the body pole common resistance R BC The other end of the first control end is connected with the second control end.
In some embodiments, the set of control terminals 50 includes two control terminals (e.g., a first control terminal and a second control terminal); in the example where the bias circuit 20 is implemented by a body bias resistor, for example, the set of control terminals 50 may include two control terminals. In some embodiments where the control terminal set 50 includes two control terminals: common resistor R of gate of bias circuit 10 GC (ii) a Gate common resistance R GC And a transistor of an arbitrary stage such as an Nth-stage transistor M N Is connected to the gate node of the gate common resistor R GC Is connected with one of the control terminals (for example, the first control terminal); the body bias circuit 20 further includes a body common resistor R BC (ii) a Body pole common resistance R BC And a transistor of an arbitrary stage such as the Nth stage transistor M N Is connected with the body pole, and the body pole is connected with the common resistor R BC And the other end of the second switch is connected to another control terminal (e.g., a second control terminal).
Fig. 5 is an example of a radio frequency switch circuit.
In FIG. 5, R G1 To R G(N-1) Representing N-1 gate bias resistors, R B1 To R B(N-1) Denotes N-1 individual pole bias resistance, R DS1 To R DSN Representing N source drain bias resistors; r GC Representing the gate common resistance, R BC Represents a bulk pole common resistance; the RF switch circuit shown in FIG. 5 is a transistor M of each stage 1 To transistor M N Are provided with a configuration resistor, wherein the resistor R GPK Is a K-th stage transistor M K The value range of K is 1 to N; the structure of fig. 5 can accelerate the speed of switching the radio frequency switch circuit from off to on to turn on, and shorten the time of switching the radio frequency switch circuit from off to on to turn on, which is analyzed below.
The source and drain electrodes of each cascaded transistor in the radio frequency switch circuit are biased at zero potential, the on and off are mainly determined by grid voltage, and the body voltage can be ignored due to the second-order effect; whether the gate voltage completes switching therefore determines whether the transistor completes switching. Taking the circuit structure shown in fig. 2 as an example, during the switching process from off to on, the dc bias voltage 1 is switched from negative voltage to positive voltage, and the nth transistor M N After the gate voltage exceeds the threshold voltage, the transistor M N The radio frequency switch circuit is still in a turn-off state because other transistors are not turned on at the moment; then transistor M N-1 Is turned on and then sequentially until transistor M 1 And finally, the radio frequency switch circuit is conducted. In the switching process from on to off, the direct current bias voltage 1 is switched from positive voltage to negative voltage, and the transistor M N After the grid voltage is lower than the threshold voltage, the transistor M N When the radio frequency switch circuit is switched off, the whole path is switched off or cut off as long as the primary transistor in the radio frequency switch circuit is switched off. Therefore, as can be seen from the above analysis, all transistors are required to be turned on from the turn-off to the turn-on of the rf switch circuit, the turn-on time is relatively slow, and only one stage of transistor is required to be turned off when the rf switch circuit is turned off, so that the turn-off time is realizedRelatively fast. In some embodiments, configuration resistors may be introduced to the transistors at each stage to adjust the voltage rise time of the transistors at each stage, and according to actual requirements, the configuration resistors R may be provided GP1 To a configuration resistance R GPN Designing a corresponding value so that the gate circuits of the transistors at each stage are simultaneously lifted in the switching process from turn-off to turn-on of the radio frequency switch circuit, and after the gate voltage of the transistors at each stage exceeds the corresponding threshold voltage, the transistors at each stage are all switched on so as to switch on the radio frequency switch circuit; compared with the circuit structure shown in fig. 2, for example, the radio frequency switch circuit with the configuration resistor does not need to wait for the transistors of each stage to be sequentially turned on like the circuit structure shown in fig. 2, so that the radio frequency switch circuit with the configuration resistor can speed up the switching of the radio frequency switch circuit from off to on so as to be turned on, and shorten the time for switching the radio frequency switch circuit from off to on so as to be turned on.
Fig. 6 is an example of a radio frequency switch circuit.
Compared with the rf switch circuit of fig. 5, the rf switch circuit of fig. 6 has only one control terminal and is provided for each stage of the transistor M 1 To transistor M N A bias transistor is provided instead of the body bias resistor, wherein the bias transistor M Kb Is a Kth transistor M K K ranges from 1 to N.
By introducing the bias transistors, the transistors (referred to as multi-stage transistors M) of the corresponding stages of the bias transistors can be reduced when the radio frequency switch circuit is switched from on to off 1 To M N ) The magnitude of the voltage rise due to leakage current.
In some embodiments of the present application, a bias circuit for the first control electrode is implemented by constructing a T-shaped bias structure for the transistor, so that the speed of switching the radio frequency switch circuit from off to on to turn on can be increased, and the time of switching the radio frequency switch circuit from off to on to turn on can be shortened.
Reference is made herein to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope hereof. For example, the various operational steps, as well as the components for performing the operational steps, may be implemented in differing ways depending upon the particular application or consideration of any number of cost functions associated with the operation of the system (e.g., one or more steps may be deleted, modified, or combined with other steps).
While the principles herein have been illustrated in various embodiments, many modifications of structure, arrangement, proportions, elements, materials, and components particularly adapted to specific environments and operative requirements may be employed without departing from the principles and scope of the present disclosure. The above modifications and other changes or modifications are intended to be included within the scope of this document.
The foregoing detailed description has been described with reference to various embodiments. However, one skilled in the art will recognize that various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the disclosure is to be considered in all respects as illustrative and not restrictive, and all such modifications are intended to be included within the scope thereof. Also, advantages, other advantages, and solutions to problems have been described above with regard to various embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any element(s) to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, system, article, or apparatus. Furthermore, the term "coupled," and any other variation thereof, as used herein, refers to a physical connection, an electrical connection, a magnetic connection, an optical connection, a communicative connection, a functional connection, and/or any other connection.
Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined only by the claims.
Claims (14)
1. A radio frequency switch circuit is characterized by comprising a radio frequency input port, a radio frequency output port, an N-stage transistor, a grid bias circuit, a body bias circuit, a source-drain bias circuit and a control end group, wherein the N-stage transistor is cascaded between the radio frequency input port and the radio frequency output port;
the radio frequency input port is used for inputting radio frequency signals;
the radio frequency output port is used for outputting radio frequency signals;
the transistor comprises a grid electrode, a body electrode, a first electrode and a second electrode, wherein if the first electrode is a source electrode, the second electrode is a drain electrode, and if the first electrode is a drain electrode, the second electrode is a source electrode; the transistors are cascaded with their neighboring transistors by their first or second poles; n is an integer greater than or equal to 2;
the grid biasing circuit is used for providing a biasing voltage for the grid of each transistor; the gate bias circuit includes: the circuit comprises N grid nodes, N-1 grid bias resistors and N configuration resistors, wherein each grid node corresponds to a transistor; the grid electrode of each transistor is connected with the grid electrode node corresponding to the transistor through one configuration resistor; the grid bias resistor is connected between grid nodes corresponding to adjacent transistors in each group of transistors;
the body electrode bias circuit is used for providing bias voltage for the body electrode of each transistor;
the source-drain electrode bias circuit is used for providing bias voltage for the source electrode and the drain electrode of each transistor;
the control end group is used for receiving control signals; the control signal is used for controlling bias voltages provided by the body electrode bias circuit, the grid electrode bias circuit and the source drain electrode bias circuit to the body electrode, the grid electrode, the source electrode and the drain electrode of each transistor so as to control the on and off of the transistors.
2. The radio frequency switch circuit of claim 1, wherein the body bias circuit comprises: the transistor comprises N individual pole nodes and N-1 individual pole bias resistors, each body pole node corresponds to one transistor, the body pole bias resistors are connected between the body pole nodes corresponding to adjacent transistors in each group of transistors, and the body poles of the transistors are directly connected with the body pole nodes corresponding to the transistors.
3. The radio frequency switch circuit of claim 1, wherein the body bias circuit comprises: n bias transistors, one for each transistor; the grid electrode, the body electrode and the first electrode of the bias transistor are all connected to the grid electrode node of the corresponding transistor, and the second electrode of the bias transistor is connected to the body electrode of the transistor of the corresponding stage; or the grid electrode, the body electrode and the first electrode of the bias transistor are all connected to the body electrode of the corresponding transistor, and the second electrode of the bias transistor is connected to the grid electrode node of the corresponding transistor.
4. The radio frequency switch circuit of claim 1, wherein the source drain bias circuit comprises: and the source-drain bias resistors are connected between the first electrode and the second electrode of each transistor.
5. The radio frequency switch circuit of any of claims 1 to 4, wherein the set of control terminals includes a first control terminal, the gate bias circuit further including a gate common resistance; one end of the grid common resistor is connected with a grid node corresponding to the Nth-stage transistor, and the other end of the grid common resistor is connected with the first control end.
6. The radio frequency switch circuit of claim 5, wherein the set of control terminals includes a second control terminal, the body bias circuit further including a body common resistance; and one end of the body electrode common resistor is connected with a body electrode node corresponding to the Nth-stage transistor, and the other end of the body electrode common resistor is connected with the second control end.
7. A radio frequency switch circuit, comprising:
the radio frequency input port is used for inputting radio frequency signals;
a radio frequency output port for outputting a radio frequency signal;
a multi-stage transistor cascaded between the radio frequency input port and the radio frequency output port, the transistor comprising at least a first control electrode, a first electrode and a second electrode;
a bias circuit for the first control electrode, for providing a bias voltage to the first control electrode of each transistor; the bias circuit for the first control electrode includes: a first gate bias resistor connected between the first gate nodes of each adjacent transistor, and a configuration resistor connected between the first gate and the first gate node of each transistor; wherein each transistor corresponds to a first gate node;
a bias circuit for the first and second poles for providing a bias voltage to the first and second poles of each transistor;
the control end group is used for receiving control signals; the control signal is used for controlling the bias voltage provided by each bias circuit to each transistor so as to control the on and off of the transistors.
8. The radio frequency switch circuit of claim 7, wherein the transistor further comprises a second control electrode; the radio frequency switch circuit further comprises a bias circuit for the second control electrode for providing a bias voltage to the second control electrode of each transistor.
9. The radio frequency switch circuit of claim 8, wherein the bias circuit for the second control pole comprises: and a second gate bias resistor connected between the second gates of adjacent transistors.
10. The radio frequency switching circuit of claim 8, wherein the bias circuit for the second gate comprises: a bias transistor provided for each transistor; the transistor of each stage corresponds to a bias transistor;
the first pole, the first control pole and the second control pole of the bias transistor are connected to the first control pole node of the transistor of the corresponding stage, and the second pole of the bias transistor is connected to the second control pole of the transistor of the corresponding stage; or the first electrode, the first control electrode and the second control electrode of the bias transistor are all connected to the second control electrode of the transistor of the corresponding stage, and the second electrode of the bias transistor is connected to the first control electrode node of the transistor of the corresponding stage.
11. The radio frequency switching circuit of claim 7, wherein the bias circuit for the first pole and the second pole comprises: a first diode bias resistor connected between the first and second poles of each transistor.
12. The radio frequency switch circuit of claim 7, the set of control terminals comprising a first control terminal;
the bias circuit for the first control electrode further comprises a first control electrode common resistor; one end of the first control electrode common resistor is connected with a first control electrode node corresponding to the transistor of any stage, and the other end of the first control electrode common resistor is connected with the first control end; the transistor of any stage is the transistor of the last stage.
13. The radio frequency switch circuit of claim 9, the set of control terminals including a second control terminal;
the bias circuit for the second control electrode further comprises a second control electrode common resistor; one end of the second control electrode common resistor is connected with the second control electrode of the transistor at any stage, and the other end of the second control electrode common resistor is connected with the second control end; the transistor of any stage is the transistor of the last stage.
14. The radio frequency switch circuit of claim 7, wherein the multi-stage transistor is an at least three-stage transistor, an at least four-stage transistor, or an at least five-stage transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221405114.0U CN217985025U (en) | 2022-06-06 | 2022-06-06 | Radio frequency switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221405114.0U CN217985025U (en) | 2022-06-06 | 2022-06-06 | Radio frequency switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217985025U true CN217985025U (en) | 2022-12-06 |
Family
ID=84271315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221405114.0U Active CN217985025U (en) | 2022-06-06 | 2022-06-06 | Radio frequency switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217985025U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118100892A (en) * | 2024-04-25 | 2024-05-28 | 成都明夷电子科技股份有限公司 | Single-channel radio frequency switch chip circuit structure, layout structure and high-frequency isolation optimization method |
-
2022
- 2022-06-06 CN CN202221405114.0U patent/CN217985025U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118100892A (en) * | 2024-04-25 | 2024-05-28 | 成都明夷电子科技股份有限公司 | Single-channel radio frequency switch chip circuit structure, layout structure and high-frequency isolation optimization method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104980135B (en) | System and method for driving RF switch | |
| US5945867A (en) | Switch circuit device | |
| JP3736356B2 (en) | High frequency switch circuit | |
| CN113472329B (en) | Radio frequency switching circuit for optimizing voltage-withstanding uniformity of stacked switching tube | |
| KR101452072B1 (en) | Radio frequency switch circuit | |
| CN113595542B (en) | Single-pole double-throw radio frequency switch | |
| CN110719092A (en) | Radio frequency switch circuit structure | |
| JP2007259112A (en) | High frequency switch circuit and semiconductor device | |
| KR20110068585A (en) | Speed Switch for High Frequency Band Switching and Switching Isolation Enhancement Method | |
| KR20230114717A (en) | Rf switch with switching time acceleration | |
| CN217985025U (en) | Radio frequency switch circuit | |
| CN115378410B (en) | A radio frequency switch circuit and a radio frequency module | |
| CN217985024U (en) | Radio frequency switch circuit | |
| CN217985026U (en) | Radio frequency switch circuit | |
| CN215897704U (en) | Radio frequency switching circuit and multi-stage buffer | |
| CN117040504A (en) | Radio frequency switch circuit | |
| KR20090003182A (en) | Method and system for high power switching | |
| CN113572467A (en) | A radio frequency switching circuit for improving harmonics | |
| CN117040509A (en) | Radio frequency switch circuit | |
| CN101394173A (en) | SPDT Switch Based on Enhanced PHEMT | |
| US8866466B2 (en) | Power generating circuit and switching circuit | |
| CN215773068U (en) | Radio frequency switch circuit for optimizing voltage withstanding uniformity of stacked switch tubes | |
| CN215773071U (en) | Radio frequency switch circuit for improving harmonic wave | |
| CN117674784A (en) | Radio frequency switch and control method thereof | |
| CN213243961U (en) | Radio frequency switch circuit, wireless device and mobile terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |