CN212323727U - Power failure protection circuit - Google Patents
Power failure protection circuit Download PDFInfo
- Publication number
- CN212323727U CN212323727U CN202021747154.4U CN202021747154U CN212323727U CN 212323727 U CN212323727 U CN 212323727U CN 202021747154 U CN202021747154 U CN 202021747154U CN 212323727 U CN212323727 U CN 212323727U
- Authority
- CN
- China
- Prior art keywords
- circuit
- pin
- resistor
- input pin
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Protection Of Static Devices (AREA)
- Power Conversion In General (AREA)
Abstract
本实用新型公开了一种停电保护电路，包括主电路、电源电路、检测电路和逻辑控制电路，主电路为带光电隔离器U4的双向可控硅开关电路；电源电路为半波整流电路；电源电路与检测电路之间设有开关SW1，检测电路包括延时电路和开关状态检测电路，可实现对电网和开关SW1的状态检测；逻辑控制电路包括与非逻辑控制器U1、U2、U3，控制U4的输入脚2电平，从而控制U4“1”和“2”脚之间的电压差实现对双向可控硅的控制。当工作电路运行时突然停电，电网和开关检测信号异常，电路停止运行，开关SW1未断开；上电后电网检测正常，但检测到开关处于闭合状态，逻辑控制电路不会输出触发信号，启动主电路，需对开关进行断开再闭合操作才可正常运行。
The utility model discloses a power failure protection circuit, comprising a main circuit, a power supply circuit, a detection circuit and a logic control circuit. The main circuit is a bidirectional thyristor switch circuit with a photoelectric isolator U4; the power supply circuit is a half-wave rectifier circuit; There is a switch SW1 between the circuit and the detection circuit. The detection circuit includes a delay circuit and a switch state detection circuit, which can realize the state detection of the power grid and the switch SW1; the logic control circuit includes NAND logic controllers U1, U2, and U3, which control The input pin 2 of U4 is level, thereby controlling the voltage difference between the "1" and "2" pins of U4 to control the triac. When there is a sudden power failure when the working circuit is running, the grid and switch detection signals are abnormal, the circuit stops running, and the switch SW1 is not disconnected; after power-on, the grid detection is normal, but it is detected that the switch is in a closed state, the logic control circuit will not output a trigger signal, start For the main circuit, the switch needs to be opened and closed to operate normally.
Description
Technical Field
The utility model belongs to the technical field of the power electronic protection, in particular to power failure protection circuit.
Background
Common household appliances such as an electric heating furnace, an electric lamp, an electric tool and the like adopt a common on-off switch as a main element for switching on and off a circuit, when the household appliances are electrified again after sudden power failure, the circuit can be automatically restarted, so that a large potential safety hazard exists for the electric furnace, the electric tool and the like, and the electric energy waste can be caused for an illumination circuit; therefore, it is necessary to design a new circuit with power failure protection function.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a power failure protection circuit has solved the automatic problem of restarting of circuit after the outage.
The utility model discloses a realize through following technical scheme:
a power failure protection circuit comprises a power supply circuit, a detection circuit, a logic control circuit and a main circuit;
the power supply circuit is used for converting alternating current into direct current;
a switch SW1 is arranged between the power supply circuit and the detection circuit, the detection circuit comprises a delay circuit and a switch state detection circuit, the delay circuit is used for detecting the state of the power grid, and the switch state detection circuit is used for detecting the state of a switch SW 1;
the logic control circuit comprises a NAND logic controller U1, a NAND logic controller U2 and a NAND logic controller U3, the NAND logic controller U1 comprises an input pin 1, an input pin 2 and an output pin 3, the NAND logic controller U2 comprises an input pin 4, an input pin 5 and an output pin 6, and the NAND logic controller U3 comprises an input pin 9, an input pin 10 and an output pin 11;
the switch SW1 is connected with the input pin 4 and the input pin 9 through the switch state detection circuit, the delay circuit is connected with the input pin 2, the output pin 3 is connected with the input pin 5, the input pin 1 is connected with the output pin 6, and the input pin 10 is connected with the output pin 6;
the main circuit is a bidirectional thyristor circuit with a drive, one input end of the main circuit is connected with the output end of the power circuit, the other input end of the main circuit is connected with the output pin 11 of the NAND logic controller U3, and when the output pin 11 outputs high level, the bidirectional thyristor circuit is not conducted; when the output pin 11 outputs a low level, the triac circuit is turned on to supply power to the load.
Further, when the switch SW1 is in the off state, the output state of the switch state detection circuit is at low level, and the input pin 4 and the input pin 9 are at low level; when the SW1 is in the closed state, the output state of the switch state detection circuit is at high level, and the input pin 4 and the input pin 9 are at high level;
when the input end of the power circuit is not connected to the power grid, the input pin 2 is at a low level, and when the input end of the power circuit is connected to the power grid, the input pin 2 is at a high level.
Further, the power supply circuit comprises a diode D1, a resistor R1, a voltage stabilizing diode D2 and a capacitor C1, the diode D1, the resistor R1 and the capacitor C1 are sequentially connected, and the voltage stabilizing diode D2 and the capacitor C1 are arranged in parallel;
the diode D1 is used for converting alternating current into direct current, the resistor R1 and the internal resistance of the circuit form a voltage division circuit, the capacitor C1 is used for filtering, and the voltage stabilizing diode D2 is used for protecting a post-stage circuit.
Further, the main circuit comprises a photoelectric isolator U4 and a bidirectional triode thyristor TRIAC1, an input pin 1 of the photoelectric isolator U4 is connected with the output end of the power supply circuit through a resistor R5, and an input pin 2 of the photoelectric isolator U4 is connected with an output pin 11 of the NAND logic controller U3;
an output pin 4 of the photoelectric isolator U4 is connected with one end of a bidirectional triode thyristor TRIAC1 through a resistor R7, and an output pin 6 of the photoelectric isolator U4 is connected with the other end of the bidirectional triode thyristor TRIAC 1;
the resistor R5, the photoelectric isolator U4 and the resistor R7 form a driving circuit of the bidirectional triode thyristor TRIAC 1.
Further, the TRIAC1 is model BAT 06-600.
Furthermore, the delay circuit comprises a resistor R4 and a capacitor C3, the input end of the resistor R4 is connected with the output end of the power circuit, the output end of the resistor R4 is respectively connected with one end of the capacitor C3 and the input pin 2 of the U1, and the other end of the capacitor C3 is connected with the negative electrode of the power supply.
Further, the switch state detection circuit comprises a diode D3, a resistor R3, a capacitor C2 and a resistor R6, the diode D3, the resistor R3 and the resistor R6 are sequentially connected, the resistor R6 and the capacitor C2 are arranged in parallel, and the output end of the resistor R3 is connected with the input pin 4 of the U2 and the input pin 9 of the U3;
the diode D3 is used for converting alternating current into direct current, and the resistor R3 and the resistor R6 form a voltage division circuit; the capacitor C2 is used for filtering to obtain a flat switching signal.
Further, the nand logic controller U1, the nand logic controller U2, and the nand logic controller U3 all employ schmitt nand gates.
Compared with the prior art, the utility model discloses following profitable technological effect has:
the utility model discloses a power failure protection circuit, which comprises a main circuit, a power circuit, a detection circuit and a logic control circuit, wherein the main circuit is a bidirectional thyristor circuit with a drive, the detection circuit comprises a time delay circuit and a switch state detection circuit, and the state detection of a power grid and a switch SW1 can be realized; the logic control circuit comprises NAND logic controllers U1, U2 and U3, and the working modes of the logic control circuit are determined according to high-low level signals of pins U1, U2 and U3. When the output pin 11 of the U3 outputs high level, the bidirectional thyristor is not conducted; when the output pin 11 of the U3 outputs a low level, the triac conducts and supplies power to the load. When the working circuit is suddenly powered off in operation, the power grid and the switch detection signals are abnormal, the circuit stops operating, and the switch SW1 is not disconnected; after the power is on, the power grid is normally detected, but the logic control circuit does not output a trigger signal when the switch is detected to be in a closed state, the main circuit is started, and the normal operation can be realized only by carrying out the operation of opening and then closing the switch.
Further, the main circuit comprises a photoelectric isolator U4 and a bidirectional triode thyristor TRIAC1, one of two input pins of the photoelectric isolator is connected with the power circuit, the other input pin of the photoelectric isolator is connected with an output pin of the NAND logic controller U3, and the bidirectional triode thyristor is controlled by controlling the voltage difference between the two input pins of the U4.
Further, a diode D1 converts alternating current into direct current, and the grid voltage converts the alternating current into the direct current through a diode D1; because the amplitude of the rectified grid voltage is higher, the voltage is reduced by using a voltage division circuit, the voltage division circuit is composed of a resistor R1 and the internal resistance of the circuit, and the resistor R1 divides the voltage with the internal resistance of the circuit to obtain the required voltage level; the rectified direct current is pulsating direct current, the stable operation of the circuit needs direct current with small fluctuation, and the capacitor C1 is a filter circuit to reduce the pulsation of the direct current; the direct current is filtered by a capacitor C1, and in order to prevent the sudden surge of the power grid voltage, a voltage stabilizing diode D2 is used for protecting a post-stage circuit, so that the post-stage circuit can be protected by instantaneous overvoltage of the circuit, and the voltage stabilizing diode D2 is used for protecting the overvoltage of the power grid.
Drawings
Fig. 1 is a schematic circuit diagram of a power failure protection circuit of the present invention.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
As shown in fig. 1, the utility model discloses a power failure protection circuit, including main circuit, power supply circuit, detection circuitry and logic control circuit. The main circuit is a bidirectional silicon controlled rectifier circuit with a drive; the power supply circuit is a half-wave rectifying circuit and is used for converting alternating current into direct current; a switch SW1 is arranged between the power supply circuit and the detection circuit, the detection circuit comprises a delay circuit and a switch state detection circuit, the delay circuit is used for detecting the state of the power grid, and the switch state detection circuit is used for detecting the state of a switch SW 1; the logic control circuit comprises three NAND logic controllers, and the level of the pin 2 of the photoelectric isolator U4 is controlled through the connection of the three NAND logic controllers, so that the voltage difference between the pin 1 and the pin 2 of the U4 is controlled to realize the control of the bidirectional triode thyristor.
The main circuit comprises a photoelectric isolator U4 and a bidirectional thyristor TRIAC1, an input pin 1 of the photoelectric isolator U4 is connected with a power circuit, an input pin 2 of the photoelectric isolator U4 is connected with an output pin 11 of the NAND logic controller U3, and an output pin of the photoelectric isolator U4 is connected with a bidirectional thyristor TRIAC 1. The optoelectronic isolator U4 is used as a driving device, and the level of the pin 2 of the optoelectronic isolator U4 is controlled through the connection of three NAND logic controllers, so that the voltage difference between the pin 1 and the pin 2 of the U4 is controlled to realize the control of the bidirectional triode thyristor.
Specifically, the logic control circuit comprises a nand logic controller U1, a nand logic controller U2 and a nand logic controller U3, the nand logic controller U1 comprises an input pin 1, an input pin 2 and an output pin 3, the nand logic controller U2 comprises an input pin 4, an input pin 5 and an output pin 6, and the nand logic controller U3 comprises an input pin 9, an input pin 10 and an output pin 11.
Specifically, the power supply circuit comprises a diode D1, a resistor R1, a voltage stabilizing diode D2 and a capacitor C1, wherein the diode D1, the resistor R1 and the capacitor C1 are sequentially connected, and the voltage stabilizing diode D2 is connected with the capacitor C1 in parallel; the circuit needs a direct current power supply for working, so an alternating current and direct current conversion circuit is formed by the diode D1, the resistor R1, the voltage stabilizing diode D2 and the capacitor C1, and the direct current power supply is provided for a system. The rectifying part of the power supply circuit uses the simplest half-wave rectifying circuit, wherein a diode D1 converts alternating current into direct current, and the grid voltage converts the alternating current into the direct current through a diode D1; because the amplitude of the rectified grid voltage is higher, the voltage is reduced by using a voltage division circuit, the voltage division circuit is composed of a resistor R1 and the internal resistance of the circuit, and the resistor R1 divides the voltage with the internal resistance of the circuit to obtain the required voltage level; the rectified direct current is pulsating direct current, the stable operation of the circuit needs direct current with small fluctuation, and the capacitor C1 is a filter circuit to reduce the pulsation of the direct current; the direct current is filtered by a capacitor C1, and in order to prevent the sudden surge of the power grid voltage, a voltage stabilizing diode D2 is used for protecting a post-stage circuit, so that the post-stage circuit can be protected by instantaneous overvoltage of the circuit, and the voltage stabilizing diode D2 is used for protecting the overvoltage of the power grid.
As shown in FIG. 1, the delay circuit is composed of a resistor R4 and a capacitor C3, the input end of the resistor R4 is connected with the output end of the resistor R1, the output end of the resistor R4 is respectively connected with one end of a capacitor C3 and an input pin 2 of U1, and the other end of the capacitor C3 is connected with the negative electrode of a power supply. After the alternating current input end is connected to a power grid, the direct current power supply outputs a stable direct current power supply, so that the direct current power supply can be provided for a system, and the direct current power supply is not controlled by a switch SW1 and can work as long as a power failure protection circuit is connected to a mains supply, so that the working state (normal power supply or power failure state) of the power grid can be judged by detecting the output of the direct current power supply through a delay circuit formed by a resistor R4 and a capacitor C3, when the power grid normally supplies power, after the delay circuit formed by the resistor R4 and the capacitor C3 finishes charging, the input pin 2 of the U1 is at a high level, and otherwise, when the power grid fails, the input pin 2 of the U1 is at a.
When the switch SW1 is in the off state, the switch state detection circuit composed of the diode D3, the resistor R3, the capacitor C2 and the resistor R6 outputs a low level, that is, the input pin 4 of the U2 is at a low level. When SW1 is in the closed state, the switch state detection circuit will output a high level, i.e., input pin 4 of U2 will be at a high level.
Similar to the power circuit, the switch state detection circuit composed of the diode D3, the resistor R3, the capacitor C2 and the resistor R6 converts alternating current into direct current by using a half-wave rectification circuit, the main part of the switch state detection circuit is the diode D3, the voltage level is reduced by using a voltage division circuit, the voltage division circuit is composed of a resistor R3 and an equivalent resistor R6 of a pin, in order to reduce voltage fluctuation, filtering is performed by using the capacitor C2 to obtain a relatively flat switch signal, and when the switch SW1 is in an off state, the switch state detection circuit outputs a low level, namely the input pin 4 of the U2 is in a low level. When SW1 is in the closed state, the switch state detection circuit will output a high level, i.e., input pin 4 of U2 will be at a high level.
The circuit comprises a bidirectional thyristor drive circuit, a resistor R5, a photoelectric isolator U4 and a resistor R7, wherein an input pin 1 of the U4 is connected with a resistor R1 through a resistor R5, an output pin 4 of the U4 is connected with one end of a bidirectional thyristor TRIAC1 through a resistor R7, and an output pin 6 of the U4 is connected with the other end of the bidirectional thyristor TRIAC 1; input pin 2 of U4 is connected to output pin 11 of U3, and output pin 6 of U4 is connected to pin 3 of the triac. One end of the resistor R7 is connected with the 2 pin of the bidirectional controllable silicon, and the other end is connected with the output pin 4 of the U4.
When the pin 2 of the U4 is at a high level, the light emitting diode in the U4 is not turned on, and the controlled diodes connected to the pins 6 and 4 of the U4 in the U4 are not turned on, which cannot trigger the conduction of the TRIAC1, whereas if the pin 2 of the U4 is at a low level, the TRIAC1 is turned on. R7 is a current limiting resistor to prevent excessive conduction current when the controlled diode inside U4 is conducting. Pin 3 of TRIAC1 is the gate of TRIAC, as long as pin 2 of U4 is low level, pin 3 of TRIAC1 will have the trigger signal, and pin 1 and pin 2 of TRIAC1 are conductive, if pin 2 of U4 is high level, pin 1 and pin 2 of TRIAC1 do not have the trigger signal, and the TRIAC is disconnected.
U1, U2 and U3 constitute the logic control circuit of the power failure protection circuit. The power supply state of the power grid is judged through the high-low level state of the pin 2 of the U1; the switch state of the switch SW1 is determined by determining the 4-pin high-low state of U2.
Assume that 1 represents high and 0 represents low. There are the following operation modes, and table 1-table 7 show the pin levels of the circuits U1, U2, U3 and U4 in each operation state.
Mode I: when the input end of the power failure protection circuit is connected to the power grid, the switch SW1 is in an off state. At this time, since the resistor R4 and the capacitor C3 form a delay circuit, the pin 2 of the U1 is at a low level before the voltage of the capacitor C3 does not reach the threshold voltage of the U1. At the same time, since the switch SW1 is in the off state, the 4-pin of U2 is also in the low level. Therefore, the 3 pin of U1 and the 6 pin of U2 both output high, the 1 pin of U1 is connected to the 6 pin of U2, and the 1 pin of U1 is also high. Since pin 9 of U3 is connected to pin 4 of U2, pin 11 of U3 also outputs a high level. Therefore, pin 2 of U4 is at high level, the led inside U4 cannot be turned on, and TRIAC1 is off and cannot supply power to the load. The truth tables of the U1, U2 and U3 pins are shown in Table 1.
TABLE 1 truth table of U1, U2 and U3 pins in mode I
Mode II: when the input of the power failure protection circuit is connected to the power grid, the switch SW1 is still in the off state. At this time, the delay circuit formed by the resistor R4 and the capacitor C3 has completed the charging process, i.e., the voltage on the capacitor C3 has reached the threshold voltage of U1, and pin 2 of U1 is at a high level. Since pin 1 of U1 is also at a level at this time, pin 3 of U1 outputs a low level at this time. Since pin 5 of U2 is connected to pin 3 of U1, pin 5 of U2 is also low; since switch SW1 is still in the open state, pin 4 of U2 is still in the low state and so the pin 6 output of U2 is still high. At the same time, the level states of the pin 9 and the pin 10 of the U3 are also kept unchanged, so the output of the pin 11 of the U3 is still at a high level, and the internal light emitting diode of the U4 is turned off. The truth tables of the U1, U2 and U3 pins are shown in Table 2.
TABLE 2 mode II pins truth table for U1, U2 and U3
Mode III: in the mode II state, switch SW1 is closed. The switch state detection circuit composed of the diode D3, the resistor R3, the capacitor C2 and the resistor R6 outputs a high level, and at this time, the 4 pin of U2 and the 9 pin of U3 are converted from a low level to a high level. The state of U1 does not change, pin 5 of U2 is still low, so pin 6 of U2 is still high, so pin 10 of U3 is still high, so pin 11 of U3 is low. And an internal light emitting diode of the U4 is conducted to trigger the TRIAC1 to be conducted, so that power is supplied to the electric load connected with the output end. The truth tables of the U1, U2 and U3 pins are shown in Table 3.
TABLE 3 mode III pins truth table for U1, U2 and U3
Mode IV: when the power grid is normally supplied, the pin states of the switches SW1, U1, U2 and U3 are turned off at this time, and the pin state in the mode II is restored, and the TRIAC1 is turned off, as shown in table 4.
TABLE 4 MODE IV U1, U2, U3 Pin truth Table
V: in the mode III state, when the power grid is suddenly powered off, the switch SW1 is still in the closed state, and the power supply of the power grid is recovered after a while. Due to the existence of the time delay circuit in the grid state detection circuit, the 2 pin of the U1 still keeps low level before the capacitor C3 does not reach the threshold voltage of the U1, so the 3 pin of the U1 outputs high level. Since the switch detection circuit outputs high, pin 4 of U2 is high, and pin 5 of U2 is connected to pin 3 of U1 and is also high, pin 6 of U2 outputs low. Therefore, pin 10 of U3 is low, pin 11 of U3 outputs high, the led in U4 is not conducting, and U4 does not send trigger signal so the TRIAC1 is not conducting. Thus, even if switch SW1 is closed, power is not supplied to the electrical load. The truth tables of the U1, U2 and U3 pins are shown in Table 5.
TABLE 5 mode V U1, U2, U3 pin truth table
Mode VI: after the capacitor C3 is charged for a period of time, when the voltage of the capacitor C3 reaches the threshold voltage of U1, the pin 2 of the U1 changes from low level to high level, and at this time, because the pin 1 of the U1 is still at low level, the pin levels of the U2 and the U3 do not change, the output of the pin U13 is still at high level, the U4 is not conducted, and the TRIAC1 is still turned off. The truth tables of the U1, U2 and U3 pins are shown in Table 6.
TABLE 6 mode VI U1, U2, U3 pin truth table
Mode VII: in the state of VI, the switch SW1 is turned off, and pin 4 of U2 is changed from high level to low level, so pin 6 of U2 outputs high level, pin 9 of U3 is changed from high level to low level, and pin 10 of U3 is changed from low level to high level, so pin 11 of U3 still outputs high level, and the TRIAC1 is turned off. Meanwhile, pin 1 of U1 changes from low to high, pin 2 of U1 is still high, so pin 3 of U1 outputs low, and pin 5 of U2 also changes from high to low. The truth tables of the U1, U2 and U3 pins are shown in Table 7.
TABLE 7 mode VII U1, U2, U3 pin truth table
From tables 7 and 2 it can be seen that state VII has the same logic state as state II. The logic state of the outage protection circuit will be in state III when switch SW1 is closed again.
As can be seen from the above analysis, the power failure protection circuit shown in fig. 1 has a function of recovering power supply again when the power supply is interrupted, and even if the switch or the power outlet switch is in a closed state, the power supply can be cut off, and power supply is not supplied to the electrical appliance to which the power failure protection circuit belongs, and power supply is recovered only after the switch is operated again.
The utility model discloses an each circuit component parameter is shown as table 8:
TABLE 8 Circuit element parameters and models
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021747154.4U CN212323727U (en) | 2020-08-19 | 2020-08-19 | Power failure protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021747154.4U CN212323727U (en) | 2020-08-19 | 2020-08-19 | Power failure protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212323727U true CN212323727U (en) | 2021-01-08 |
Family
ID=74035318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021747154.4U Expired - Fee Related CN212323727U (en) | 2020-08-19 | 2020-08-19 | Power failure protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212323727U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111884191A (en) * | 2020-08-19 | 2020-11-03 | 陕西科技大学 | Power failure protection circuit and application thereof |
-
2020
- 2020-08-19 CN CN202021747154.4U patent/CN212323727U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111884191A (en) * | 2020-08-19 | 2020-11-03 | 陕西科技大学 | Power failure protection circuit and application thereof |
| CN111884191B (en) * | 2020-08-19 | 2024-11-19 | 陕西科技大学 | A power failure protection circuit and its application |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203537047U (en) | An Uninterruptible Power Supply System with Dual-Input Intelligent Power Supply | |
| WO2010094215A1 (en) | Power supply control device and ventilating device using same | |
| CN107094326A (en) | LED lighting control circuit | |
| CN109041373A (en) | Flash switch detection circuit and Intelligent lamp | |
| WO2019033237A1 (en) | Electric leakage protection circuit, electric leakage protection apparatus and led apparatus | |
| CN109769321A (en) | A kind of LED lamp circuit with Delayed extinguishing function | |
| CN212323727U (en) | Power failure protection circuit | |
| CN109946598A (en) | Double control switch detection circuit and device | |
| JP5325603B2 (en) | Electronic switch with TRIAC control / stabilized power circuit | |
| CN209658987U (en) | Low-voltage dc power supply with overvoltage protection | |
| CN111884191B (en) | A power failure protection circuit and its application | |
| CN208445503U (en) | Circuit for controlling motor and burnisher | |
| CN207531122U (en) | A kind of LED fishing lamps power supply output switching circuit | |
| CN104135793B (en) | A kind of circuit using on and off switch to adjust electrical parameter | |
| CN107666305B (en) | Intelligent switch | |
| CN206411505U (en) | A kind of robot system and its opening/closing control device | |
| CN105675977B (en) | A kind of electric energy meter and method with front stage detection of power loss | |
| CN106971922A (en) | Inexpensive low standby power loss takes control breaker control system and control method | |
| CN203398457U (en) | Intelligent household electrical appliance standby energy-saving socket | |
| WO2022134239A1 (en) | Wide-voltage alternating current circuit suitable for high-power switch | |
| CN211429586U (en) | Sectional switch controller circuit | |
| CN210639450U (en) | Intelligent detection zero-power consumption multi-mode switching control circuit | |
| CN219936044U (en) | Relay on-off detection circuit and household appliance | |
| CN201039120Y (en) | Two-line capacitance touch and induction switch | |
| CN209748872U (en) | acousto-optic controlled delay switch and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210108 Termination date: 20210819 |