CN211700266U - TSV (through silicon via) interconnection link structure and chip packaging structure - Google Patents
TSV (through silicon via) interconnection link structure and chip packaging structure Download PDFInfo
- Publication number
- CN211700266U CN211700266U CN202020845588.1U CN202020845588U CN211700266U CN 211700266 U CN211700266 U CN 211700266U CN 202020845588 U CN202020845588 U CN 202020845588U CN 211700266 U CN211700266 U CN 211700266U
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- pair
- metal pad
- tsv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims description 18
- 229910052710 silicon Inorganic materials 0.000 title description 9
- 239000010703 silicon Substances 0.000 title description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims description 78
- 239000004033 plastic Substances 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 230000005611 electricity Effects 0.000 abstract description 12
- 230000005540 biological transmission Effects 0.000 abstract description 6
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 25
- 239000000463 material Substances 0.000 description 18
- 239000010949 copper Substances 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 238000002360 preparation method Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- 229910007637 SnAg Inorganic materials 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ICXAPFWGVRTEKV-UHFFFAOYSA-N 2-[4-(1,3-benzoxazol-2-yl)phenyl]-1,3-benzoxazole Chemical compound C1=CC=C2OC(C3=CC=C(C=C3)C=3OC4=CC=CC=C4N=3)=NC2=C1 ICXAPFWGVRTEKV-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model discloses a TSV interconnect link structure and chip package structure, this TSV interconnect link structure includes: at least one pair of through conductive vias; at least one metal pad, each metal pad electrically connecting a pair of through conductive vias; at least one pair of micro-bumps electrically connected to the pair of through-conductive vias through a metal pad. The embodiment of the utility model provides a TSV interconnected link structure sets up a pair of electrically conductive through-hole and a pair of little lug of piercing through respectively in the both sides of metal pad, pierces through to realize the electricity through the metal pad between electrically conductive through-hole and the little lug and connects, when one of them pierces through electrically conductive through-hole or little lug and breaks down, the other normal transmission that pierces through electrically conductive through-hole or little lug and still can guarantee the signal of telecommunication. Therefore, the embodiment of the utility model provides a TSV interconnect link structure has improved the fault-tolerance and the yields of this structure, has improved signal transmission's reliability.
Description
Technical Field
The utility model relates to the field of semiconductor technology, concretely relates to TSV interconnect link structure and chip package structure
Background
Semiconductor devices are used in various electronic products such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material over a semiconductor substrate, and then patterning the various material layers using photolithography to form circuit components and elements thereon.
At present, semiconductor devices usually need to work continuously for a long time, so that the semiconductor devices need high-reliability 2.5D/3D packages such as CPUs, GPUs, FPGAs and HBMs during preparation, and simultaneously need high-reliability power supply and signal network design. However, when the semiconductor device adopts 2.5D/3D package with chip interconnection structure, the situation that the semiconductor device cannot normally operate due to the fact that electrical property cannot be transmitted often occurs.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a TSV interconnection link structure and a chip package structure, so as to solve the problem that a 2.5D/3D packaged semiconductor device in the prior art cannot operate normally.
The utility model provides a technical scheme as follows:
the embodiment of the utility model provides a first aspect provides a TSV interconnect link structure, and this structure includes: at least one pair of through conductive vias; at least one metal pad, each metal pad electrically connecting a pair of through conductive vias; at least one pair of micro-bumps electrically connected to the pair of through-conductive vias through a metal pad.
Further, the TSV interconnection link structure further includes: and a limiting structure arranged between the metal pad and the micro bump, wherein the limiting structure is not arranged above the penetrating conductive through hole, and the limiting structure is used for limiting the position of the micro bump.
The embodiment of the utility model provides a second aspect provides a chip package structure, and this package structure includes: a substrate; chip architecture, chip architecture includes at least two and passes through the utility model provides an in the first aspect and the first aspect any TSV interconnect link structure pile up the chip of connection, chip architecture passes through the utility model provides an in the first aspect and the first aspect any TSV interconnect link structure connect the substrate.
Furthermore, a plurality of pairs of penetrating conductive through holes are arranged in the substrate, and a plurality of metal bonding pads are arranged on the surface of the substrate; the chip structure includes the first chip structure who constitutes by at least one first chip, set up many pairs of through electrically conductive through holes in the first chip, the front and the back of first chip set up a plurality of metal pads respectively, set up a pair of little lug on every pad that the first chip is positive, pile up the connection through the little lug on first chip surface between the first chip in the first chip structure, the first chip structure is connected through the little lug on first chip surface the metal pad on the surface of the substrate.
Further, the chip structure further includes: the second chip openly sets up a plurality of metal pads and a plurality of to little lug, the second chip sets up first chip structure is kept away from one side of substrate, the second chip passes through the positive little lug of second chip and connects first chip structure.
Further, the chip package structure further includes: the base plate is arranged on one side, far away from the chip structure, of the substrate, and the base plate is electrically connected with the substrate.
Further, the chip package structure further includes: the underfill is arranged between the substrate and the substrate; the plastic package structure is arranged above the substrate and used for plastic packaging the substrate and the chip structure; the solder balls are arranged on one side of the base plate, which is far away from the substrate, and are used for leading out the electrical property in the chip structure.
The embodiment of the utility model provides a third aspect provides a preparation method of TSV interconnect link structure, and this method includes: forming at least one pair of through conductive vias in a substrate or chip, the through conductive vias exposing a surface of the substrate or chip; forming at least one metal pad on the surface of the substrate or the chip, wherein each metal pad is electrically connected with the penetrating conductive through hole; a pair of micro-bumps is formed over each metal pad, the pair of micro-bumps being electrically connected through one metal pad and a pair of through conductive vias.
Further, forming a pair of microbumps over each metal pad includes: forming a defining structure over each metal pad, the defining structure not being over a through conductive via; micro bumps are formed in the defining structures.
The utility model discloses technical scheme has following advantage:
the embodiment of the utility model provides a TSV interconnected link structure and preparation method thereof sets up a pair of electrically conductive through-hole and a pair of little lug of piercing through respectively through the both sides at the metal pad, pierces through to realize the electricity through the metal pad between electrically conductive through-hole and the little lug and connects, when one of them pierces through electrically conductive through-hole or little lug and breaks down, the other normal transmission that pierces through electrically conductive through-hole or little lug still can guarantee the signal of telecommunication. Therefore, the embodiment of the utility model provides a TSV interconnect link structure has improved the fault-tolerance and the yields of this structure, has improved signal transmission's reliability.
The embodiment of the utility model provides a chip packaging structure through the structure of introducing diplopore TSV and two little lug interconnections in chip stacked structure, sets up 2 and above electricity passageways promptly in packaging structure, and a plurality of electricity passageways can simultaneous working, and when 1 electricity passageway broke down, the normal operating of chip, encapsulation can still be ensured to other electricity passageways. Therefore, the embodiment of the utility model provides a chip packaging structure can promote signal, power transmission's reliability between chip and the chip to promote packaging system reliability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a TSV interconnection link structure in an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a TSV interconnect link structure in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a chip package structure in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a chip package structure according to another embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a chip package structure manufactured by the method for manufacturing a chip package structure according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a chip package structure manufactured by a method for manufacturing a chip package structure according to another embodiment of the present invention;
fig. 8 is a schematic structural diagram of a chip package structure manufactured by a method for manufacturing a chip package structure according to another embodiment of the present invention;
fig. 9 is a schematic structural diagram of a chip package structure manufactured by a method for manufacturing a chip package structure according to another embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.
The embodiment of the utility model provides a TSV interconnect link structure, as shown in FIG. 1, this TSV interconnect link structure includes: at least one pair of through conductive vias 10; at least one metal pad 20, each metal pad 20 electrically connecting a pair of through conductive vias 10; at least one pair of micro-bumps 30, the pair of micro-bumps 30 being electrically connected to the pair of through-conductive vias 10 through one metal pad 20.
The embodiment of the utility model provides a TSV interconnected link structure sets up a pair of electrically conductive through-hole and a pair of little lug of piercing through respectively in the both sides of metal pad, pierces through to realize the electricity through the metal pad between electrically conductive through-hole and the little lug and connects, when one of them pierces through electrically conductive through-hole or little lug and breaks down, the other normal transmission that pierces through electrically conductive through-hole or little lug and still can guarantee the signal of telecommunication. Therefore, the embodiment of the utility model provides a TSV interconnect link structure has improved the fault-tolerance and the yields of this structure, has improved signal transmission's reliability.
In one embodiment, the metal pad 20 may be selected from a copper material or an aluminum material, and when the copper material is selected, the preparation of the metal pad 20 may be achieved by using an electroplating process, and when the aluminum material is selected, the preparation of the metal pad 20 may be achieved by using a sputtering process. In addition, the metal pad 20 may be prepared by selecting other materials and other processes, which is not limited by the present invention.
In one embodiment, the microbump 30 may include a triple-layer structure composed of Cu, Ni, and SnAg, i.e., the lowermost layer may be a Cu material, the middle layer may be a Ni material, and the uppermost layer may be a SnAg material. Alternatively, the three-layer structure in the microbump 30 may be realized by using an electroplating process. In addition, the micro bumps 30 may be made of other materials and other processes, which is not limited by the present invention. Alternatively, the diameter of the micro bump 30 may be less than or equal to 50 micrometers, for example, 40 micrometers or 45 micrometers, etc.
In one embodiment, the TSV interconnect link structure further includes: and the limiting structure is arranged between the metal pad and the micro bump, is not arranged above the penetrating conductive through hole, and is used for limiting the position of the micro bump. In particular, the definition structure may be formed over the metal pad after the metal pad is formed, and then the micro bump may be formed at a position defined by the definition structure. Alternatively, the limited structure may be made of an organic material, specifically, PI (Polyimide) or PBO (Poly-p-phenylenebenzobisoxazole) may be selected as the material, and the limited structure is prepared by applying glue, exposing, and developing.
The embodiment of the utility model provides a still provide a preparation method of TSV interconnect link structure, as shown in FIG. 2, this preparation method includes following step:
step S101: at least one pair of penetrating conductive vias is formed in the substrate or chip, the penetrating conductive vias exposing both surfaces of the substrate or chip. Specifically, the process for preparing the through conductive via (TSV) may include marking a region to be etched with a photoresist, and then etching a via on one side of a substrate or a chip using a Deep Reactive Ion Etching (DRIE) method; sequentially depositing a silicon dioxide (SiO2) insulating layer by using a chemical deposition method, depositing titanium (Ti) as a barrier layer by using a physical vapor deposition method, and depositing copper (Cu) as a seed layer; selecting an electroplating method to fill the through hole with electroplating copper; the excess copper on the substrate or chip surface is removed using a Chemical Mechanical Polishing (CMP) process.
Step S102: forming at least one metal pad on the surface of the substrate or the chip, wherein each metal pad is electrically connected with the penetrating conductive through hole; specifically, the metal pad may be selected from a copper material or an aluminum material, and when the copper material is selected, the preparation of the metal pad may be achieved by using an electroplating process, and when the aluminum material is selected, the preparation of the metal pad may be achieved by using a sputtering process. Optionally, when a copper material is selected, copper on the surface of the substrate or the chip is not removed when the TSV through hole is formed, that is, extra copper electroplated in the TSV is directly used as a metal pad, or the extra copper is used as a metal pad after being subjected to patterning etching, so that the preparation process of the TSV interconnection link structure is reduced, and the cost is reduced.
Step S103: a pair of micro-bumps is formed over each metal pad, the pair of micro-bumps being electrically connected through one metal pad and a pair of through conductive vias.
Optionally, a defining structure may be formed over each metal pad prior to forming the micro-bumps, the defining structure not being over the through conductive vias; the limiting structure can be made of organic materials, specifically PI or PBO and other materials, by gluing, exposing and developing. Followed by the formation of micro-bumps in the defined structure.
The embodiment of the utility model provides a preparation method of TSV interconnected link structure sets up a pair of electrically conductive through-hole and a pair of little lug of piercing through respectively through the both sides at the metal pad, pierces through to realize the electricity through the metal pad between electrically conductive through-hole and the little lug and connects, when one of them pierces through electrically conductive through-hole or little lug and breaks down, the other normal transmission that pierces through electrically conductive through-hole or little lug still can guarantee the signal of telecommunication. Therefore, the embodiment of the utility model provides a TSV interconnect link structure has improved the fault-tolerance and the yields of this structure, has improved signal transmission's reliability.
The embodiment of the utility model provides a still provide a chip package structure, as shown in FIG. 3, this chip package structure includes: the chip structure 2 includes at least two chips stacked and connected through the TSV interconnection link structure described in the above embodiment, and the chip structure 2 is connected to the substrate 1 through the TSV interconnection link structure described in the above embodiment. Alternatively, the substrate 1 may be a silicon substrate.
The embodiment of the utility model provides a chip packaging structure through the structure of introducing diplopore TSV and two little lug interconnections in chip stacked structure, sets up 2 and above electricity passageways promptly in packaging structure, and a plurality of electricity passageways can simultaneous working, and when 1 electricity passageway broke down, the normal operating of chip, encapsulation can still be ensured to other electricity passageways. Therefore, the embodiment of the utility model provides a chip packaging structure can promote signal, power transmission's reliability between chip and the chip to promote packaging system reliability.
In an embodiment, when the chip structure and the substrate are interconnected by using the TSV interconnection link structure, a plurality of pairs of through conductive vias may be disposed in the substrate, and a plurality of metal pads are disposed on the surface of the substrate. Meanwhile, a first chip structure formed by at least one first chip can be arranged in the chip structure, a plurality of pairs of penetrating conductive through holes are formed in the first chip, a plurality of metal bonding pads are respectively arranged on the front surface and the back surface of the first chip, a pair of micro-bumps are arranged on each bonding pad on the front surface of the first chip, the first chips in the first chip structure are connected in a stacking mode through the micro-bumps on the surface of the first chip, and the first chip structure is connected with the metal bonding pads on the surface of the substrate through the micro-bumps on the surface of the first chip.
In one embodiment, the chip structure further includes: the second chip is arranged on one side, far away from the substrate, of the first chip structure and is connected with the first chip structure through the micro-bumps on the front side of the second chip. Specifically, the second chip may be disposed above the first chip structure and the substrate, that is, one side of the second chip away from the first chip structure may not be disposed with other structures, and therefore, the second chip may not be disposed with the through conductive via, and the back side of the second chip may not be disposed with the metal pad and the micro bump.
In an embodiment, as shown in fig. 4, the chip structure further includes: a base plate 3, the base plate 3 being arranged on a side of the substrate 1 remote from the chip structure 2, the base plate 3 and the substrate 1 being electrically connected. Alternatively, the substrate 3 may be an organic substrate, a micro bump may be disposed on a surface of the substrate 1 away from the first chip structure, and the substrate 1 may be soldered with the micro bump, so as to transmit electrical property and signals in the chip structure to the substrate.
In an embodiment, as shown in fig. 4, the chip structure further includes: the plastic packaging structure comprises underfill 4, a plastic packaging structure 5 and solder balls 6, wherein the underfill 4 is arranged between a base plate 3 and a substrate 1; the plastic package structure 5 is arranged above the substrate 3 and used for plastic packaging the substrate 1 and the chip structure 2; the solder balls 6 are disposed on a side of the substrate 3 away from the substrate 1 for electrical lead-out in the chip structure. Specifically, the underfill 4 may be disposed between the gap between the substrate 3 and the substrate 1, and the disposed underfill may protect the micro-bump between the substrate 1 and the substrate 3, and may also make the package structure more secure. Optionally, a non-conductive adhesive film may be further disposed on each chip in the chip structure to protect the microbump structures between the chips. Meanwhile, the arranged plastic package structure 5 can protect the chip structure and the substrate, and the solder balls 6 can lead out electrical property and signals in the package structure.
In one embodiment, as shown in fig. 5, the chip package structure can be prepared by the following steps:
step S201: a first chip is attached to a silicon substrate, the first chip is provided with a symmetrical bonding pad structure, each bonding pad on the front side of the first chip is provided with two micro-bumps, at least one pair of through-hole conductive vias (TSV) are arranged in the first chip and the substrate, the TSV in the first chip is connected with an upper bonding pad and a lower bonding pad, the TSV in the substrate is connected with a metal bonding pad on the front side of the substrate, and the first chip is connected with the metal bonding pad on the front side of the substrate through the micro-bumps on the bonding pad on the front side. The structure passing through step S201 is shown in fig. 3.
Step S202: and continuously mounting a second first chip and a third first chip, wherein the two first chips have the same structure as the first chip, and the three chips are connected through the micro-bumps on the front surfaces of the chips. The structure after step S202 is shown in fig. 6.
Step S203: and mounting the second chip on the third first chip, wherein the second chip is not provided with a TSV structure and a Pad structure on the back surface of the chip. Specifically, the front surface of the second chip is provided with a metal pad and a micro bump, and the second chip is connected with the metal pad on the back surface of the third first chip through the micro bump. The structure after step S203 is shown in fig. 7.
Step S204: and the silicon substrate and the four chips are pasted on the organic substrate, the back surface of the silicon substrate, which is far away from the chips, is provided with a micro-bump connected with the TSV, the micro-bump on the back surface of the silicon substrate is welded with the organic substrate, and meanwhile underfill is filled between gaps of the silicon substrate and the substrate. In addition, a non-conductive film (NCF) may be filled between the four chips to protect the micro bump structure between the chips. The structure after step S204 is shown in fig. 8.
Step S205: and forming a plastic packaging layer on the organic substrate, wherein the plastic packaging layer wraps the four chips and the substrate and is used for protecting the chips and the silicon substrate. The structure passing through step S205 is shown in fig. 9.
Step S206: and planting balls on the surface of the organic substrate far away from the substrate to finish the packaging of the chip. The structure passing through step S201 is shown in fig. 4.
Although the present invention has been described in detail with respect to the exemplary embodiments and the advantages thereof, those skilled in the art will appreciate that various changes, substitutions and alterations can be made to the embodiments without departing from the spirit of the invention and the scope of the invention as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while maintaining the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (7)
1. A TSV interconnect link structure, comprising:
at least one pair of through conductive vias;
at least one metal pad, each metal pad electrically connecting a pair of through conductive vias;
at least one pair of micro-bumps electrically connected to the pair of through-conductive vias through a metal pad.
2. The TSV interconnect link structure of claim 1, further comprising: and a limiting structure arranged between the metal pad and the micro bump, wherein the limiting structure is not arranged above the penetrating conductive through hole, and the limiting structure is used for limiting the position of the micro bump.
3. A chip package structure, comprising:
a substrate;
a chip structure comprising at least two chips stacked and connected by the TSV interconnect link structure of claim 1 or 2, the chip structure being connected to the substrate by the TSV interconnect link structure of claim 1 or 2.
4. The chip package structure according to claim 3,
a plurality of pairs of penetrating conductive through holes are arranged in the substrate, and a plurality of metal bonding pads are arranged on the surface of the substrate;
the chip structure includes the first chip structure who constitutes by at least one first chip, set up many pairs of through electrically conductive through holes in the first chip, the front and the back of first chip set up a plurality of metal pads respectively, set up a pair of little lug on every pad that the first chip is positive, pile up the connection through the little lug on first chip surface between the first chip in the first chip structure, the first chip structure is connected through the little lug on first chip surface the metal pad on the surface of the substrate.
5. The chip package structure according to claim 4,
the chip structure further includes: the second chip openly sets up a plurality of metal pads and a plurality of to little lug, the second chip sets up first chip structure is kept away from one side of substrate, the second chip passes through the positive little lug of second chip and connects first chip structure.
6. The chip package structure according to claim 4, further comprising: the base plate is arranged on one side, far away from the chip structure, of the substrate, and the base plate is electrically connected with the substrate.
7. The chip package structure according to claim 6, further comprising: underfill, a plastic package structure and solder balls,
the underfill is arranged between the base plate and the substrate;
the plastic package structure is arranged above the substrate and used for plastic packaging the substrate and the chip structure;
the solder balls are arranged on one side of the base plate, which is far away from the substrate, and are used for leading out the electrical property in the chip structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020845588.1U CN211700266U (en) | 2020-05-19 | 2020-05-19 | TSV (through silicon via) interconnection link structure and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020845588.1U CN211700266U (en) | 2020-05-19 | 2020-05-19 | TSV (through silicon via) interconnection link structure and chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211700266U true CN211700266U (en) | 2020-10-16 |
Family
ID=72784490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020845588.1U Active CN211700266U (en) | 2020-05-19 | 2020-05-19 | TSV (through silicon via) interconnection link structure and chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211700266U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477608A (en) * | 2020-05-19 | 2020-07-31 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure, TSV (through silicon Via) interconnection link structure and preparation method thereof |
-
2020
- 2020-05-19 CN CN202020845588.1U patent/CN211700266U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477608A (en) * | 2020-05-19 | 2020-07-31 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure, TSV (through silicon Via) interconnection link structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11996401B2 (en) | Packaged die and RDL with bonding structures therebetween | |
| KR102585621B1 (en) | Integrated circuit package and method | |
| KR102193505B1 (en) | Semiconductor packages and methods of forming same | |
| KR101124568B1 (en) | Semiconductor chip and stack chip semiconductor package | |
| CN101542726B (en) | Semiconductor chip with through-silicon vias and side pads | |
| TWI556400B (en) | Stacked fan-out semiconductor chip | |
| TWI573224B (en) | Stacked die integrated circuit | |
| KR101501739B1 (en) | Method of Fabricating Semiconductor Packages | |
| CN110299329A (en) | A kind of encapsulating structure and preparation method thereof, electronic equipment | |
| JP2022021336A (en) | Semiconductor package and its manufacturing method | |
| TWI578421B (en) | Stackable semiconductor package and the method for manufacturing the same | |
| CN112687670B (en) | Integrated circuit structure and forming method thereof | |
| CN106328632A (en) | Electronic package and manufacturing method thereof | |
| CN103794569A (en) | Package structure and method for fabricating the same | |
| WO2021081855A1 (en) | Chip package on package structure and packaging method therefor, and electronic device | |
| CN114765110A (en) | Package structure and method for manufacturing the same | |
| CN115527972A (en) | High-density interconnection three-dimensional integrated device packaging structure and manufacturing method thereof | |
| CN110634848A (en) | Multi-chip stacking packaging structure and manufacturing method thereof | |
| CN110634832A (en) | Packaging structure based on through silicon via adapter plate and manufacturing method thereof | |
| CN111477608A (en) | Chip packaging structure, TSV (through silicon Via) interconnection link structure and preparation method thereof | |
| CN211700266U (en) | TSV (through silicon via) interconnection link structure and chip packaging structure | |
| CN115939117A (en) | Encapsulation structure, preparation method of encapsulation structure and electronic device | |
| US8384215B2 (en) | Wafer level molding structure | |
| CN118588688B (en) | Back-to-back three-dimensional stacked fan-out packaging structure and preparation method thereof, back-to-back three-dimensional stacked fan-out packaging module and preparation method thereof | |
| CN114203564A (en) | A packaging method and packaging structure of a multi-layer stacked high-bandwidth memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |