CN110634832A - Packaging structure based on through silicon via adapter plate and manufacturing method thereof - Google Patents
Packaging structure based on through silicon via adapter plate and manufacturing method thereof Download PDFInfo
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- CN110634832A CN110634832A CN201910809269.7A CN201910809269A CN110634832A CN 110634832 A CN110634832 A CN 110634832A CN 201910809269 A CN201910809269 A CN 201910809269A CN 110634832 A CN110634832 A CN 110634832A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a packaging structure based on a through silicon via adapter plate and a manufacturing method thereof. The above-mentioned packaging structure based on through-silicon-via keysets includes: the adapter plate is provided with a first silicon through hole and a second silicon through hole which penetrate through the front surface and the back surface of the adapter plate; the first chip is arranged on one side, close to the front side, of the adapter plate and is electrically connected with the first through silicon via; the first plastic package body is used for encapsulating the first chip, a first conductive interconnection structure is arranged in the first plastic package body, and the first conductive interconnection structure is electrically connected with the second silicon through hole; the second chip is arranged on one side, away from the first silicon through hole, of the first chip and is electrically connected with the first conductive interconnection structure; and the rewiring structure is arranged on one side of the adapter plate close to the back surface and is electrically connected with the first silicon through hole and the second silicon through hole respectively. The packaging density is high, the packaging size is more compact, the number of the I/O of the output terminals is large, the packaging structure is suitable for packaging chips with various sizes, the flexibility of chip position arrangement is high, the utilization rate of the silicon through holes is high, the packaging cost is reduced, and the packaging structure is suitable for wide popularization and application.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure based on a through silicon via adapter plate and a manufacturing method thereof.
Background
With the increasing requirements for high transmission, high bandwidth, low power consumption and low delay of electronic products, the demand for multi-chip packaging technology is also increasing, and new packaging technologies are emerging, which not only realize high-density packaging of multiple chips, but also require more compact packaging size and more output terminal I/O number, and the packaging technology related to the through-silicon-via adapter board is one of the technologies for meeting the requirements. Tsv (through silicon via) technology is an abbreviation of through silicon via technology, generally referred to as "through silicon via" technology, and is a new technical solution for implementing interconnection of stacked chips in three-dimensional integrated circuits, and is called as the 4 th generation packaging technology after wire bonding, tape bonding (TAB), and Flip Chip (FC). The TSV technology not only can realize high integration, but also can meet the product requirements for realizing the characteristics of high performance, low delay, high frequency, large bandwidth and the like.
Chinese patent document (CN105428331A) discloses a packaging structure based on through-silicon via keysets, including the through-silicon via keysets, flip chip, underfill, plastic-encapsulated material and BGA solder ball, flip chip flip-chip welds the front at the through-silicon via keysets, and flip chip and through-silicon via keysets are sealed to the plastic-encapsulated material, and expose the back of through-silicon via keysets, the BGA solder ball is planted at the through-silicon via keysets back, underfill is glued and is located between flip chip and the through-silicon via keysets. The packaging structure combines fan-out and adapter plate technologies to realize system-level packaging, so that a plurality of bare chips or a plurality of groups of stacked chip assemblies are assembled on one silicon through hole adapter plate to form a two-dimensional packaging structure, the requirement of multi-chip three-dimensional packaging is not met, the packaging density is low, the packaging of chips with different sizes is limited, the utilization rate of silicon through holes on the silicon through hole adapter plate is low, and the packaging cost is not reduced.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects that the packaging structure based on the silicon through hole adapter plate in the prior art does not meet the requirements of multi-chip three-dimensional packaging, has low packaging density, is not suitable for packaging chips with various sizes and is not beneficial to reducing the packaging cost, thereby providing the packaging structure based on the silicon through hole adapter plate and the manufacturing method thereof.
The invention provides a packaging structure based on a through silicon via adapter plate, which comprises:
the adapter plate is provided with a first silicon through hole and a second silicon through hole which penetrate through the front surface and the back surface of the adapter plate;
the first chip is arranged on one side, close to the front surface, of the adapter plate and is electrically connected with the first through silicon via;
the first plastic package body encapsulates the first chip, a first conductive interconnection structure is arranged in the first plastic package body, and the first conductive interconnection structure is electrically connected with the second silicon through hole;
the second chip is arranged on one side, away from the first through silicon via, of the first chip and is electrically connected with the first conductive interconnection structure;
and the rewiring structure is arranged on one side of the adapter plate close to the back surface and is respectively and electrically connected with the first silicon through hole and the second silicon through hole.
Further, the first conductive interconnect structure includes:
the conductive piece penetrates through the front surface and the back surface of the first plastic package body and comprises a conductive column or a conductive hole;
and one end of the first transfer line is connected with the conductive piece, and the other end of the first transfer line is connected with the second through silicon via.
Furthermore, the rewiring structure comprises a second transfer line and an external solder ball, wherein one end of the second transfer line is connected with the first through silicon via or the second through silicon via, and the other end of the second transfer line is connected with the external solder ball.
Further, the first chip is electrically connected with the first through silicon via through a second conductive interconnection structure, and the second conductive interconnection structure is encapsulated in the first plastic package.
Further, the package structure based on the through silicon via interposer further includes a second plastic package body encapsulating the second chip.
Further, the second chip is electrically connected with the first conductive interconnection structure through a third conductive interconnection structure, and the third conductive interconnection structure is encapsulated in the second plastic package.
Further, one surface of the first chip, which is far away from the first through silicon via, is flush with the front surface of the first plastic package body.
The second aspect of the present invention provides a method for manufacturing the package structure based on the through silicon via interposer, including:
providing an adapter plate, wherein a first silicon through hole and a second silicon through hole which penetrate through the front surface and the back surface of the adapter plate are formed in the adapter plate;
placing a first chip on one side of the adapter plate close to the front surface, and electrically connecting the front surface of the first chip with the first through silicon via;
manufacturing a first plastic package body for encapsulating the first chip and a first conductive interconnection structure encapsulated in the first plastic package body, so that the first conductive interconnection structure is electrically connected with the second through silicon via;
placing a second chip on one side of the first chip, which is far away from the first through silicon via, and electrically connecting the front surface of the second chip with the first conductive interconnection structure;
and manufacturing a rewiring structure on one side of the adapter plate close to the back surface, so that the rewiring structure is electrically connected with the first silicon through hole and the second silicon through hole respectively.
Further, the method for manufacturing the first plastic package body and the first conductive interconnection structure comprises the following steps:
manufacturing a first transfer line on the second through silicon via, so that one end of the first transfer line is electrically connected with the second through silicon via, the other end of the first transfer line is connected with a conductive piece, and manufacturing a first plastic package body to encapsulate the first chip, the first transfer line and the conductive piece; or
And manufacturing a first transfer line on the second silicon through hole, electrically connecting one end of the first transfer line with the second silicon through hole, manufacturing a first plastic package body to encapsulate the first chip and the first transfer line, manufacturing a through hole on the first plastic package body to expose the other end of the first transfer line, and forming a conductive piece in the through hole.
Further, the manufacturing method of the packaging structure based on the through silicon via interposer further includes:
and manufacturing a second plastic package body to encapsulate the second chip.
The technical scheme of the invention has the following advantages:
1. according to the packaging structure based on the through silicon via adapter plate, the first through silicon via and the second through silicon via on the adapter plate are utilized, the first chip and the second chip are stacked up and down, the first chip is connected with the first through silicon via on the adapter plate, the second chip is connected with the second through silicon via through a first conductive interconnection structure in the first plastic package body, and the redistribution structure is arranged to be electrically connected with the first through silicon via and the second through silicon via respectively, so that three-dimensional integrated packaging of the chip based on only one through silicon via adapter plate is realized, the packaging density is high, the packaging size is more compact, more I/O (input/output) numbers are provided, the packaging structure is suitable for packaging chips with various sizes, the flexibility of chip position arrangement is high, the utilization rate of the through silicon vias on the through silicon via adapter plate is high, the packaging cost is favorably reduced, and the packaging structure is suitable for wide popularization and.
2. According to the packaging structure based on the through silicon via adapter plate, the second chip is connected with the rewiring structure through the conductive columns or the conductive holes penetrating through the first plastic package body and the first transfer lines, and the reliability of the connection relation is improved due to the conductive columns or the conductive holes.
3. According to the packaging structure based on the through silicon via adapter plate, the front surface of the first plastic package body can be flush with the surface, far away from the first through silicon via, of the first chip through planarization processes such as mechanical grinding, chemical etching and UV irradiation, so that the overall thickness of the packaging structure can be effectively reduced, and the size of an electronic product can be reduced.
4. The preparation method of the packaging structure based on the silicon through hole adapter plate reasonably utilizes the silicon through hole on the adapter plate to realize multi-chip three-dimensional integrated packaging, is simple and convenient to operate and easy to realize, and has wide packaging application prospect; the processed conductive piece and the first transfer line are interconnected and then encapsulated or the first plastic package piece is manufactured and then the through hole is opened and the conductive metal is filled, so that the manufactured first conductive interconnection structure is high in reliability and stable in connection.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a package structure based on a through silicon via interposer in an embodiment of the present application;
fig. 2 is a schematic flow chart illustrating a method for manufacturing a package structure based on a through silicon via interposer according to an embodiment of the present invention.
Description of reference numerals:
1-an adapter plate; 2-a first through-silicon-via; 3-a second through-silicon-via; 4-a first chip; 5-a first plastic package body; 6-a second chip; 7-a conductive member; 8-a first transfer line; 9-a first welded structure; 10-a third transfer line; 11-a second plastic package body; 12-a second welded structure; 13-a fourth transfer line; 14-a second transfer line; 15-external solder balls; 16-PCB board.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In a first aspect, an embodiment of the present invention provides a package structure based on a through silicon via interposer.
The above-mentioned packaging structure based on through-silicon-via keysets includes:
the adapter plate 1 is provided with a first silicon through hole 2 and a second silicon through hole 3 which penetrate through the front surface and the back surface of the adapter plate;
the first chip 4 is arranged on one side, close to the front surface, of the adapter plate 1 and is electrically connected with the first through silicon via 2;
the first plastic package body 5 encapsulates the first chip 4, a first conductive interconnection structure is arranged in the first plastic package body 5, and the first conductive interconnection structure is electrically connected with the second through silicon via 3;
the second chip 6 is arranged on one side, away from the first through silicon via 2, of the first chip 4 and is electrically connected with the first conductive interconnection structure;
and the rewiring structure is arranged on one side of the adapter plate 1 close to the back surface and is electrically connected with the first silicon through hole 2 and the second silicon through hole 3 respectively.
The packaging structure based on the silicon through hole adapter plate provided by the embodiment of the invention utilizes the first silicon through hole 2 and the second silicon through hole 3 on the adapter plate 1, the first chip 4 and the second chip 6 are stacked up and down, the first chip 4 is connected with the first silicon through hole 2 on the adapter plate 1, the second chip 6 is connected with the second silicon through hole 3 through the first conductive interconnection structure in the first plastic package body 5, and the heavy wiring structure is arranged to be electrically connected with the first silicon through hole 2 and the second silicon through hole 3 respectively, so that the three-dimensional integrated packaging of the chip based on only one silicon through hole adapter plate is realized, the packaging density is high, the packaging size is more compact, more output terminals I/O quantity is provided, the chip packaging structure is suitable for the packaging of chips with various sizes, the flexibility of chip position arrangement is high, and the utilization rate of the silicon through holes on the silicon through hole adapter plate is high, the packaging cost is favorably reduced, and the silicon through hole adapter plate is suitable for wide popularization and application.
The adapter plate 1 may be made of silicon, glass, or the like, and the first through-silicon via 2 and the second through-silicon via 3 formed on the adapter plate 1 penetrate through the adapter plate 1 to form a TSV array. The method for manufacturing the through silicon via interposer belongs to the prior art, and is not described herein. In the embodiment, a through silicon via adapter plate finished product can be directly selected, or prepared and used according to the requirement. The filling material in the first through silicon via 2 and the second through silicon via 3 is a conductive metal, typically copper, and may also be other metals such as aluminum, tungsten, titanium, and the like. In addition, the first through-silicon via 2 and the second through-silicon via 3 may be the same or different in structure or material, and the "first" and "second" are only used to distinguish the through-silicon via electrically connected to the first chip 4 and the through-silicon via electrically connected to the second chip 6.
The present embodiment does not limit the type and structure of the first chip 4 and the second chip 6, for example, the first chip 4 and the second chip 6 may be chips themselves, circuit devices, or packaging structures of chips and their related circuits, may be a single bare chip or a chip assembly formed by stacking a plurality of bare chips, and the like, which are all within the scope of the claimed invention.
The first plastic package body 5 encapsulates the first chip 4, and the first plastic package body 5 is made of an insulating material, which may be an organic material or an inorganic material with a photolithography capability, such as a phenolic resin or an epoxy resin.
Preferably, as the embodiment, the front surface of the first plastic package body 5 is flush with the surface of the first chip 4 far away from the first through silicon via 2 by planarization process methods such as mechanical grinding, chemical etching, UV irradiation, and the like, so that the overall thickness of the package structure can be effectively reduced, and the volume of the electronic product can be reduced.
The first conductive interconnection structure is located in the first plastic package body 5 and is used for connecting the second chip 6 and the redistribution structure, and any conductive structure capable of achieving the above functions is within the scope of the present invention. As a preference of this embodiment, the first conductive interconnection structure includes: the conductive piece 7 penetrates through the front surface and the back surface of the first plastic package body 5, and the conductive piece 7 comprises a conductive column or a conductive hole; and one end of the first transfer line 8 is connected with the conductive member 7, and the other end is connected with the second through silicon via 3. The conductive device 7 may be formed with a through hole in the first plastic package body 5 by photolithography, chemical etching, PVD, CVD, electroplating, or the like, and filled with a conductive metal to form a conductive pillar or a conductive hole, or the conductive pillar or the conductive hole may be formed first and then encapsulated with an insulating material, and the end of the conductive device 7 is exposed by planarization processing through mechanical polishing, chemical etching, UV irradiation, or the like. The material of the first transfer line 8 may be copper, aluminum, nickel, gold, tin, silver, and the like, and may be manufactured by electroplating, chemical plating, PVD, CVD, and the like. The second chip 6 is connected with the rewiring structure by arranging the conductive columns or the conductive holes penetrating through the first plastic package body 5 and the first transfer line 8, and the reliability of the connection relation is improved by the conductive columns or the conductive hole structure.
The first chip 4 and the first through silicon via 2 are electrically connected through a second conductive interconnection structure, and the second conductive interconnection structure is encapsulated in the first plastic package body 5. The front surface of the first chip 4 may be disposed toward or away from one side of the first through silicon via 2, preferably, the front surface of the first chip 4 is disposed toward one side of the first through silicon via 2, and is electrically connected to the first through silicon via 2 through the first soldering structure 9 and the third transfer line 10, the first soldering structure 9 may be a bump structure or a metal direct bonding (only the bump bonding structure is shown in the figure), such as a copper-copper bonding structure, and the first soldering structure 9 may be made of a metal such as copper, nickel, tin, silver, gold, etc.; one end of the third transfer line 10 is connected with the first welding structure 9, the other end is connected with the first through silicon via 2, the third transfer line 10 can be made of copper, aluminum, nickel, gold, tin, silver and other metals and can be manufactured by adopting the processes of electroplating, chemical plating, PVD, CVD and the like.
Preferably, the package structure based on the through silicon via interposer further includes a second molding compound 11 encapsulating the second chip 6.
The front surface of the second chip 6 may be disposed toward or away from a side of the second through-silicon-via 3. Preferably, the front surface of the second chip 6 is disposed toward one side of the second through silicon via 3, the second chip 6 is electrically connected to the first conductive interconnection structure through a third conductive interconnection structure, and the third conductive interconnection structure is encapsulated in the second plastic package body 11. Specifically, the third conductive interconnection structure includes a second soldering structure 12 and a fourth transfer line 13, the front surface of the second chip 6 is electrically connected to the first conductive interconnection structure through the second soldering structure 12 and the fourth transfer line 13, the second soldering structure 12 may be a bump structure or a metal direct bonding (only the bump bonding structure is shown in the figure), such as a copper-copper bonding structure, and the second soldering structure 12 may be made of a metal such as copper, nickel, tin, silver, gold, or the like; one end of the fourth transfer line 13 is connected with the second welding structure 12, the other end is connected with the first conductive interconnection structure, the fourth transfer line 13 can be made of copper, aluminum, nickel, gold, tin, silver and other metals and can be manufactured by adopting electroplating, chemical plating, PVD, CVD and other processes.
The rewiring structure, that is, a structure for conducting signals between the first chip 4 and the second chip 6 and other devices (such as the PCB 16), realizes fan-out packaging of the first chip 4 and the second chip 6. Preferably, the rewiring structure includes a second transfer line 14 and an external solder ball 15, one end of the second transfer line 14 is connected to the first through silicon via 2 or the second through silicon via 3, and the other end is connected to the external solder ball 15. Specifically, the material of the second transfer line 14 is generally copper, and may also be other metals such as aluminum, tungsten, titanium, etc., the external solder ball 15 is a bump structure, and the material thereof may be tin, nickel, gold, or other metals, and the external solder ball 15 is used for electrically connecting with other devices, such as a PCB 16 (printed circuit board).
In a second aspect, the present embodiment provides a method for manufacturing the package structure based on the through silicon via interposer.
The manufacturing method comprises steps S1-S5:
step S1, providing an interposer 1, wherein the interposer 1 is provided with a first through silicon via 2 and a second through silicon via 3 penetrating the front and back of the interposer 1.
The adapter plate 1 provided with the first through silicon via 2 and the second through silicon via 3 is manufactured by a method for manufacturing a through silicon via adapter plate in the prior art. To facilitate the subsequent manufacturing process, the interposer 1 is attached to the wafer by an adhesive layer.
In step S2, a first chip 4 is placed on the interposer 1 near the front side, and the front side of the first chip 4 is electrically connected to the first through-silicon-via 2.
Preferably, in this embodiment, the front surface of the first chip 4 is disposed toward the interposer 1, the third transfer line 10 is first formed on the first through silicon via 2, and the third transfer line is formed by electroplating, chemical plating, PVD, CVD, or other processes, and then the first bonding structure 9 is formed on the third transfer line 10, and bump bonding or direct metal bonding is performed.
Step S3, a first plastic package body 5 encapsulating the first chip 4 and a first conductive interconnection structure encapsulated in the first plastic package body 5 are fabricated, so that the first conductive interconnection structure is electrically connected to the second through silicon via 3.
As an optional implementation manner of this embodiment, the method for manufacturing the first plastic package body 5 and the first conductive interconnection structure includes:
and manufacturing a first transfer line 8 on the second through silicon via 3, electrically connecting one end of the first transfer line 8 with the second through silicon via 3, connecting a conductive member 7 at the other end of the first transfer line 8, and manufacturing a first plastic package body 5 to encapsulate the first chip 4, the first transfer line 8 and the conductive member 7.
The first transfer line 8 is manufactured by adopting the processes of electroplating, chemical plating, PVD, CVD and the like. The conductive member 7 is a fabricated conductive column or conductive hole (hollow conductive column). Preferably, one end of the conductive member 7 away from the second through-silicon-via 3 is controlled to be flush with the back surface of the first chip 4, and the front surface of the first plastic package body 5 is made flush with the back surface of the first chip 4 and one end of the conductive member 7 away from the second through-silicon-via 3 by using mechanical grinding, chemical etching, UV irradiation and other process methods, so as to reduce the thickness of the package structure.
As another optional implementation manner of this embodiment, the method for manufacturing the first plastic package body 5 and the first conductive interconnection structure includes:
and manufacturing a first transfer line 8 on the second through silicon via 3, electrically connecting one end of the first transfer line 8 with the second through silicon via 3, manufacturing a first plastic package body 5 to encapsulate the first chip 4 and the first transfer line 8, manufacturing a through hole on the first plastic package body 5 to expose the other end of the first transfer line 8, and forming a conductive member 7 in the through hole.
The first transfer line 8 is manufactured by adopting the processes of electroplating, chemical plating, PVD, CVD and the like. Through holes are manufactured on the first plastic package body 5 through photoetching or chemical corrosion, PVD, CVD, electroplating and other processes, and conductive columns or conductive holes are formed through conductive metal filling. Preferably, the front surface of the first plastic package body 5 is flush with the back surface of the first chip 4 and an end of the conductive member 7 away from the second through-silicon-via 3 by a mechanical grinding, a chemical etching, a UV irradiation, or the like, so as to reduce the thickness of the package structure.
Step S4, placing the second chip 6 on the side of the first chip 4 away from the first through silicon via 2, and electrically connecting the front side of the second chip 6 with the first conductive interconnection structure.
Preferably, in this embodiment, a fourth transfer line 13 is formed at an end of the first conductive interconnection structure away from the second through-silicon-via 3, a second bonding structure 12 is formed at an end of the fourth transfer line 13 not connected to the first conductive interconnection structure, and a pad on the front surface of the second chip 6 is connected to the second bonding structure 12. The fourth transfer line 13 can be manufactured by electroplating, chemical plating, PVD, CVD, or other processes, and the second soldering structure 12 is manufactured by bump bonding or direct metal bonding.
As a preferred embodiment, after the front surface of the second chip 6 is electrically connected to the first conductive interconnection structure, the second plastic package body 11 is manufactured to encapsulate the second chip 6, the second soldering structure 12 and the fourth transfer line 13, and the front surface of the second plastic package body 11 and the back surface of the second chip 6 may be leveled by using processes such as mechanical grinding, chemical etching, UV irradiation and the like to reduce the thickness of the package structure.
In step S5, a redistribution structure is formed on the side of the interposer 1 close to the back surface, so that the redistribution structure is electrically connected to the first through-silicon via 2 and the second through-silicon via 3, respectively.
The adhesive layer and the carrier are peeled off by a debonding process, and the package is inverted for preparation of the rewiring structure. And manufacturing a second transfer line 14 at one end of the first through silicon via 2 or the second through silicon via 3, which is far away from the first chip 4 and the second chip 6, and manufacturing an external solder ball 15 on the second transfer line 14. The second transfer line 14 can be manufactured by electroplating, chemical plating, PVD, CVD, or the like, and the external solder ball 15 is manufactured by electroplating or ball-planting. Further, the external solder balls 15 may be soldered to the PCB board 16 for electronic device fabrication.
It should be emphasized that the number of the first chips 4 is not limited to two as shown in the figures, the second chip 6 is not limited to one as shown in the figures, and in addition, other chips and the like can be stacked above the second chip 6, which can be selected and matched according to practical situations, and the invention is not limited thereto.
The preparation method of the packaging structure based on the silicon through hole adapter plate provided by the embodiment reasonably utilizes the silicon through hole on the adapter plate 1 to realize multi-chip three-dimensional integrated packaging, is simple and convenient to operate and easy to realize, and has a wide packaging application prospect; the processed conductive piece 7 and the first transfer line 8 are interconnected and then encapsulated or the first plastic package piece is manufactured and then a through hole is formed and conductive metal is filled, so that the manufactured first conductive interconnection structure is high in reliability and stable in connection.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. The utility model provides a packaging structure based on through-silicon-via keysets which characterized in that includes:
the adapter plate (1) is provided with a first silicon through hole (2) and a second silicon through hole (3) which penetrate through the front surface and the back surface of the adapter plate;
the first chip (4) is arranged on one side, close to the front surface, of the adapter plate (1) and is electrically connected with the first through silicon via (2);
the first plastic package body (5) encapsulates the first chip (4), a first conductive interconnection structure is arranged in the first plastic package body (5), and the first conductive interconnection structure is electrically connected with the second through silicon via (3);
the second chip (6) is arranged on one side, away from the first through silicon via (2), of the first chip (4) and is electrically connected with the first conductive interconnection structure;
and the rewiring structure is arranged on one side, close to the back surface, of the adapter plate (1) and is electrically connected with the first silicon through hole (2) and the second silicon through hole (3) respectively.
2. The through-silicon-via interposer-based package structure of claim 1, wherein the first conductive interconnect structure comprises:
the conductive piece (7) penetrates through the front surface and the back surface of the first plastic package body (5), and the conductive piece (7) comprises a conductive column or a conductive hole;
and one end of the first transfer line (8) is connected with the conductive piece (7), and the other end of the first transfer line is connected with the second through silicon via (3).
3. The through silicon via interposer-based package structure of claim 1 or 2, wherein the redistribution structure comprises a second transfer line (14) and an external solder ball (15), one end of the second transfer line (14) is connected to the first through silicon via (2) or the second through silicon via (3), and the other end is connected to the external solder ball (15).
4. The through-silicon-via interposer-based package structure of any one of claims 1 to 3, wherein the first chip (4) is electrically connected to the first through silicon via (2) through a second conductive interconnection structure, and the second conductive interconnection structure is encapsulated in the first plastic package body (5).
5. The through-silicon-via interposer-based package structure of any one of claims 1-4, further comprising a second molding compound (11) encapsulating the second chip (6).
6. The through silicon via interposer-based package structure of claim 5, wherein the second chip (6) is electrically connected to the first conductive interconnect structure through a third conductive interconnect structure, the third conductive interconnect structure being encapsulated within the second plastic package body (11).
7. The through silicon via interposer-based package structure of any one of claims 1 to 6, wherein a surface of the first chip (4) away from the first through silicon via (2) is flush with a front surface of the first molding compound (5).
8. A method for manufacturing a through-silicon-via interposer-based package structure as claimed in any one of claims 1 to 7, comprising:
providing an adapter plate (1), wherein a first silicon through hole (2) and a second silicon through hole (3) which penetrate through the front surface and the back surface of the adapter plate (1) are formed in the adapter plate (1);
placing a first chip (4) on one side of the adapter plate (1) close to the front surface, and electrically connecting the front surface of the first chip (4) with the first through silicon via (2);
manufacturing a first plastic package body (5) for encapsulating the first chip (4) and a first conductive interconnection structure encapsulated in the first plastic package body (5), so that the first conductive interconnection structure is electrically connected with the second through silicon via (3);
placing a second chip (6) on one side of the first chip (4) away from the first through silicon via (2), and electrically connecting the front surface of the second chip (6) with the first conductive interconnection structure;
and manufacturing a rewiring structure on one side of the adapter plate 1 close to the back surface, so that the rewiring structure is electrically connected with the first silicon through hole (2) and the second silicon through hole (3) respectively.
9. The method for manufacturing a through silicon via interposer-based package structure according to claim 8, wherein the method for manufacturing the first molding compound (5) and the first conductive interconnection structure comprises:
manufacturing a first transfer line (8) on the second through silicon via (3), electrically connecting one end of the first transfer line (8) with the second through silicon via (3), connecting a conductive member (7) at the other end of the first transfer line (8), and manufacturing a first plastic package body (5) to encapsulate the first chip (4), the first transfer line (8) and the conductive member (7); or
And manufacturing a first transfer line (8) on the second through silicon via (3), electrically connecting one end of the first transfer line (8) with the second through silicon via (3), manufacturing a first plastic package body (5) to encapsulate the first chip (4) and the first transfer line (8), manufacturing a through hole on the first plastic package body (5) to expose the other end of the first transfer line (8), and forming a conductive piece (7) in the through hole.
10. The method for manufacturing the through silicon via interposer-based package structure according to claim 8 or 9, further comprising:
and manufacturing a second plastic package body (11) to encapsulate the second chip (6).
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| CN111668120A (en) * | 2020-06-01 | 2020-09-15 | 杭州晶通科技有限公司 | Fan-out package structure of high-density chip and preparation method thereof |
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| CN114334946A (en) * | 2021-12-09 | 2022-04-12 | 江苏长电科技股份有限公司 | Package structure and manufacturing method |
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Application publication date: 20191231 |