CN211529113U

CN211529113U - High-performance server operation board power supply circuit

Info

Publication number: CN211529113U
Application number: CN202020054712.2U
Authority: CN
Inventors: 沈新民
Original assignee: Shenzhen Zhichen Information Technology Co ltd
Current assignee: Shenzhen Zhichen Information Technology Co ltd
Priority date: 2020-01-12
Filing date: 2020-01-12
Publication date: 2020-09-18
Anticipated expiration: 2030-01-12

Abstract

The utility model discloses a high performance server operation board supply circuit, include: the Boost circuit is externally connected with power supply and used for boosting the power supply; the input end of the Buck circuit is coupled to the output end of the Boost circuit, the Buck circuit is used for reducing voltage, the output end of the Buck circuit is coupled to the input end of the LDO circuit, the LDO circuit is connected to the IC chip and used for providing stable voltage for an I/O pin corresponding to the IC chip, and each IC chip is correspondingly provided with one LDO circuit. The utility model has novel concept, reasonable design and convenient use, and can keep stable ground voltage input by combining the voltage stabilizer and the divider resistor in several levels of IC chips close to Buck through combining the Boost circuit and the Buck circuit to supply power for the IC chips used for calculation, especially aiming at the serial connection of a plurality of IC chips; meanwhile, because the Boost circuit and the Buck circuit are provided with feedback circuits, the output of the Boost circuit and the Buck circuit is very quick and stable.

Description

High-performance server operation board power supply circuit

Technical Field

The utility model relates to an operation board technical field, in particular to high performance server operation board supply circuit.

Background

In the hardware technology involved in the block chain, the hardware of the computing board is involved.

For the force calculation board, the circuit design has two main points, namely a power supply mode and cascade connection of signals between chips. The power supply generally adopts a series power supply mode, and the input voltage of the series chips is equally divided as the core voltage of the current stage. Signals between chips need to be transmitted through chip I/O, the I/O level generally uses 1.8V, the level is generated by using the LDO, the input voltage of the LDO is provided by using a voltage which is higher than the level of the LDO by a few orders, and the number of the orders is higher according to the nuclear voltage of each stage of the chip. However, for the highest I/O level, the LDO has no way to obtain the higher core voltage, and in this case, a Boost circuit is usually used to Boost the input voltage of the entire power board so as to supply power to the highest LDO level.

The single Boost circuit is adopted to supply power to the upper LDO stages, and the following defects exist:

the Boost is a fixed voltage output, if the output voltage is too low, the differential pressure between the input and the output is too small for the LDO, the output driving capability of the LDO is insufficient, at the moment, if certain interference noise exists or the input voltage of the computation board suddenly becomes high, the LDO cannot obtain normal 1.8V level output, the IO of the chip cannot normally work, and the signal transmission between the chips is abnormal;

if Boost output voltage is too high, input and output voltage difference is too large for the LDO, and the loss power of the LDO becomes large.

Thus, there are inherent drawbacks to a single Boost circuit scheme.

Disclosure of Invention

In view of the above problems, the present invention provides a power supply circuit for a high performance server operation board, which has the following technical solutions:

a high performance server operation panel power supply circuit, comprising:

the Boost circuit is externally connected with power supply and used for boosting the power supply;

the input end of the Buck circuit is coupled to the output end of the Boost circuit, the Buck circuit is used for reducing voltage, and the output end of the Buck circuit is coupled to the input end of the LDO circuit;

the IC chip is used for calculating the block chain and is directly connected with an external power supply input with a signal;

and the LDO circuits are connected to the IC chips and used for providing stable voltage input for the I/O pins corresponding to the IC chips, and one LDO circuit is correspondingly arranged on each IC chip.

Further, the number of the IC chips is multiple, and the IC chips are connected through a cascade signal circuit.

Furthermore, one IC chip farthest from the Buck circuit is a first-stage IC chip, the LDO circuit corresponding to the first-stage IC chip is powered by the output of an nth-stage IC chip, and so on, and the LDO circuit corresponding to a second-stage IC chip is powered by the output of an n +1 th-stage IC chip; a current-limiting resistor is arranged on the input line of the LDO circuit corresponding to the n-stage IC chip close to the Buck circuit, the output end of the Buck circuit is connected to the first end of the current-limiting resistor, and the second end of the current-limiting resistor is connected to the input end of the LDO circuit.

Further, the output voltage of the output end of the Buck circuit is 2.5V.

Further, in the current corresponding to the current limiting resistor, the voltage output by the LDO is 1.8V.

Further, IN the Boost circuit and the Buck circuit, the GND terminal of the Boost circuit is grounded as a ground terminal, and the PWR IN terminal of the Buck circuit is a floating terminal.

Has the advantages that: the utility model has novel concept, reasonable design and convenient use, and can keep stable ground voltage input by combining the voltage stabilizer and the divider resistor in several levels of IC chips close to Buck through combining the Boost circuit and the Buck circuit to supply power for the IC chips used for calculation, especially aiming at the serial connection of a plurality of IC chips; meanwhile, because the Boost circuit and the Buck circuit are provided with feedback circuits, the output of the Boost circuit and the Buck circuit is very quick and stable.

Drawings

Fig. 1 is a schematic diagram of a circuit structure according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1, a power supply circuit for a high performance server operation board includes:

Specifically, the number of the IC chips is plural, and the IC chips are connected by a cascade signal circuit. The scheme means that power supplies are connected in series, computing power IC chips are connected in series, and signals are transmitted in a first-level and first-level mode.

Specifically, one of the IC chips farthest from the Buck circuit is a first-stage IC chip, the LDO circuit corresponding to the first-stage IC chip supplies power through the output of the nth-stage IC chip, and so on, and the LDO circuit corresponding to the second-stage IC chip supplies power through the output of the (n + 1) th-stage IC chip; a current-limiting resistor is arranged on the input line of the LDO circuit corresponding to the n-stage IC chip close to the Buck circuit, the output end of the Buck circuit is connected to the first end of the current-limiting resistor, and the second end of the current-limiting resistor is connected to the input end of the LDO circuit. For a plurality of IC chips, a cross-stage power supply manner is adopted from the first-stage IC chip, for example, the value of n is 9, then the LDO circuit of the first-stage IC chip is powered by the lead-out line of the ninth-stage IC chip, the LDO circuit of the second-stage IC chip is powered by the lead-out line of the tenth-stage IC chip, and so on. Since the nine-stage IC chip close to the Buck circuit has no higher-stage lead-out power supply, the current limiting resistor is used for limiting the current.

Specifically, the output voltage of the output end of the Buck circuit is 2.5V.

Specifically, in the circuit corresponding to the current-limiting resistor, the voltage output by the LDO is 1.8V.

Specifically, IN the Boost circuit and the Buck circuit, a GND terminal of the Boost circuit is grounded as a ground terminal, and a PWR IN terminal of the Buck circuit is a floating terminal.

Synthesize above all technical scheme, as shown in fig. 1 (the total number of IC chip is indefinite, and IC chip does not draw in the middle of the part in the picture), the utility model discloses an external input voltage passes through the Boost circuit input, accomplishes and steps up, follows input Buck circuit again behind the Boost circuit output, accomplish the step-down. A DC-DC chip is arranged in the Boost circuit to realize boosting, a feedback circuit is arranged at the same time to ensure the fast and stable speed of the Boost circuit, a DC-DC chip is arranged in the Buck circuit to realize voltage reduction, and a feedback circuit is arranged at the same time to ensure the fast and stable speed of the Buck circuit. The GND end of the Boost circuit is grounded to be used as a voltage reference end, and the PWR IN end of the Buck circuit is used as a floating end. As shown in fig. 1, a plurality of IC chips for block chain operation are provided, and are connected to each other through a cascade signal circuit, where the stage farthest from the Buck circuit is a first-stage IC chip, and the stage closest to the Buck circuit is a highest-stage IC chip. The output end of the Buck circuit simultaneously and directly supplies power to LDO circuits corresponding to the highest-level IC chip, the penultimate IC chip and the penultimate IC chip, and then the corresponding LDO circuits output power to I/O pins of the corresponding IC chips (eight levels are actually preferred, and only four of the eight levels are drawn in the figure). As shown in fig. 1, the IC chip provided with the current limiting resistor is specifically eight stages in this embodiment. Preferably eight stages (only four of which are shown), the specific number being as the case may be. Each power supply circuit is provided with current limiting resistors R1, R2, R3 and R4 connected in series, so that the voltage input to the highest-order IC chip, the penultimate IC chip and the penultimate IC chip is 1.8V under the condition that the Buck circuit outputs 2.5V. As shown IN the figure, the IC chip is directly input through PWR IN end signals, and is sequentially transmitted to the first-stage IC chip from the highest-stage IC chip and then is led out.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A high-performance server operation board power supply circuit is characterized by comprising:

2. The power supply circuit for the high-performance server operation panel according to claim 1, wherein the number of the IC chips is plural and the IC chips are connected by a cascade signal circuit.

3. The power supply circuit for high performance server operation board as claimed in claim 2, wherein the IC chip farthest from the Buck circuit is the first stage IC chip, the LDO circuit corresponding to the first stage IC chip is powered by the nth stage IC chip output, and so on, and the LDO circuit corresponding to the second stage IC chip is powered by the n +1 th stage IC chip output; a current-limiting resistor is arranged on the input line of the LDO circuit corresponding to the n-stage IC chip close to the Buck circuit, the output end of the Buck circuit is connected to the first end of the current-limiting resistor, and the second end of the current-limiting resistor is connected to the input end of the LDO circuit.

4. The power supply circuit for the operation panel of the high-performance server according to claim 3, wherein the output voltage of the Buck circuit is 2.5V.

5. The power supply circuit for the high-performance server operation panel according to claim 4, wherein in the circuit corresponding to the current-limiting resistor, the voltage of the LDO output is 1.8V.

6. The power supply circuit for the high-performance server operation panel according to claim 5, wherein IN the Boost circuit and the Buck circuit, a GND end of the Boost circuit is grounded and a PWR IN end of the Buck circuit is a floating end.