CN112953242B - An instantaneous overpower control method and circuit - Google Patents

Abstract

The invention provides an instantaneous overpower control method and a circuit, when a CS pin of a controller detects that a source voltage when a power tube is conducted is larger than a maximum peak current limiting threshold value in a normal mode in the controller within a plurality of continuous periods, the controller is judged to be in an instantaneous overpower state at the moment, so that the peak current of the CS pin of the controller is raised, the working frequency of the controller is improved, the controller works in an overpower working mode, and in the maintenance time of the instantaneous overpower state, if the output state is recovered to be normal or the timing of the maintenance time is finished, the instantaneous overpower state can be quitted under the two conditions, so that the controller is recovered to the normal working mode. The invention can distinguish the normal large dynamic state from the instantaneous overpower state, namely the normal large dynamic state can not be triggered by mistake to enter the instantaneous overpower state, so as to avoid the increase of the switching loss caused by overhigh working frequency and the influence on the working efficiency of the system.

Description

An instantaneous overpower control method and circuit

technical field

The invention relates to the technical field of power semiconductors, in particular to an instantaneous overpower control method and circuit, which are suitable for power management integrated circuit systems in power converters, especially for power management integrated circuit systems in flyback isolated converters.

Background technique

At present, due to the advantages of high efficiency, low loss, small size and light weight, the flyback converter (Flyback Converter) has been widely used as a power conversion device for various electronic products.

Flyback converters are frequently used in various portable devices such as mobile phones, digital cameras, tablet computers, digital music players, media players, portable hard drives, handheld game consoles, and other handheld consumer electronic devices. Portable devices are powered from limited internal batteries, such as lithium batteries. Therefore, flyback converters are often used to provide voltage regulation.

As technology advances, portable devices have more and more functions, requiring more power supply requirements from power converters. In some applications there will be a short-term higher current demand (short-term transient overpower boost demand). The above applications can be printers, motors, or for CPU power boosting functions. The above instantaneous overpower can be 2 times or even 3-4 times the maximum power required for normal operation. Known converters are not capable of delivering large amounts of instantaneous overpower without paying any penalty (eg using a larger transformer to avoid magnetic saturation conditions).

Therefore, it is necessary to provide a technology to enable the module to maintain normal operation during instantaneous overpower, avoid magnetic core saturation, and at the same time reduce as much as possible the increase in module volume and cost in order to meet the instantaneous overpower state.

Contents of the invention

In view of the above-mentioned shortcomings and limitations of the prior art, the technical problem to be solved by the present invention is to provide an instantaneous overpower control method and circuit, by detecting the peak current when the primary side power tube is turned on, it can be judged that the converter is in overpower , and then increase the operating frequency of the controller, and at the same time increase the peak current threshold, increase the load capacity of the converter, and maintain the stability of the output voltage; at the same time, the present invention is designed to maintain a programmable maintenance time for entering the instantaneous overpower state, meeting the needs of different applications for instantaneous Overpower requirements; the invention detects the maximum peak current threshold and output feedback voltage at the same time, distinguishes the output normal dynamic load from the instantaneous overpower state, and avoids accidentally entering the instantaneous overpower state when the output large dynamic load jumps, which affects the system work efficiency.

In order to solve the above-mentioned technical problems, the technical scheme of the instantaneous overpower control method proposed by the present invention is as follows:

An instantaneous overpower control method applied to a power converter, the power converter comprising a power tube and a controller, characterized in that the control method includes the following steps:

The peak current sampling step is detected by the CS pin of the controller to generate a voltage signal VCS that varies with the source voltage when the power transistor is turned on;

The PWM input gain and output state judgment step is to generate the voltage signal VFB_PFM, voltage signal VFB_PEM and voltage signal VFB_PWM that change with the output voltage of the power converter through the detection of the FB pin of the controller, and the output that reflects the output overpower of the power converter Status signal Vout_ok_H;

In the peak current sampling step, it is also selected to compare the obtained voltage signal VCS with the voltage signal VFB_PEM or the voltage signal VFB_PWM to generate a duty cycle control signal PWM_L; and also select to compare the obtained voltage signal VCS with the first threshold Vref_Lim1 or the first threshold Comparing the two thresholds Vref_Lim2 to generate the maximum duty cycle control signal PWM_Lim_L;

The instantaneous overpower judging step is to generate an instantaneous overpower state signal PEM_EN_L according to the maximum duty cycle control signal PWM_Lim_L;

The maintenance time programmable step is to generate the maintenance time of the over-power state according to the instantaneous over-power state signal PEM_EN_L; and to generate the exit instantaneous over-power state signal PEM_out_ok_L according to the instantaneous over-power state signal PEM_EN_L and the output state signal Vout_ok_H;

The frequency and duty cycle control step generates the drive signal GATE, the low-voltage drive signal Drive_H and The current signal IFB_PEM that changes with the output voltage of the power converter; at the same time, the first operating frequency of the controller operating in the normal operating mode or the second operating frequency in the instantaneous over-power mode is selected according to the instantaneous over-power state signal PEM_EN_L and the voltage signal VFB_PFM ;

Among them, Vref_Lim1﹤Vref_Lim2, the first working frequency﹤the second working frequency, the second working frequency changes with the voltage signal VFB_PFM;

Each step also includes switching the working mode of the controller according to the following control logic;

When VCS≤Vref_Lim1 or although VCS>Vref_Lim1, but the duration is less than N cycles, the maximum duty cycle control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both at high level, and the controller is working in the normal working mode, select the voltage The signal VCS is compared with the first threshold Vref_Lim1 to select the controller to work at the first working frequency;

When VCS>Vref_Lim1 lasts for more than N cycles, the maximum duty ratio control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both low, the controller works in the overpower mode, and the voltage signal VCS and the second threshold are selected Vref_Lim2 compares and selects the controller to work at the second operating frequency;

When the instantaneous overpower state signal PEM_EN_L is low level, if the output state of the power converter returns to normal, the output state signal Vout_ok_H is high level; when the maintenance time is over or the output state signal Vout_ok_H is high level, the instantaneous overpower The status signal PEM_out_ok_L is low level, and the controller returns to the normal working mode at this time;

Where N is a set positive integer.

Further, the higher the overpower multiple output by the power converter is, the higher the second operating frequency is.

Further, the length of the maintenance time is set through the PEM pin of the controller, and the higher the overpower multiple output by the power converter is, the shorter the maintenance time is.

Correspondingly, the technical solution of the instantaneous overpower control circuit proposed by the present invention is as follows:

An instantaneous overpower control circuit, applied to a power converter, the power converter includes a power tube and a controller, characterized in that the control circuit includes: a peak current sampling unit, an instantaneous overpower judging unit, a maintenance Time programmable unit, PWM input gain and output state judgment unit and frequency and duty ratio control unit;

The peak current sampling unit is detected by the CS pin of the controller to generate a voltage signal VCS that changes with the source voltage when the power transistor is turned on;

The PWM input gain and output state judgment unit generates voltage signals VFB_PFM, voltage signal VFB_PEM, and voltage signal VFB_PWM that vary with the output voltage of the power converter through the detection of the FB pin of the controller, and the output that reflects the output overpower of the power converter Status signal Vout_ok_H;

The peak current sampling unit also selects to compare the obtained voltage signal VCS with the voltage signal VFB_PEM or voltage signal VFB_PWM to generate a duty ratio control signal PWM_L; and also selects to compare the obtained voltage signal VCS with the first threshold Vref_Lim1 or the first threshold Vref_Lim1 Comparing the two thresholds Vref_Lim2 to generate the maximum duty cycle control signal PWM_Lim_L;

The instantaneous overpower judging unit generates an instantaneous overpower state signal PEM_EN_L according to the maximum duty ratio control signal PWM_Lim_L;

The maintenance time programmable unit generates the maintenance time of the over-power state according to the instantaneous over-power state signal PEM_EN_L; also generates the exiting instantaneous over-power state signal PEM_out_ok_L according to the instantaneous over-power state signal PEM_EN_L and the output state signal Vout_ok_H;

The frequency and duty cycle control unit generates the drive signal GATE, the internal low voltage drive signal Drive_H and The current signal IFB_PEM that changes with the output voltage of the power converter; at the same time, the first operating frequency of the controller operating in the normal operating mode or the second operating frequency in the instantaneous over-power mode is selected according to the instantaneous over-power state signal PEM_EN_L and the voltage signal VFB_PFM ;

Among them, Vref_Lim1﹤Vref_Lim2, the first working frequency﹤the second working frequency, the second working frequency changes with the voltage signal VFB_PFM;

Each circuit unit also realizes the switching of the working mode of the controller according to the following control logic;

When VCS≤Vref_Lim1 or although VCS>Vref_Lim1, but the duration is less than N cycles, the maximum duty ratio control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both at high level, the controller works in the normal working mode, and the peak current The sampling unit selection voltage signal VCS is compared with the first threshold Vref_Lim1, and the frequency and duty cycle control unit selection controller works at the first operating frequency;

When VCS>Vref_Lim1 lasts for more than N periods, the maximum duty ratio control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both low, the controller works in the overpower mode, and the peak current sampling unit selects the voltage signal VCS Compared with the second threshold Vref_Lim2, the frequency and duty cycle control unit selects the controller to work at the second operating frequency;

When the instantaneous overpower state signal PEM_EN_L is low level, if the output state of the power converter returns to normal, the output state signal Vout_ok_H is high level, and when the maintenance time ends or the output state signal Vout_ok_H is high level, the instantaneous overpower The status signal PEM_out_ok_L is low level, and the controller returns to the normal working mode at this time;

Where N is a set positive integer.

Further, the higher the overpower multiple output by the power converter is, the higher the second operating frequency is.

Further, the length of the maintenance time is set through the PEM pin of the controller, and the higher the overpower multiple output by the power converter is, the shorter the maintenance time is.

As a specific implementation of the peak current sampling unit, it is characterized in that it includes: a data selector MUX1 for choosing one of two, a data selector MUX2 for choosing one of two, a comparator CMP1 and a comparator CMP2; the negative phase input terminal of the comparator CMP1 It is used to connect the CS pin of the controller, and at the same time it is connected to the negative phase input terminal of the comparator CMP2, and the positive phase input terminal is connected to the output terminal of the two-to-one data selector MUX1, and the output terminal outputs the duty cycle control signal PWM_L; The first input terminal of the one-to-one data selector MUX1 inputs the voltage signal VFB_PWM, the second input terminal inputs the voltage signal VFB_PEM, and the third input terminal is connected with the third input terminal of the two-to-one data selector MUX2 to input the instantaneous overpower State signal PEM_EN_L; the first input terminal of the two-choice data selector MUX2 inputs the first threshold value Vref_Lim1, the second input terminal inputs the second threshold value Vref_Lim2, and the output terminal is connected to the non-inverting input terminal of the comparator CMP2; the output terminal of the comparator CMP2 Output maximum duty ratio control signal PWM_Lim_L.

As a specific implementation of the above-mentioned one-two data selector MUX1, it is characterized in that it includes: NMOS transistor NM1, NMOS transistor NM2 and a NOT gate, and the drain of the NMOS transistor NM1 is used as the first two-choice data selector MUX1. An input terminal, the source of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM2, and the intersection of this connection is used as the output terminal of the two-to-one data selector MUX1; the gate of the NMOS transistor NM1 is connected to the input terminal of the NOT gate, The junction of this connection is used as the third input terminal of the data selector MUX1; the output terminal of the NOT gate is connected to the gate of the NMOS transistor NM2, and the drain of the NMOS transistor NM2 is used as the second input terminal of the data selector MUX1. input.

As another specific implementation of the above-mentioned two-to-one data selector MUX1, it is characterized in that it includes: a transmission gate Transgate1, a transmission gate Transgate2 and a NOT gate not, and the input terminal of the transmission gate Transgate1 is used as the second data selector of the two-to-one data selector. One input terminal, the output terminal of the transmission gate Transgate1 is connected to the output terminal of the transmission gate Transgate2, and the intersection of this connection is used as the output terminal of the two-to-one data selector MUX1; the positive control terminal of the transmission gate Transgate1 is the input terminal of the NOT gate not Connection, the junction of this connection is used as the third input terminal of the two-choice data selector MUX1; the output terminal of the not gate is connected to the positive control terminal of the transmission gate Transgate2, and the input terminal of the transmission gate Transgate2 is used as the two-choice data selector The second input of MUX1.

As a specific implementation of the instantaneous overpower judgment unit, it is characterized in that it includes: a judgment delay unit, an RS latch and a NOT gate not_1; the judgment delay unit is based on the maximum duty cycle control signal input by the first input terminal PWM_Lim_L, the low-voltage drive signal Drive_H inside the controller input from the second input terminal, and the drive signal GATE input from the third input terminal generate a judgment signal PEM_IN_H for entering the instantaneous overpower state, which is output to the S terminal of the RS latch, and the RS latch The input terminal R of the register exits the instantaneous overpower status signal PEM_out_ok_L, the output terminal Q of the RS latch is connected to the input terminal of the NOT gate not_1, and the output terminal of the NOT gate not_1 outputs the instantaneous overpower status signal PEM_EN_L.

As a specific implementation of the above judgment delay unit, it is characterized in that it includes: RS latch RS1, RS latch RS2, D flip-flop DFF, NOT gate not1, NOT gate not2, NOT gate not3, AND gate and, the leading edge blanking LEB and the counter counter; the S terminal of the RS latch RS1 inputs the maximum duty cycle control signal PWM_Lim_L, and the R terminal is connected to the output terminal of the NOT gate not1, and the input terminal of the NOT gate not1 is connected to the first of the counter counter After the input terminal CP is connected, input the low-voltage drive signal Drive_H inside the controller, the output terminal Q of the RS latch RS1 is connected to the first input terminal D of the D flip-flop DFF, and the second input terminal CP of the D flip-flop DFF is a NAND gate The output terminal of not2 is connected, the input terminal of the NOT gate not2 is connected to the output terminal of the leading edge blanking LEB, the input terminal of the leading edge blanking LEB inputs the drive signal GATE, and the third input terminal Clr_L of the D flip-flop DFF is simultaneously connected with the AND gate and The output terminal is connected to the R terminal of the RS latch RS2, the first input terminal of the AND gate and inputs the instantaneous overpower state signal PEM_EN_L, and the second input terminal of the AND gate and is used to input the low-voltage initialization signal ENP_lv inside the controller, D The output terminal Q of the flip-flop DFF is connected to the second input terminal Clr_L of the counter counter, the output terminal Q of the counter counter is connected to the input terminal of the NOT gate not3, and the output terminal of the NOT gate not3 is connected to the S terminal of the RS latch RS2, The output terminal Q of the RS latch RS2 outputs the judgment signal PEM_IN_H for entering the instantaneous overpower state.

As a specific implementation of the maintenance time programmable unit, it is characterized in that it includes: current source IB ₁ , current source IB ₂ , capacitor C1, NMOS transistor NM1_1, comparator CMP, NAND gate nand, latch LATH, D flip-flop DFF1, NOT gate not4, NOT gate not5, NOT gate not6, delay Delay, and AND gate and1;

The input terminal of the current source IB ₁ is used to connect to the low-voltage power supply VCC, and the output terminal is used to connect to the PEM pin of the controller. The output terminal of the current source IB ₁ is also connected to the non-inverting input terminal of the comparator CMP; the current source IB ₂ The input terminal of the current source IB2 is used to connect the low-voltage power supply VCC _, the output terminal inputs the current signal IFB_PEM, and the output terminal of the current source IB ₂ is also connected with one terminal of the capacitor C1, the drain of the NMOS transistor NM1_1 and the inverting input of the comparator CMP The other end of the capacitor C1 is simultaneously connected to the source of the NMOS transistor NM1_1 and the ground of the controller; the gate of the NMOS transistor NM1_1 is connected to the output end of the NAND gate nand, and the first input end of the NAND gate nand is simultaneously connected to the The output terminal of the latch LATH is connected to the second input terminal CP of the D flip-flop DFF1, and the second input terminal of the NAND gate nand is connected to the third input terminal Clr_lv of the D flip-flop DFF1 for inputting the internal Low-voltage initialization signal ENP_lv; the input terminal of the latch LATH is connected to the output terminal of the comparator CMP; the first input terminal D of the D flip-flop DFF1 is connected to the second output terminal Q of the D flip-flop, and the first input terminal of the D flip-flop DFF1 The output terminal Q is connected to the input terminal of the NOT gate not4, the output terminal of the NOT gate not4 is connected to the first input terminal CP_L of the counter counter1, the second input terminal Clr_L of the counter counter1 is connected to the output terminal of the NOT gate not5, and the output terminal of the NOT gate not5 The input terminal inputs the instantaneous overpower state signal PEM_EN_L; the output terminal of the counter counter1 is connected to the input terminal of the NOT gate not6, the output terminal of the NOT gate not6 is connected to the second input terminal of the AND gate and1, and the first input terminal of the AND gate and1 is connected to the input terminal of the AND gate and1. The output terminal of the delay Delay is connected, and the input terminal of the delay Delay inputs and outputs the state signal Vout_ok_H.

As a PWM input gain and output state judging unit, it includes PWM input gain, one-of-two data selector MUX3, comparator CMP3, NOT gate not7; the first input end of PWM input gain is used to connect the FB lead of the controller pin, the second input end of the PWM input gain is connected to the third input end of the data selector MUX3, and then the instantaneous overpower state signal PEM_EN_L is input, and the first output end of the PWM input gain is connected to the non-inverting input end of the comparator CMP3 Connection, the second output terminal, the third output terminal and the fourth output terminal of the PWM input gain respectively output the voltage signal VFB_PFM, the voltage signal VFB_PEM and the voltage signal VFB_PWM; the first input terminal of the two-choice data selector MUX3 is used for input control The first reference voltage signal Vref1 inside the controller is connected, the second input terminal of the data selector MUX3 is used to input the second reference voltage signal Vref2 inside the controller, and the output terminal of the data selector MUX3 is connected to the comparator The negative phase input terminal of CMP3 is connected, the output terminal of the comparator CMP3 is connected with the input terminal of the NOT gate not7, and the output terminal of the NOT gate not7 outputs the output state signal Vout_ok_H.

As a specific implementation of the above-mentioned PWM input gain, it is characterized in that it includes: a switched capacitor filter Filter, an NMOS transistor NM3, a resistor R1, a resistor R2, a resistor R3, and a resistor R4; the input end of the switched capacitor filter Filter is used for Connect the FB pin of the controller, the first output terminal of the switched capacitor filter Filter is connected to the gate of the NMOS transistor NM3, and the second output terminal of the switched capacitor filter Filter outputs the voltage signal VFB_PFM; the drain of the NMOS transistor NM3 is used for Connect the low-voltage power supply VCC, the source of the NMOS transistor NM3 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, and the junction of this connection is connected to the non-inverting input end of the comparator CMP3; the other end of the resistor R2 is connected to One end of the resistor R3 is connected, and the junction of this connection outputs the voltage signal VFB_PEM; the other end of the resistor R3 is connected to one end of the resistor R4, and the junction of this connection outputs the voltage signal VFB_PWM, and the other end of the resistor R4 is connected to the ground of the controller.

As a specific implementation of the frequency and duty cycle control unit, it is characterized in that it includes: a voltage-controlled oscillator VCO, an AND gate and2, an RS latch RS3 and a driver Driver; the first input terminal of the voltage-controlled oscillator VCO Input the instantaneous overpower state signal PEM_EN_L, the second input terminal of the voltage-controlled oscillator VCO inputs the voltage signal VFB_PFM, the first output terminal of the voltage-controlled oscillator VCO outputs the current signal IFB_PEM, the second output terminal of the voltage-controlled oscillator VCO and RS The S terminal of the latch RS3 is connected, the R terminal of the RS latch is connected to the output terminal of the AND gate and2, the first input terminal of the AND gate and2 inputs the duty ratio control signal PWM_L, and the second input terminal of the AND gate inputs The maximum duty ratio control signal PWM_Lim_L, the output terminal Q of the RS latch RS3 is connected to the input terminal of the driver, this connection point outputs the low-voltage drive signal Drive_H inside the controller, and the output terminal of the driver outputs the drive signal GATE.

Brief operating principle of the present invention is as follows:

When the CS pin of the controller detects that the source voltage when the power transistor is turned on is greater than the maximum peak current limit threshold in the normal mode inside the controller for several consecutive cycles, it is judged that the controller is in an instantaneous overcurrent condition. Power state, and then select a larger maximum peak current limit threshold through the instantaneous over-power state signal to increase the peak current; at the same time, the instantaneous over-power state signal controls the voltage-controlled oscillator to switch to a higher operating frequency, so that the GATE of the controller The pin outputs a higher operating frequency to meet the demand for overpower, and further generates voltage and current that vary with the voltage of the controller pin FB through the PWM input gain part, and the voltage that varies with the FB voltage controls the voltage-controlled oscillator to produce a variable The maximum operating frequency is to meet the requirements of different overpower multiples for the maximum operating frequency; the current that changes with the FB voltage, under the control of the instantaneous overpower state signal, makes the maintenance time change with the size of the overpower multiple, and at the same time through the controller Different sampling resistors are externally connected to the PEM pin of the PEM to generate different holding times to meet the requirements of different overpower states for holding time. Further, within the maintenance time of the instantaneous overpower state, the output state is judged by the voltage of the FB pin of the controller. If the output state returns to normal or the maintenance time is over, in both cases, the instantaneous overpower state can be exited, so that the control to return to normal operating mode.

In order to avoid deviations or obstacles in understanding, the above technical solutions are supplemented as follows:

1. CS pin detection and related signal generation in the peak current sampling step, FB pin detection and related signal generation in the PWM input gain and output state judgment step, these two steps are carried out simultaneously;

2. The first threshold Vref_Lim1, the second threshold Vref_Lim2, the first reference voltage signal Vref1, the second reference voltage signal Vref2 and the internal low-voltage initialization signal ENP_lv of the controller are all preset according to the actual application needs of the controller.

The specific working principle and relevant analysis of the present invention will be described in detail in the following specific embodiments. Beneficial effect of the present invention is summarized as follows now:

1. The present invention can distinguish between normal large dynamics and instantaneous over-power states, that is, normal large dynamics will not be triggered into instantaneous over-power states by mistake, so as to avoid the increase of switching loss caused by excessively high operating frequency and affect the working efficiency of the system.

2. The present invention can make the maximum operating frequency of the controller adaptive to the instantaneous overpower multiple state through the loop, that is, the maximum operating frequency of the controller working in the instantaneous overpower mode is adaptive to the instantaneous overpower multiple, and the higher the instantaneous overpower multiple , the higher the maximum operating frequency of the controller is.

3. The maintenance time of the overpower state can be programmed in the present invention to meet the requirements of different applications for instantaneous overpower.

4. The present invention can adapt the instantaneous overpower multiple state through the loop while programming the holding time, that is, the higher the instantaneous overpower multiple, the shorter the holding time.

Description of drawings

FIG. 1 is a typical circuit schematic diagram of a controller 10 including an instantaneous overpower control circuit 100 of the present invention applied in a flyback converter;

FIG. 2 is a functional block diagram of an embodiment of the instantaneous overpower control circuit 100 of the present invention;

FIG. 3 is a schematic circuit diagram of an embodiment of the peak current sampling unit 101 of the present invention;

Fig. 4 is the schematic circuit diagram of an embodiment of the data selector MUX1011 in the peak current sampling unit 101 of Fig. 3;

FIG. 5 is a schematic circuit diagram of an embodiment of the instantaneous overpower judging unit 102 of the present invention;

Fig. 6 is the schematic circuit diagram of an embodiment of the judging delay unit 1021 in the instantaneous overpower judging unit 102 of Fig. 5;

FIG. 7 is a schematic circuit diagram of an embodiment of the maintenance time programmable unit 103 of the present invention;

FIG. 8 is a schematic circuit diagram of an embodiment of the PWM input gain and output state judging unit 104 of the present invention;

FIG. 9 is a schematic circuit diagram of an embodiment of the PWM input gain 1041 in the PWM input gain and output state judging unit 104 of FIG. 8;

FIG. 10 is a schematic circuit diagram of an embodiment of the frequency and duty ratio control unit 105 of the present invention;

FIG. 11 is a schematic diagram of signal waveforms related to a large dynamic load and an instantaneous overpower state of a flyback converter to which the instantaneous overpower control circuit 100 of the present invention is applied;

FIG. 12 is a large dynamic load and transient overpower state system simulation related signal waveform diagram of the flyback converter applying the instantaneous overpower control circuit 100 of the present invention;

FIG. 13 is a schematic circuit diagram of another embodiment of the data selector MUX2011 in the peak current sampling unit 201 in FIG. 3 .

Detailed ways

In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

first embodiment

FIG. 1 is a typical circuit schematic diagram of a controller 10 including an instantaneous overpower control circuit 100 of the present invention applied in a flyback converter. As shown in Figure 1, the circuit includes a controller 10, an optocoupler OP1, a coupling transformer T1, an input voltage VIN, a power tube M1, resistors R _CS , R _PEM , R1, R2, R3, R4, R _O , capacitors C _O , C1, three-terminal regulator TL431 and diode D1.

The controller 10 includes the following pins, and other pins are not related to the present invention, so they will not be described:

CS pin: current sampling input port, used to sample the peak voltage of the source when the power tube is turned on;

PEM pin: Instantaneous overpower time programmable pin, used to program the maintenance time of the instantaneous overpower state;

FB pin: optocoupler feedback pin, used to feed back the output voltage change signal of the power converter;

GATE pin: used to connect to the control terminal of the power tube in the power converter to provide a driving signal for the power tube in the power converter;

GND pin: used to connect the primary ground of the flyback converter.

In Fig. 1, the FB pin of the controller 10 is connected to the 3 pin of the optocoupler OP1, the 4 pin of the optocoupler OP1 is connected to the primary ground, the PEM pin of the controller 10 is connected to one end of the resistor R _PEM , and the other end of the resistor R _PEM One end is connected to the GND pin of the controller and the primary ground, the GATE pin of the controller is connected to the gate of the power transistor M1, the CS pin of the controller is connected to the source of the power transistor M1, and at the same time is connected to the sampling resistor R _CS One end of the sampling resistor R _CS is connected to the primary ground, the drain of the power transistor M1 is connected to the same-named end of the primary coil of the coupling transformer T1, and the opposite end of the primary coil of the coupling transformer T1 is connected to the input voltage VIN Connect, the terminal with the same name of the secondary coil of the coupling transformer T1 is connected to the anode of the diode D1, and the cathode of the diode D1 is simultaneously connected to one end of the output filter capacitor C _O , one end of the output load resistor R _O , one end of the resistor R1, and one end of the resistor R2 It is connected to the positive terminal + of the output voltage V _O , and the opposite end of the secondary coil of the coupling transformer T1 is simultaneously connected to the other end of the output capacitor C _O , the other end of the resistor R _O , the negative terminal of the output voltage V _O - and the secondary side Ground connection; the other end of resistor R1 is connected to pin 1 of optocoupler OP1, and pin 2 of optocoupler OP1 is connected to one end of resistor R4 and the cathode of three-terminal regulator TL431 at the same time, and the other end of resistor R4 is connected to one end of capacitor C1 , the other end of the capacitor C1 is simultaneously connected to one end of the resistor R3, the other end of the resistor R2 and the reference input end of the three-terminal voltage regulator TL431; the anode of the three-terminal voltage regulator TL431 and the other end of the resistor R3 are connected to the secondary ground.

FIG. 2 is a functional block diagram of the instantaneous overpower control circuit 100 of the present invention. The instantaneous overpower control circuit 100 of the present invention is integrated in the controller 10 of FIG. 1 . In addition to the instantaneous overpower control circuit 100 of the present invention, the controller 10 also includes other circuits, such as a low-voltage power supply VCC generation circuit and a reference voltage generation circuit. And low-voltage initialization signal generation circuit, etc. In the present invention, the low-voltage power supply VCC can be obtained by stepping down the input voltage VIN of the converter, and is used to supply power to each sub-module inside the controller 10. The low-voltage power supply VCC=5V selected in the embodiment of the present invention; the reference voltage generation circuit can be obtained by a known The bandgap reference circuit is obtained and is used to input a stable voltage reference signal to the modules inside the controller. The present invention needs to produce two reference voltage signals, namely the first reference voltage signal Vref1 and the second reference voltage signal Vref2; the low-voltage initialization signal generates The circuit can be obtained by adding a delay to the known start-up circuit. The low-voltage initialization signal ENP_lv generated by it is usually established with a delay of a period of time after the internal power supply voltage of the controller is generated, and is used for corresponding logic units inside the controller, such as RS latches, D flip-flops, counters, etc. are used for initialization, so that they are at an effective potential before the logic works.

Each unit circuit of the instantaneous overpower control circuit 100 of the present invention also includes more sub-circuits, such as the voltage-controlled oscillator VCO, the switched capacitor filter Filter, the driver driver, and the counter counter described in the specific embodiments of each unit circuit below. , delay Delay, leading edge blanking LEB, bias current source IBIAS, etc. These circuits have many known circuit structures. Since they are not the innovation of the present invention, they will not be described in specific embodiments below.

As shown in Figure 2, the instantaneous overpower control circuit 100 of this embodiment includes a peak current sampling unit 101, an instantaneous overpower judging unit 102, a hold time programmable unit 103, a PWM input gain and output state judging unit 104 and frequency and Duty ratio control unit 105 .

The CS pin is connected to the first input terminal of the peak current sampling unit 101, and the first output terminal of the peak current sampling unit 101 outputs the maximum duty cycle control signal PWM_Lim_L to the first input terminal of the instantaneous overpower judging unit 102 and the frequency and duty cycle The first input end of the duty ratio control unit 105; the second output end of the peak current sampling unit 101 outputs the duty ratio control signal PWM_L to the second input end of the frequency and duty ratio control unit 105; the instantaneous overpower judgment unit 102 The output end outputs the instantaneous overpower state signal PEM_EN_L to the first input end of the maintenance time programmable unit 103, the second input end of the peak current sampling unit 101, the first input end of the PWM input gain and output state judgment unit 104 and the frequency and The third input terminal of the duty ratio control unit 105 is connected; the second input terminal of the maintenance time programmable unit 103 is connected with the PEM pin of the controller, and the third input terminal of the maintenance time programmable unit 103 is connected to the PWM input gain and output The first output end of the state judging unit 104 is connected, and the output end of the maintenance time programmable unit 103 outputs the exiting instantaneous overpower state signal PEM_out_ok_L to the second input end of the instantaneous overpower judging unit 102; the FB pin and the PWM input gain and output The second input end of the state judgment unit 104 is connected, and the second output end of the PWM input gain and output state judgment unit 104 outputs a voltage signal VFB_PFM that varies with the output voltage of the power converter to the fourth input of the frequency and duty ratio control unit 105 terminal, the third output terminal of the PWM input gain and output state judging unit 104 outputs the voltage signal VFB_PEM that varies with the output voltage of the power converter to the third input end of the peak current sampling unit 101, and the PWM input gain and output state judging unit 104 The fourth output terminal outputs the voltage signal VFB_PWM signal that varies with the output voltage of the power converter to the fourth input terminal of the peak current sampling unit 101; the GATE pin of the controller is connected to the first output terminal of the frequency and duty ratio control unit 105 , the first output end of the frequency and duty ratio control unit 105 outputs the driving signal GATE, and the second output end of the frequency and duty ratio control unit 105 outputs the internal low-voltage drive Drive_H signal of the controller to the second step of the instantaneous overpower judgment unit 102 Three input terminals, the third output terminal of the frequency and duty ratio control unit 105 outputs the current signal IFB_PEM that varies with the output voltage of the power converter to the fourth input terminal of the sustain time programmable unit 103 .

There are many signals involved in the present invention, which are concentrated as follows:

Voltage signal VCS: the voltage signal that changes with the source voltage when the power tube is turned on;

Voltage signal VFB_PFM: a voltage signal that changes with the output voltage of the power converter, used to control the change of the operating frequency of the controller;

Voltage signal VFB_PEM: a voltage signal that changes with the output voltage of the power converter, used to control the change of the duty cycle of the drive signal output by the controller in the instantaneous overpower mode;

Voltage signal VFB_PWM: a voltage signal that changes with the output voltage of the power converter, and is used to control the change of the duty cycle of the drive signal output by the controller in the normal working mode;

Output status signal Vout_ok_H: a voltage signal reflecting the output overpower condition of the power converter;

Duty cycle control signal PWM_L: used to indicate the duty cycle of the controller in normal working mode;

Maximum duty cycle control signal PWM_Lim_L: used to indicate the duty cycle of the controller in the state of instantaneous overpower;

The first threshold Vref_Lim1: the maximum peak current limit threshold of the controller in normal working mode;

The second threshold Vref_Lim2: the maximum peak current limit threshold of the controller in the overpower working mode;

Instantaneous overpower state signal PEM_EN_L: used to indicate that the controller is working in an instantaneous overpower state;

Exit the instantaneous overpower state signal PEM_out_ok_L: used to indicate that the controller has exited the instantaneous overpower state;

Drive signal GATE: the signal that controls the power tube in the power converter to turn on and off;

Low-voltage driving signal Drive_H inside the controller: The driving module inside the controller generates the above-mentioned driving signal GATE according to this signal;

Current signal IFB_PEM: The current signal that changes with the output voltage of the power converter.

1 and 2, the working principle of the instantaneous overpower control circuit 100 is described as follows:

When the peak current sampling unit 101 detects through the CS pin that the voltage on the sampling resistor R _CS when the power transistor M1 is turned on is greater than the maximum peak current limit threshold in the normal working mode inside the controller, it outputs the maximum duty cycle control signal PWM_Lim_L is at a low level and sent to the instantaneous overpower judging unit 102. If the maximum duty ratio control signal PWM_Lim_L has been at a low level for several cycles, it is judged that the controller is in an instantaneous overpower state at this time, so that the instantaneous overpower The judging unit 102 outputs the instantaneous overpower state signal PEM_EN_L as a low level, and the instantaneous overpower state signal PEM_EN_L is sent to the peak current sampling unit 101 to select a larger maximum peak current limit threshold to increase the primary peak current of the controller; At the same time, the instantaneous over-power state signal PEM_EN_L is input to the frequency and duty ratio control unit 105, which controls the internal voltage-controlled oscillator to switch to a higher operating frequency, so that the GATE pin of the controller outputs a higher operating frequency to meet the over-voltage requirement. power requirements.

Further, the instantaneous overpower state signal PEM_EN_L is also sent to the PWM input gain and output state judging unit 104, through its internal PWM input gain circuit to generate a voltage signal VFB_PFM that varies with the voltage of the pin FB, and sent to the frequency and duty cycle control The unit 105 controls the internal voltage-controlled oscillator to generate a changed maximum operating frequency, so as to meet the requirements of different overpower multiples for the maximum operating frequency.

Further, the frequency and duty cycle control unit 105 outputs a current signal IFB_PEM that changes with the FB voltage, and sends it to the programmable maintenance time unit 103, and under the control of the instantaneous overpower state signal PEM_EN_L, the maintenance time is changed with the magnitude of the overpower multiple Change.

Further, the maintenance time programmable unit 103 is externally connected to different sampling resistors R _PEM through the PEM pin of the controller (that is, the resistance value of the sampling resistor R _PEM can be selected according to actual conditions), under the control of the instantaneous overpower state signal PEM_EN_L, Furthermore, different maintenance times are generated to meet the requirements of different overpower states on the maintenance time.

Further, the instantaneous overpower state signal PEM_EN_L is sent to the PWM input gain and output state judging unit 104. During the maintenance time of the instantaneous overpower state, the output state is judged by the FB pin voltage of the controller to generate the output state signal Vout_ok_H, which will be This output state signal Vout_ok_H is sent to the maintenance time programmable unit 103, if the output state returns to normal, then the output state signal Vout_ok_H is high level; The maintenance time programmable unit 103 generates a signal PEM_out_ok_L to exit the transient overpower state at a low level, so that the controller returns to the normal working mode.

FIG. 3 is a schematic circuit diagram of an embodiment of the peak current sampling unit 101 of the present invention. The peak current sampling unit 101 includes one-of-two data selectors MUX1, MUX2, and comparators CMP1, CMP2.

The CS pin is connected to the negative phase input terminal of the comparator CMP1 and the negative phase input terminal of the comparator CMP2 at the same time; the positive phase input terminal of the comparator CMP1 is connected to the output terminal of the two-to-one data selector MUX1, and the two-to-one data selection The first input end of the device MUX1 is the fourth input end of the peak current sampling unit 101, the input voltage signal VFB_PWM, the second input end of the two-to-one data selector MUX1 is the third input end of the peak current sampling unit 101, the input voltage The signal VFB_PEM, the third input terminal of the data selector MUX1 is the second input terminal of the peak current sampling unit 101, and the instantaneous overpower state signal PEM_EN_L is input, and the output terminal of the comparator CMP1 is the second input terminal of the peak current sampling unit 101. The output terminal outputs the duty ratio control signal PWM_L; the first input terminal of the two-to-one data selector MUX2 is used to input the first threshold value Vref_Lim1, and the second input terminal of the two-to-one data selector MUX2 is used to input the second threshold value Vref_Lim2 , Vref_Lim2>Vref_Lim1, the third input terminal of the data selector MUX2 is connected to the second input terminal of the peak current sampling unit 101, and the instantaneous overpower state signal PEM_EN_L is input, and its output terminal is connected to the non-inverting input terminal of the comparator CMP2 , the output terminal of the comparator CMP2 is the first output terminal of the peak current sampling unit 101, which outputs the maximum duty ratio control signal PWM_Lim_L.

FIG. 4 is a circuit diagram of an electrical embodiment of the data selector MUX1011 in the peak current sampling unit 101 in FIG. 3 of the present invention. One-of-two data selector MUX1011 includes NMOS transistors NM1, NM2 and a not gate, the drain of NMOS transistor NM1 serves as the first input terminal Vin1 of the one-two data selector 1011, the source of NMOS transistor NM1 and the gate of NMOS transistor NM2 The source is connected, and the junction of this connection is used as the output terminal Vout of the data selector 1011; Three-input terminal Vin3; the output terminal of the not gate is connected to the gate of the NMOS transistor NM2, and the drain of the NMOS transistor NM2 is used as the second input terminal Vin2 of the two-to-one data selector 1011 .

1, 3 and 4, the working principle of the embodiment of the peak current sampling unit 101 of the present invention is described as follows:

The comparator CMP1 is used to detect the voltage of the CS pin of the controller, and compare it with the output voltage signal fed back by the FB pin of the controller through the optocoupler OP1, that is, with the FB voltage generated by the PWM input gain and output state judgment unit 104 The changing voltage signal VFB_PWM is compared with the voltage signal VFB_PEM. When the instantaneous overpower state signal PEM_EN_L is low, the voltage signal VFB_PEM is selected for comparison with the CS pin voltage signal VCS to generate the duty ratio control signal PWM_L in the overpower working mode. If the instantaneous overpower state signal PEM_EN_L is high level, the selected voltage signal VFB_PWM is compared with the CS pin voltage signal VCS to generate the duty cycle control signal PWM_L in normal working mode; the comparator CMP2 is used to limit the maximum value of the CS pin Voltage, which is to limit the maximum peak current flowing through the primary side power tube M1, specifically: if the instantaneous overpower state signal PEM_EN_L is low, select a higher reference voltage Vref_Lim2 and compare it with the CS pin voltage signal VCS, Generate the maximum duty cycle control signal PWM_Lim_L in the overpower working mode. If PEM_EN_L is high level, select the maximum peak current limit threshold Vref_Lim1 in the normal mode and compare it with the CS pin voltage signal VCS to generate the maximum duty cycle in the normal working mode. Duty cycle control signal PWM_Lim_L.

That is, the peak current sampling unit 101 can not only limit the maximum peak current of the primary power transistor M1 in the normal working mode, but also limit the maximum peak current of the primary power transistor M1 in the overpower working mode; The duty cycle control signal PWM_L can also generate the duty cycle control signal PWM_L in the over-power working mode.

The peak current sampling unit 101 can distinguish between the peak current mode control in the normal working mode and the peak current mode control in the overpower working mode.

FIG. 5 is a schematic circuit diagram of an embodiment of the instantaneous overpower judging unit 102 of the present invention. The instantaneous overpower judging unit 102 includes a judging delay unit 1021 , an RS latch RS and a NOT gate not_1. The first input end of the judgment delay unit 1021 is the first input end of the instantaneous overpower judgment unit 102, and the maximum duty ratio control signal PWM_Lim_L is input, and the second input end thereof is the third input end of the instantaneous overpower judgment unit 102, Input the low-voltage drive signal Drive_H inside the controller, the third input terminal of which is the fourth input terminal of the instantaneous overpower judgment unit 102, input the drive signal GATE, and the output terminal outputs the judgment signal PEM_IN_H for entering the instantaneous overpower state to be latched by RS The S terminal of the device, the R terminal of the RS latch is the second input terminal of the instantaneous overpower judging unit 102, which inputs and exits the instantaneous overpower state signal PEM_out_ok_L, and its output terminal Q is connected to the input terminal of the NOT gate not_1, and the NOT gate not_1 The output terminal of is the output terminal of the instantaneous overpower judging unit 102, which outputs the instantaneous overpower state signal PEM_EN_L signal.

FIG. 6 is a schematic circuit diagram of an embodiment of the judging delay unit 1021 in the instantaneous overpower judging unit 102 in FIG. 5 . The judgment delay unit 1021 includes RS latches RS1, RS2, D flip-flop DFF, NOT gates not1, not2, not3, AND gate and, leading edge blanking LEB and counter. The input terminal of the not gate not1 and the first input terminal CP_L of the counter counter are connected together as the second input terminal of the judgment delay unit 1021, which is input to the internal low-voltage drive signal Drive_H of the controller; the S terminal of the RS latch RS1 is used for judging The first input terminal of the delay unit 1021 inputs the maximum duty ratio control signal PWM_Lim_L, its R terminal is connected to the output terminal of the NOT gate not1, and inputs the Drive_L signal, its output terminal Q is connected to the first input terminal D of the D flip-flop DFF connection, the second input terminal CP_L of the D flip-flop DFF is connected to the output terminal of the NOT gate not2, the input terminal of the NOT gate not2 is connected to the output terminal of the leading edge blanking LEB, and the low-voltage drive feedback signal Feedback_L inside the input controller, the leading edge blanking The input terminal of the hidden LEB is connected with the first output terminal of the frequency and duty ratio control unit 105, the drive signal GATE is input, the third input terminal Clr_L of the D flip-flop DFF is simultaneously connected with the output terminal of the AND gate and and the RS latch RS2 The R terminal of the AND gate and is connected to the output terminal of the instantaneous overpower judging unit 102, and the instantaneous overpower state signal PEM_EN_L is input, and the second input terminal of the AND gate and is used to input the internal low voltage initialization of the controller The signal ENP_lv, the output terminal Q of the D flip-flop DFF is connected to the second input terminal Clr_L of the counter counter, the output terminal Q of the counter counter is connected to the input terminal of the NOT gate not3, and the output terminal of the NOT gate not3 is connected to the RS latch RS2 The terminal S is connected, and the output terminal Q of the RS latch is the output terminal of the judgment delay unit 1021 , which outputs the judgment signal PEM_IN_H for entering the instantaneous overpower state.

FIG. 7 is a schematic circuit diagram of an embodiment of the sustain time programmable unit 103 of the present invention. The sustain time programmable unit 103 includes current sources IB ₁ and IB ₂ , capacitor C1, NMOS transistor NM1_1, comparator CMP, NAND gate nand, latch LATH, D flip-flop DFF1, NOT gates not4, not5, not6, delay Time Delay, counter counter1, AND gate and1.

The input terminal of the current source IB ₁ is used to input the low-voltage power supply VCC, and the output terminal of the current source IB ₁ is connected to the second input terminal of the maintenance time programmable unit 103 and the non-inverting input terminal of the comparator CMP at the same time; the input terminal of the current source IB ₂ The end is used to input the low-voltage power supply VCC, and the output end of the current source _IB2 is connected to the fourth input end of the programmable maintenance time unit 103, one end of the capacitor C1, the drain of the NMOS transistor NM1_1, and the inverting input end of the comparator CMP; The other end of the capacitor C1 is connected to the source and ground of the NMOS transistor NM1_1 at the same time; the gate of the NMOS transistor NM1_1 is connected to the output end of the NAND gate nand, and the first input end of the NAND gate nand is simultaneously connected to the output end of the latch LATH and the second input terminal CP_L of the D flip-flop DFF1, the second input terminal of the NAND gate nand and the third input terminal Clr_L of the D flip-flop DFF1 are connected together for inputting the internal low-voltage initialization signal ENP_lv of the controller; the latch The input end of LATH is connected with the output end of comparator CMP; The first input end D of D flip-flop DFF1 is connected with its second output end, the first output end Q of D flip-flop DFF is connected with the input end of NAND gate not4, and the non- The output terminal of the gate not4 is connected with the first input terminal CP_L of the counter counter1, the second input terminal Clr_L of the counter counter1 is connected with the output terminal of the NOT gate not5, and the input terminal of the NOT gate not5 is connected with the output of the instantaneous overpower judgment unit 102 terminal connection, this connection is used as the third input terminal of the maintenance time programmable unit 103, and inputs the instantaneous overpower state signal PEM_EN_L; the output terminal of the counter counter1 is connected to the input terminal of the NOT gate not6, and the output terminal of the NOT gate not6 outputs the instantaneous overpower The status signal PEM_out_Tkeep_ok_L is completed with the maintenance time and connected to the second input terminal of the AND gate and1, and the first input terminal of the AND gate and1 is connected to the output terminal of the delay Delay, and the input instantaneous overpower is completed with the output status. The input terminal of Delay is connected to the first output terminal of the PWM input gain and output state judging unit 104 , and this connection is used as the third input terminal of the hold time programmable unit to input and output the state signal Vout_ok_H.

With reference to Fig. 5, Fig. 6 and Fig. 7, the working principle of the embodiment of the instantaneous overpower judging unit 102 and the embodiment of the maintenance time programmable unit 103 of the present invention is briefly described as follows:

If the maximum duty ratio control signal PWM_Lim_L is always at low level for several cycles, it is judged that the controller is in the instantaneous overpower state at this time, so the instantaneous overpower judging unit 102 outputs the instantaneous overpower state signal PEM_EN_L as low level , the instantaneous overpower state signal PEM_EN_L is sent to the PWM input gain and output state judging unit 104, and within the maintenance time of the instantaneous overpower state, the output state is judged by the voltage of the FB pin of the controller to generate the output state signal Vout_ok_H, and this signal Vout_ok_H is sent to the maintenance time programmable unit 103. If the output state returns to normal, the output state signal Vout_ok_H is high level; or the maintenance time counting ends, in both cases, the instantaneous overpower state can be exited, so that the maintenance time can be programmed The unit 103 generates a signal PEM_out_ok_L for exiting the transient overpower state to be at a low level, so that the controller returns to the normal working mode.

Further, the maintenance time programmable unit 103 connects different sampling resistors R _PEM to the PEM pin of the controller, and then generates different maintenance times under the control of the instantaneous overpower state signal PEM_EN_L, so as to meet the requirements of different overpower states for maintenance time demands.

Further, the frequency and duty cycle control unit 105 outputs a current signal IFB_PEM that varies with the FB voltage, and sends it to the programmable maintenance time unit 103. Under the control of the instantaneous overpower state signal PEM_EN_L, the maintenance time can be changed with the size of the overpower multiple And change.

FIG. 8 is a schematic circuit diagram of an embodiment of the PWM input gain and output state judging unit 104 of the present invention. The PWM input gain and output state judging unit 104 includes a PWM input gain 1041 , a data selector MUX3 , a comparator CMP3 and a NOT gate not7 .

The first input end of PWM input gain 1041 is connected with the FB pin of controller, and this connection is used as the second input end of PWM input gain and output state judgment unit 104; The second input end of PWM input gain 1041 is PWM input gain and The first input end of the output state judging unit 104 inputs the PEM_EN_L signal, and is connected with the output end of the instantaneous overpower judging unit 102 and the third input end of the data selector MUX for choosing one of two; the first output end of the PWM input gain 1041 Output VFB_OLP signal, connected with the non-inverting input terminal of comparator CMP3, the second output terminal, the third output terminal and the fourth output terminal of PWM input gain 1041 are respectively used as the second output terminal of PWM input gain and output state judgment unit 104 , the third output terminal and the fourth output terminal, which respectively output VFB_PFM signal, VFB_PEM signal and VFB_PWM signal; the first input terminal of the two-to-one data selector MUX3 is used to input the internal reference voltage signal Vref1 of the controller, and the two-to-one data The second input terminal of the selector MUX3 is used to input the internal reference voltage signal Vref2 of the controller, the output terminal of the data selector MUX is connected to the negative phase input terminal of the comparator CMP, and the output terminal of the comparator CMP3 is a NAND gate The input terminal of not7 is connected, and the output terminal of the NOT gate not7 is used as the first output terminal of the PWM input gain and output state judgment unit 104 to output the Vout_ok_H signal.

FIG. 9 is a schematic circuit diagram of an embodiment of the PWM input gain 1041 in the PWM input gain and output state judging unit 104 in FIG. 8 . The PWM input gain 1041 includes a switched capacitor filter Filter, an NMOS transistor NM3, and resistors R1, R2, R3, and R4.

The input terminal of the switched capacitor filter Filter is connected to the FB pin of the controller, the first output terminal of the switched capacitor filter Filter is connected to the gate of the NMOS transistor NM3, and the second output terminal of the switched capacitor filter Filter is used as the PWM input gain The second output terminal of 1041 outputs the VFB_PFM signal; the drain of the NMOS transistor NM3 is used to connect the low-voltage power supply VCC, the source of the NMOS transistor NM3 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the resistor R2. The connection intersection is used as the first output terminal of the PWM input gain 1041, and the VFB_OLP signal is output; the other end of the resistor R2 is connected to one end of the resistor R3, and the connection intersection is used as the third output terminal of the PWM input gain 1041, and the VFB_PEM signal is output; The other end of R3 is connected to one end of resistor R4, and the junction of this connection is used as the fourth output end of PWM input gain 1041 to output VFB_PWM signal, and the other end of resistor R4 is connected to the ground of the controller.

FIG. 10 is a schematic circuit diagram of an embodiment of the frequency and duty ratio control unit 105 of the present invention. The frequency and duty ratio control unit 105 includes a voltage-controlled oscillator VCO, an AND gate and2, an RS latch RS3, and a GATE pin for driving the Driver and the controller.

The first input terminal of the voltage-controlled oscillator VCO is the third input terminal of the frequency and duty ratio control unit 105, and the PEM_EN_L signal is input, connected to the output terminal of the instantaneous overpower judgment unit 102, and the second input terminal of the voltage-controlled oscillator VCO It is the fourth input end of the frequency and duty ratio control unit 105, input the VFB_PFM signal, connected to the second output end of the PWM input gain and output state judgment unit 104, the first output end of the voltage-controlled oscillator VCO outputs the IFB_PEM signal, and The fourth input terminal of the maintenance time programmable unit 103 is connected, which is used as the third output terminal IFB_PEM of the frequency and duty cycle control unit, and the second output terminal CLK of the voltage-controlled oscillator VCO is connected to the S terminal of the RS latch , the R terminal of the RS latch RS3 is connected to the output terminal of the AND gate and2, and the PWM_off_L signal is input, and the first input terminal of the AND gate and2 is the second input terminal of the frequency and duty cycle control unit 105, and the PWM_L signal is input, and The second output terminal of the peak current sampling unit 101 is connected, and the second input terminal of the gate and2 is the first input terminal of the frequency and duty ratio control unit 105, and the PWM_Lim_L signal is input, and the first output terminal of the peak current sampling unit 101 connected, the output end of the RS latch RS3 outputs the Drive_H signal, which is connected to the input end of the driver, and this connection is used as the second output end of the frequency and duty ratio control unit 105, and the output end of the driver driver is connected to the GATE lead of the controller. The pin is connected as the first output end of the frequency and duty ratio control unit 105 .

It should be noted that the structure of the voltage-controlled oscillator is common knowledge of those skilled in the art. The common structure is a voltage input differential pair, which controls the transconductance amplifier to generate a changing current. This current is used to charge and discharge the capacitor combined with the voltage comparator to generate changes. frequency. The function of the voltage controlled oscillator in the embodiment of the present invention is to generate a maximum operating frequency that varies with the voltage signal VFB_PFM when the instantaneous overpower state signal PEM_EN_L is valid, so as to meet the requirements of different overpower multiples for the maximum operating frequency.

With reference to Fig. 8, Fig. 9 and Fig. 10, the working principles of the PWM input gain and output state judging unit 104 and the frequency and duty ratio control unit 105 of the present invention are described as follows:

The FB pin of the controller generates voltage signals VFB_PFM, VFB_OLP, VFB_PEM, and VFB_PWM that vary with the FB voltage through the switched capacitor filter Filter and the voltage dividing resistors R1 to R4. The voltage signal VFB_PFM is sent to the frequency and duty ratio control unit 105 to generate a current signal IFB_PEM that changes with the FB voltage, and controls the maximum operating frequency of its internal voltage-controlled oscillator VCO to adapt to the maximum operating frequency of different overpower multiples frequency requirements. The voltage signal VFB_OLP is compared with the reference voltage inside the controller (select Vref1 or Vref2 according to the PEM_EN_L signal, when the PEM_EN_L signal is high, select Vref1; when the PEM_EN_L signal is low, select Vref2; Vref1>Vref2), used An output state signal Vout_ok_H is generated; voltage signals VFB_PEM and VFB_PWM are sent to the peak current sampling unit 101 for generating a duty ratio control signal PWM_L in normal mode.

Further, the frequency and duty ratio control unit 105 outputs the current IFB_PEM that changes with the FB voltage, and sends it to the maintenance time programmable unit 103. Under the control of the instantaneous overpower state signal PEM_EN_L, the maintenance time is changed with the size of the overpower multiple .

Further, the instantaneous overpower state signal PEM_EN_L is sent to the PWM input gain and output state judging unit 104. During the maintenance time of the instantaneous overpower state, the output state is judged by the FB pin voltage of the controller to generate the output state signal Vout_ok_H, which will be This signal Vout_ok_H is sent to the maintenance time programmable unit 103. If the output state returns to normal, then Vout_ok_H is at a high level; or the maintenance time counting ends, in both cases, the instantaneous overpower state can be exited, so that the maintenance time programmable unit The exit transient overpower state signal PEM_out_ok_L generated by 103 is at low level, so that the controller returns to the normal working mode.

FIG. 11 is a schematic diagram of signal waveforms related to a large dynamic load and an instantaneous overpower state of a flyback converter to which the instantaneous overpower control circuit 100 of the present invention is applied. Combined with Figure 1, the analysis is as follows:

Iout is the output load current, 10% Io means 10% load; 100% Io means 100% load, usually we call it full load; 400% Io means 4 times full load, that is, 4 times overpower. VFB represents the voltage of the FB pin of the controller; VCS represents the voltage of the CS pin of the controller; PEM_EN_L is the output signal of the instantaneous overpower judging unit 102; GATE is the output signal of the frequency and duty cycle control unit 105.

It can be seen from Figure 11 that in the case of a normal large dynamic load jump of 10% Io ~ 100% Io ~ 10%, the VCS voltage is lower than the maximum peak current limit threshold Vref_Lim1 in normal mode, and the instantaneous overpower state will not be triggered , that is, the instantaneous overpower state signal PEM_EN_L is high level; when jumping between normal load and instantaneous overpower, that is, in the case of 10% Io ~ 400% Io ~ 10% Io, the VCS voltage will be higher than the maximum in normal mode The peak current limit threshold Vref_Lim1 will normally enter the instantaneous overpower state, that is, the instantaneous overpower state signal PEM_EN_L is at low level.

Further, comparing before and after the instantaneous overpower state, it can be found that the operating frequency and peak current of the controller will both increase when PEM_EN_L is at an effective low level (the increase in the operating frequency of the controller is reflected in the interval time between the high level of the GATE signal Shorten, the increase of peak current is reflected in the increase of VCS voltage), and then meet the demand of instantaneous overpower. When PEM_EN_L is at a high level, it can exit the instantaneous overpower state and return to the normal working mode. At this time, the working frequency and peak current of the controller return to normal.

As shown in FIG. 12 , a waveform diagram of signals related to system simulation of a large dynamic load and an instantaneous overpower state of a flyback converter applying the instantaneous overpower control circuit 100 of the present invention is shown. Combined with Figure 1, the analysis is as follows:

Vout is the output voltage of the flyback converter, Iout is the output load current of the flyback converter, VFB is the voltage of the FB pin of the controller; VCS is the voltage of the CS pin of the controller; PEM_EN_L is the output signal of the instantaneous overpower judging unit 102 ; GATE is the output signal of the frequency and duty ratio control unit 105 .

It can be seen from Figure 12 that when switching from a normal load to an instantaneous overpower state, due to the rapid increase of the peak current and operating frequency, the transient response of the system is very fast, and the output voltage Vout of the system loses less than 10%; while in In the case of a normal large dynamic load jump, the system will not enter the instantaneous overpower state, and the system's overshoot and undershoot are very small; at the same time, after the instantaneous overpower load returns to the normal load, the system normally jumps out of the instantaneous overpower state, and the output of the system The overshoot of the voltage Vout is also very small, which meets the requirements of the system index.

FIG. 13 is a schematic circuit diagram of another embodiment of the data selector MUX1011 in the peak current sampling unit 101 in FIG. 3 . The difference from Figure 3 is that the NMOS tubes NM1 and NM2 are replaced by transmission gates Transgate1 and Transgate2. The specific connection relationship is as follows:

The input terminal of the transmission gate Transgate1 is used as the first input terminal Vin1 of the two-to-one data selector 1011, the output terminal of the transmission gate Transgate1 is connected to the output terminal of the transmission gate Transgate2, and the junction of this connection is used as the output of the two-to-one data selector 1011 Terminal Vout; the positive phase control terminal of the transmission gate Transgate1 is connected with the negative phase control terminal of the transmission gate Transgate2 and the output terminal of the not gate not8 at the same time; the negative phase control terminal of the transmission gate Transgate1 is connected with the normal phase control terminal and the non The input terminal of the gate not8 is connected, and the junction of this connection serves as the third input terminal Vin3 of the one-of-two data selector 1011 ; the input terminal of the transmission gate Transgate2 serves as the second input terminal Vin2 of the one-two data selector 2011 .

Because when the low-voltage power supply VCC=5V is selected, the data selector can make the NMOS transistors NM1 and NM2 work in the linear region, but if the low-voltage power supply VCC=3V is selected, then for Vin1 and Vin2 at a relatively high level , can no longer use the NMOS tube, because the NMOS tube works in the saturation region, the input voltage Vin1 or Vin2 will not be normally transmitted to the output Vout, affecting the transmission effect. Then, in the embodiment of this two-to-one data selector, the transmission gate Transgate1 (conventional structure is a PMOS transistor and an NMOS transistor, its gate is respectively connected to two control signals with opposite potentials, and its drain and source Respectively in parallel) and Transgate2 to replace the NMOS transistors NM1 and NM2 in Figure 4, even if the low-voltage power supply VCC=3V is selected, the PMOS transistor in the transmission gate can also work in the linear region, so that the input voltage Vin1 or Vin2 is relatively high In the case of a certain level value, it can also be transmitted to the output Vout normally, ensuring the reliability and effectiveness of the transmission.

The above are only preferred embodiments of the present invention, and it should be noted that the above preferred embodiments should not be regarded as limiting the present invention, and it should also be recognized that the present invention can be applied in other wider scopes. According to the above content of the present invention, using common technical knowledge and conventional means in this field, without departing from the above-mentioned basic technical idea of the present invention, the present invention can also make other modifications, replacements or changes in various forms, all falling within the scope of the present invention. Within the protection scope of the present invention.

Claims (15)

1. A method for instantaneous overpower control, applied to a power converter, wherein the power converter includes a power tube and a controller, wherein the control method comprises the following steps: The peak current sampling step is detected by the CS pin of the controller to generate a voltage signal VCS that varies with the source voltage when the power transistor is turned on; The PWM input gain and output state judgment step is to generate the voltage signal VFB_PFM, voltage signal VFB_PEM and voltage signal VFB_PWM that change with the output voltage of the power converter through the detection of the FB pin of the controller, and the output that reflects the output overpower of the power converter Status signal Vout_ok_H; In the peak current sampling step, it is also selected to compare the obtained voltage signal VCS with the voltage signal VFB_PEM or the voltage signal VFB_PWM to generate a duty cycle control signal PWM_L; and also select to compare the obtained voltage signal VCS with the first threshold Vref_Lim1 or the first threshold Comparing the two thresholds Vref_Lim2 to generate the maximum duty cycle control signal PWM_Lim_L; The instantaneous overpower judging step is to generate an instantaneous overpower state signal PEM_EN_L according to the maximum duty cycle control signal PWM_Lim_L; The maintenance time programmable step is to generate the maintenance time of the over-power state according to the instantaneous over-power state signal PEM_EN_L; and to generate the exit instantaneous over-power state signal PEM_out_ok_L according to the instantaneous over-power state signal PEM_EN_L and the output state signal Vout_ok_H; The frequency and duty cycle control step generates the drive signal GATE, the low-voltage drive signal Drive_H and The current signal IFB_PEM that changes with the output voltage of the power converter; at the same time, the first operating frequency of the controller operating in the normal operating mode or the second operating frequency in the instantaneous over-power mode is selected according to the instantaneous over-power state signal PEM_EN_L and the voltage signal VFB_PFM ; Among them, Vref_Lim1﹤Vref_Lim2, the first working frequency﹤the second working frequency, the second working frequency changes with the voltage signal VFB_PFM; Each step also includes switching the working mode of the controller according to the following control logic; When VCS≤Vref_Lim1 or although VCS>Vref_Lim1, but the duration is less than N cycles, the maximum duty cycle control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both at high level, and the controller is working in the normal working mode, select the voltage The signal VCS is compared with the first threshold Vref_Lim1 to select the controller to work at the first working frequency; When VCS>Vref_Lim1 lasts for more than N cycles, the maximum duty cycle control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both low, the controller works in the instantaneous overpower mode, and the voltage signal VCS and the second Threshold Vref_Lim2 compares and selects the controller to work at the second working frequency; When the instantaneous overpower state signal PEM_EN_L is low level, if the output state of the power converter returns to normal, the output state signal Vout_ok_H is high level; when the maintenance time is over or the output state signal Vout_ok_H is high level, the instantaneous overpower The status signal PEM_out_ok_L is low level, and the controller returns to the normal working mode at this time; Where N is a set positive integer. 2. The control method according to claim 1, characterized in that: the higher the overpower multiple output by the power converter is, the higher the second operating frequency is. 3. The control method according to claim 1, characterized in that: the length of the maintenance time is set through the PEM pin of the controller, and the higher the overpower multiple output by the power converter is, the shorter the maintenance time is. 4. An instantaneous overpower control circuit applied to a power converter, the power converter comprising a power tube and a controller, characterized in that the control circuit comprises: a peak current sampling unit, an instantaneous overpower judging unit , Maintenance time programmable unit, PWM input gain and output state judgment unit and frequency and duty cycle control unit; The peak current sampling unit is detected by the CS pin of the controller to generate a voltage signal VCS that changes with the source voltage when the power transistor is turned on; The PWM input gain and output state judgment unit generates voltage signals VFB_PFM, voltage signal VFB_PEM, and voltage signal VFB_PWM that vary with the output voltage of the power converter through the detection of the FB pin of the controller, and the output that reflects the output overpower of the power converter Status signal Vout_ok_H; The peak current sampling unit also selects to compare the obtained voltage signal VCS with the voltage signal VFB_PEM or voltage signal VFB_PWM to generate a duty ratio control signal PWM_L; and also selects to compare the obtained voltage signal VCS with the first threshold Vref_Lim1 or the first threshold Vref_Lim1 Comparing the two thresholds Vref_Lim2 to generate the maximum duty cycle control signal PWM_Lim_L; The instantaneous overpower judging unit generates an instantaneous overpower state signal PEM_EN_L according to the maximum duty ratio control signal PWM_Lim_L; The maintenance time programmable unit generates the maintenance time of the over-power state according to the instantaneous over-power state signal PEM_EN_L; also generates the exiting instantaneous over-power state signal PEM_out_ok_L according to the instantaneous over-power state signal PEM_EN_L and the output state signal Vout_ok_H; The frequency and duty cycle control unit generates the drive signal GATE, the internal low voltage drive signal Drive_H and The current signal IFB_PEM that changes with the output voltage of the power converter; at the same time, the first operating frequency of the controller operating in the normal operating mode or the second operating frequency in the instantaneous over-power mode is selected according to the instantaneous over-power state signal PEM_EN_L and the voltage signal VFB_PFM ; Among them, Vref_Lim1﹤Vref_Lim2, the first working frequency﹤the second working frequency, the second working frequency changes with the voltage signal VFB_PFM; Each circuit unit also realizes the switching of the working mode of the controller according to the following control logic; When VCS≤Vref_Lim1 or although VCS>Vref_Lim1, but the duration is less than N cycles, the maximum duty ratio control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both at high level, the controller works in the normal working mode, and the peak current The sampling unit selection voltage signal VCS is compared with the first threshold Vref_Lim1, and the frequency and duty cycle control unit selection controller works at the first operating frequency; When VCS>Vref_Lim1 lasts for more than N periods, the maximum duty ratio control signal PWM_Lim_L and the instantaneous overpower state signal PEM_EN_L are both low, the controller works in the instantaneous overpower mode, and the peak current sampling unit selects the voltage signal VCS is compared with the second threshold Vref_Lim2, and the frequency and duty cycle control unit selects the controller to work at the second operating frequency; When the instantaneous overpower state signal PEM_EN_L is low level, if the output state of the power converter returns to normal, the output state signal Vout_ok_H is high level, and when the maintenance time ends or the output state signal Vout_ok_H is high level, the instantaneous overpower The status signal PEM_out_ok_L is low level, and the controller returns to the normal working mode at this time; Where N is a set positive integer. 5. The control circuit according to claim 4, characterized in that the higher the overpower multiple output by the power converter is, the higher the second operating frequency is. 6. The control circuit according to claim 4, characterized in that: the length of the holding time is set through the PEM pin of the controller, and the higher the overpower multiple output by the power converter is, the shorter the holding time is. 7. The control circuit according to claim 4, characterized in that: the peak current sampling unit comprises a two-to-one data selector MUX1, a two-to-one data selector MUX2, a comparator CMP1, a comparator CMP2; The negative phase input terminal of CMP1 is used to connect the CS pin of the controller, and at the same time, it is connected with the negative phase input terminal of the comparator CMP2, and the positive phase input terminal is connected with the output terminal of the two-to-one data selector MUX1, and the output terminal is in duty Ratio control signal PWM_L; the first input terminal input voltage signal VFB_PWM of the two data selector MUX1, the second input terminal input voltage signal VFB_PEM, the third input terminal is connected with the third input terminal of the two data selector MUX2 Input the instantaneous overpower state signal PEM_EN_L together; the first input terminal of the two-choice data selector MUX2 inputs the first threshold value Vref_Lim1, the second input terminal inputs the second threshold value Vref_Lim2, and the output terminal is connected to the non-inverting input terminal of the comparator CMP2; The output terminal of the comparator CMP2 outputs the maximum duty ratio control signal PWM_Lim_L. 8. The instantaneous overpower control circuit according to claim 7, characterized in that: said one-of-two data selector MUX1 comprises NMOS transistor NM1, NMOS transistor NM2 and NOT gate, and the drain of NMOS transistor NM1 serves as two The first input end of the one-to-one data selector MUX1, the source of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM2, and the junction of this connection is used as the output end of the two-to-one data selector MUX1; the gate of the NMOS transistor NM1 is connected to the The input terminal of the NOT gate is connected, and the junction of this connection is used as the third input terminal of the data selector MUX1; the output terminal of the NOT gate is connected to the gate of the NMOS transistor NM2, and the drain of the NMOS transistor NM2 is used as the second selection A second input terminal of a data selector. 9. The instantaneous overpower control circuit according to claim 7, characterized in that: said two-choice data selector MUX1 comprises transmission gate Transgate1, transmission gate Transgate2 and NOT gate not, and the input end of transmission gate Transgate1 is used as two Select the first input end of the data selector MUX1, the output end of the transmission gate Transgate1 is connected with the output end of the transmission gate Transgate2, and this connection intersection is used as the output end of the two data selector MUX1; the forward control of the transmission gate Transgate1 end is connected with the input end of the NOT gate not, and the junction of this connection is used as the third input end of the data selector MUX1; the output terminal of the NOT gate not is connected with the positive control end of the transmission gate Transgate2, and the input of the transmission gate Transgate2 The terminal is used as the second input terminal of the one-of-two data selector. 10. The instantaneous overpower control circuit according to claim 4, characterized in that: said instantaneous overpower judging unit comprises a judging delay unit, an RS latch and a NOT_1; the judging delay unit is based on the first input The maximum duty cycle control signal PWM_Lim_L input at the second input terminal, the internal low-voltage drive signal Drive_H of the controller input at the second input terminal, and the drive signal GATE input at the third input terminal generate a judgment signal PEM_IN_H for entering the instantaneous overpower state, which is output to RS The S terminal of the latch, the R terminal of the RS latch input and exit the instantaneous overpower state signal PEM_out_ok_L, the output terminal Q of the RS latch is connected to the input terminal of the NOT gate not_1, and the output terminal of the NOT gate not_1 outputs the instantaneous overpower Status signal PEM_EN_L. 11. The instantaneous overpower control circuit according to claim 10, characterized in that: said judgment delay unit comprises RS latch RS1, RS latch RS2, D flip-flop DFF, NOT gate not1, NOT gate not2, not gate not3, AND gate and, leading edge blanking LEB and counter counter; the S terminal of the RS latch RS1 inputs the maximum duty cycle control signal PWM_Lim_L, and the R terminal is connected to the output terminal of the NOT gate not1, and the output terminal of the NOT gate not1 After the input terminal is connected with the first input terminal CP of the counter counter, the low-voltage driving signal Drive_H inside the controller is input, the output terminal Q of the RS latch RS1 is connected with the first input terminal D of the D flip-flop DFF, and the D flip-flop DFF The second input terminal CP is connected to the output terminal of the NOT gate not2, the input terminal of the NOT gate not2 is connected to the output terminal of the leading edge blanking LEB, the input terminal of the leading edge blanking LEB inputs the driving signal GATE, and the third input of the D flip-flop DFF The terminal Clr_L is connected to the output terminal of the AND gate and and the R terminal of the RS latch RS2 at the same time, the first input terminal of the AND gate and inputs the instantaneous overpower state signal PEM_EN_L, and the second input terminal of the AND gate and is used for inputting the controller The internal low-voltage initialization signal ENP_lv, the output terminal Q of the D flip-flop DFF is connected to the second input terminal Clr_L of the counter counter, the output terminal Q of the counter counter is connected to the input terminal of the NOT gate not3, and the output terminal of the NOT gate not3 is connected to the RS lock The terminal S of the register RS2 is connected, and the output terminal Q of the RS latch RS2 outputs a judgment signal PEM_IN_H for entering an instantaneous overpower state. 12. The instantaneous overpower control circuit according to claim 4, characterized in that: the programmable holding time unit includes a current source IB ₁ , a current source IB ₂ , a capacitor C1, an NMOS transistor NM1_1, a comparator CMP, and NOT gate nand, latch LATH, D flip-flop DFF1, NOT gate not4, NOT gate not5, NOT gate not6, delay Delay, and AND gate and1; The input terminal of the current source IB ₁ is used to connect to the low-voltage power supply VCC, and the output terminal is used to connect to the PEM pin of the controller. The output terminal of the current source IB ₁ is also connected to the non-inverting input terminal of the comparator CMP; the current source IB ₂ The input end of the current source IB2 is used to connect the low-voltage power supply VCC _, the output end inputs the current signal IFB_PEM, and the output end of the current source _IB2 is also connected to one end of the capacitor C1, the drain of the NMOS transistor NM1_1, and the inverting input end of the comparator CMP ; The other end of the capacitor C1 is simultaneously connected to the source of the NMOS transistor NM1_1 and the ground of the controller; the gate of the NMOS transistor NM1_1 is connected to the output end of the NAND gate nand, and the first input end of the NAND gate nand is simultaneously connected to the latch The output terminal of the device LATH is connected to the second input terminal CP of the D flip-flop DFF1, and the second input terminal of the NAND gate nand is connected to the third input terminal Clr_L of the D flip-flop DFF1 for low-voltage initialization inside the input controller Signal ENP_lv; the input terminal of the latch LATH is connected to the output terminal of the comparator CMP; the first input terminal D of the D flip-flop DFF1 is connected to the second output terminal of the D flip-flop

Connection, the first output terminal Q of the D flip-flop DFF1 is connected with the input terminal of the NOT gate not4, the output terminal of the NOT gate not4 is connected with the first input terminal CP_L of the counter counter1, and the second input terminal Clr_L of the counter counter1 is connected with the NOT gate not5 The output terminal of the NOT gate not5 is connected to the input terminal of the instantaneous overpower state signal PEM_EN_L; the output terminal of the counter counter1 is connected to the input terminal of the NOT gate not6, and the output terminal of the NOT gate not6 is connected to the second input terminal of the AND gate and1. The first input terminal of the AND gate and1 is connected to the output terminal of the delay Delay, and the input terminal of the delay Delay inputs and outputs the state signal Vout_ok_H. 13. The instantaneous overpower control circuit according to claim 4, characterized in that: said PWM input gain and output state judging unit comprises a PWM input gain, a two-to-one data selector MUX3, a comparator CMP3, and a not7 ; The first input end of the PWM input gain is used to connect the FB pin of the controller, and the second input end of the PWM input gain is connected to the third input end of the data selector MUX3 to input the instantaneous overpower state signal PEM_EN_L, The first output terminal of the PWM input gain is connected to the non-inverting input terminal of the comparator CMP3, and the second output terminal, the third output terminal and the fourth output terminal of the PWM input gain respectively output the voltage signal VFB_PFM, the voltage signal VFB_PEM and the voltage signal VFB_PWM ; The first input end of the data selector MUX3 is used to input the first reference voltage signal Vref1 inside the controller, and the second input end of the data selector MUX3 is used to input the second reference inside the controller The voltage signal Vref2, the output terminal of the two-choice data selector MUX3 is connected to the negative phase input terminal of the comparator CMP3, the output terminal of the comparator CMP3 is connected to the input terminal of the NOT gate not7, and the output terminal of the NOT gate not7 outputs an output status signal Vout_ok_H. 14. The instantaneous overpower control circuit according to claim 13, characterized in that: the PWM input gain comprises a switched capacitor filter Filter, an NMOS transistor NM3, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; a switched capacitor The input terminal of the filter Filter is used to connect the FB pin of the controller, the first output terminal of the switched capacitor filter Filter is connected to the gate of the NMOS transistor NM3, and the second output terminal of the switched capacitor filter Filter outputs a voltage signal VFB_PFM; The drain of the NMOS transistor NM3 is used to connect the low-voltage power supply VCC, the source of the NMOS transistor NM3 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, and the junction of this connection is connected to the positive phase input of the comparator CMP3 end; the other end of the resistor R2 is connected to one end of the resistor R3, and the output voltage signal VFB_PEM is connected at the junction; the other end of the resistor R3 is connected to one end of the resistor R4, and the voltage signal VFB_PWM is output at the junction, and the other end of the resistor R4 is connected to Controller ground. 15. The instantaneous overpower control circuit according to claim 4, characterized in that: the frequency and duty ratio control unit comprises a voltage-controlled oscillator VCO, an AND gate and2, an RS latch RS3 and a driver; The first input terminal of the voltage-controlled oscillator VCO inputs the instantaneous overpower state signal PEM_EN_L, the second input terminal of the voltage-controlled oscillator VCO inputs the voltage signal VFB_PFM, the first output terminal of the voltage-controlled oscillator VCO outputs the current signal IFB_PEM, and the voltage-controlled oscillation The second output terminal of the device VCO is connected to the S terminal of the RS latch RS3, the R terminal of the RS latch is connected to the output terminal of the AND gate and2, and the first input terminal of the AND gate and2 inputs the duty cycle control signal PWM_L, The second input terminal of the AND gate and inputs the maximum duty cycle control signal PWM_Lim_L, and the output terminal Q of the RS latch RS3 is connected to the input terminal of the driver. This connection point outputs the internal low-voltage drive signal Drive_H of the controller to drive the Driver. The output terminal outputs the driving signal GATE.

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