CN211348702U - A Micro-ring Integrated Arrayed Waveguide Grating Wavelength Division Multiplexer - Google Patents
A Micro-ring Integrated Arrayed Waveguide Grating Wavelength Division Multiplexer Download PDFInfo
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Abstract
本实用新型涉及一种微环集成的阵列波导光栅波分复用器,属于半导体光信号传输技术领域。该微环集成的阵列波导光栅波分复用器,从下至上包括硅衬底、隔离层、波导层、上包层、加热电极和电极引线,所述波导层包括阵列波导光栅、若干个传输波导和若干个微环谐振滤波器,阵列波导光栅中设有若干个输出波导,每个输出波导均通过一个传输波导连接一个微环谐振滤波器,阵列波导光栅中若干个输出波导依次通过若干个传输波导连接若干个微环谐振滤波器组成微环集成的阵列波导光栅波分复用器。本实用新型不但能够通过AWG进行一次滤波、微环谐振滤波器进行二次滤波得到优异的串扰特性,同时确保器件的总损耗与单个AWG相当。
The utility model relates to a micro-ring integrated arrayed waveguide grating wavelength division multiplexer, which belongs to the technical field of semiconductor optical signal transmission. The micro-ring integrated arrayed waveguide grating wavelength division multiplexer includes, from bottom to top, a silicon substrate, an isolation layer, a waveguide layer, an upper cladding layer, a heating electrode and electrode leads, and the waveguide layer includes an arrayed waveguide grating, a number of transmission A waveguide and several micro-ring resonant filters, the arrayed waveguide grating is provided with several output waveguides, each output waveguide is connected to a micro-ring resonant filter through a transmission waveguide, and several output waveguides in the arrayed waveguide grating pass through several The transmission waveguide is connected with several micro-ring resonant filters to form a micro-ring integrated arrayed waveguide grating wavelength division multiplexer. The utility model can not only perform primary filtering by AWG and secondary filtering by a micro-ring resonant filter to obtain excellent crosstalk characteristics, but also ensure that the total loss of the device is equivalent to that of a single AWG.
Description
技术领域technical field
本实用新型涉及一种微环集成的阵列波导光栅波分复用器,属于半导体光信号传输技术领域。The utility model relates to a micro-ring integrated arrayed waveguide grating wavelength division multiplexer, which belongs to the technical field of semiconductor optical signal transmission.
背景技术Background technique
光纤的产生和发展,使得长距离、大容量光通信得以实现。由光通信的传输损耗低、带宽宽、抗电磁干扰、传输质量好、保密性好等特点,广受人们青睐。现计算机和多媒体通信等技术进步,信息传输量与日俱增,促进了光通信技术朝着大容量、长距离、波分复用、光纤技术、光放大等方向发展。波分复用器是波分复用技术的关键器件,也是光纤通信系统中的关键器件。光波分复用器是对光波波长进行分离与合成的器件。与CMOS技术兼容的硅光子技术快速发展,硅光子器件具有小尺寸和低功耗的特点,且能够跟IC器件进行单片集成,可实现大规模生产和多功能集成。SOI材料有着优异的光学性能且与COMS集成电路工艺兼容,可降低光子集成器件成本,因此硅基绝缘(SOI)COMS硅光子技术是现光纤通信领域的研究热点。SOI基片作为波导芯层的硅与埋氧层SiO2之间的折射率差高达40%,可以在波导中实现强光学限制。目前硅光子中4种波分复用器有:刻蚀衍射光栅(EDG)、微环谐振滤波器(MRR)、级联MZI和阵列波导光栅(AWG)。其中刻蚀衍射光栅无法实现密集波分复用,适用范围有一定的限制;微环谐振滤波器利用谐振波长实现解复用,需级联不同半径的微环,受工艺影响,稳定的波长间隔较难控制,一般需要对微环热调谐,增加了功耗;MZI通过臂长差实现波分复用,通道数较多时,随着级联次数的增加,芯片尺寸会成倍增加,不适宜通道数较多的解复用。因此三种硅光子器件未在波分复用领域广泛应用。硅光子阵列波导光栅是一种综合性能最优的波分复用/解复用器,在许多密集波分复用(DWDM)系统和模块中有重要的地位。目前基于二氧化硅波导的商用AWG已经实现了几百个通道数,通道间隔可达1GHz。随着技术的发展,传输速率和器件功耗的要求越来越严格,虽然硅光子器件集成度高、尺寸小,但也限制了一些关键器件的性能。硅光AWG的串扰主要来自于器件尺寸极度减小后响应谱受阵列波导宽度影响极大,导致AWG器件的串扰性能不佳,无法大规模应用。The generation and development of optical fibers have enabled long-distance, large-capacity optical communications to be realized. Due to the characteristics of low transmission loss, wide bandwidth, anti-electromagnetic interference, good transmission quality and good confidentiality of optical communication, it is widely favored by people. With the advancement of technology such as computer and multimedia communication, the amount of information transmission is increasing day by day, which promotes the development of optical communication technology in the direction of large capacity, long distance, wavelength division multiplexing, optical fiber technology, and optical amplification. The wavelength division multiplexer is the key component of the wavelength division multiplexing technology and also the key component in the optical fiber communication system. Optical wavelength division multiplexer is a device that separates and combines wavelengths of light waves. Silicon photonics technology compatible with CMOS technology is developing rapidly. Silicon photonics devices have the characteristics of small size and low power consumption, and can be monolithically integrated with IC devices, enabling large-scale production and multi-functional integration. SOI materials have excellent optical properties and are compatible with CMOS integrated circuit technology, which can reduce the cost of photonic integrated devices. Therefore, silicon-on-insulator (SOI) CMOS silicon photonics technology is a research hotspot in the field of optical fiber communication. The refractive index difference between the silicon of the SOI substrate as the core layer of the waveguide and the buried oxide layer SiO2 is as high as 40%, which can achieve strong optical confinement in the waveguide. There are currently four wavelength division multiplexers in silicon photonics: etched diffraction grating (EDG), micro-ring resonator (MRR), cascaded MZI and arrayed waveguide grating (AWG). Among them, the etched diffraction grating cannot achieve dense wavelength division multiplexing, and the scope of application is limited; the micro-ring resonant filter uses the resonant wavelength to achieve demultiplexing, and needs to cascade micro-rings of different radii, which are affected by the process and have a stable wavelength interval. It is difficult to control, and generally requires thermal tuning of the microring, which increases power consumption; MZI realizes wavelength division multiplexing through the difference in arm length. When the number of channels is large, with the increase of the number of cascades, the chip size will increase exponentially, which is not suitable Demultiplexing with a larger number of channels. Therefore, the three silicon photonic devices are not widely used in the field of wavelength division multiplexing. Silicon photonic arrayed waveguide grating is a wavelength division multiplexer/demultiplexer with the best comprehensive performance, which plays an important role in many dense wavelength division multiplexing (DWDM) systems and modules. At present, commercial AWGs based on silica waveguides have achieved hundreds of channels, and the channel spacing can reach 1GHz. With the development of technology, the requirements for transmission rate and device power consumption are becoming more and more stringent. Although silicon photonics devices are highly integrated and small in size, they also limit the performance of some key devices. The crosstalk of silicon photonic AWG mainly comes from the fact that the response spectrum is greatly affected by the width of the arrayed waveguide after the device size is extremely reduced, resulting in poor crosstalk performance of AWG devices, which cannot be applied on a large scale.
发明内容SUMMARY OF THE INVENTION
针对上述现有技术存在的问题及不足,本实用新型提供一种微环集成的阵列波导光栅波分复用器。本实用新型通过在硅光AWG输出端集成微环谐振滤波器实现二次滤波。通过对波长调谐系统的操作,调节微环谐振滤波器的谐振波长,使谐振波长与其连接的硅光AWG输出通道对应输出波长一致,从而能够对阵列波导光栅输出波长信号进一步滤波,实现低串扰特性,有效解决硅光AWG器件串扰性能不佳的问题,本实用新型通过以下技术方案实现。Aiming at the above problems and deficiencies in the prior art, the utility model provides an arrayed waveguide grating wavelength division multiplexer integrated with a micro-ring. The utility model realizes secondary filtering by integrating a micro-ring resonant filter at the output end of the silicon photonic AWG. Through the operation of the wavelength tuning system, the resonant wavelength of the micro-ring resonator filter is adjusted so that the resonant wavelength is consistent with the corresponding output wavelength of the silicon-optical AWG output channel connected to it, so that the output wavelength signal of the arrayed waveguide grating can be further filtered to achieve low crosstalk characteristics. , effectively solve the problem of poor crosstalk performance of silicon photonic AWG devices, the utility model is realized by the following technical solutions.
一种微环集成的阵列波导光栅波分复用器,从下至上包括硅衬底、隔离层、波导层、上包层、加热电极和电极引线,所述波导层包括阵列波导光栅110、若干个传输波导120和若干个微环谐振滤波器130,阵列波导光栅110中设有若干个输出波导5,每个输出波导5均通过一个传输波导120连接一个微环谐振滤波器130,阵列波导光栅110中若干个输出波导5依次通过若干个传输波导120连接若干个微环谐振滤波器130组成微环集成的阵列波导光栅波分复用器。A micro-ring integrated arrayed waveguide grating wavelength division multiplexer, from bottom to top, includes a silicon substrate, an isolation layer, a waveguide layer, an upper cladding layer, a heating electrode and electrode leads, and the waveguide layer includes an
所述阵列波导光栅110包括输入波导1、输入平板波导2、阵列波导3、输出平板波导4和输出波导5,输入波导1连接输入平板波导2,输入平板波导2通过阵列波导3连接输出平板波导4,输入平板波导2和输出平板波导4设置成罗兰圆结构,输出平板波导4连接输出波导5。The
所述输入波导1与输出波导5数目为任意正整数,输出波导5数目根据波分复用需要为任意正整数,阵列波导3数目由器件结构设计确定。The number of the
所述微环谐振滤波器130包括输入直波导131、环形谐振腔132、波长调谐结构11和输出直波导133,输入直波导131和位于输入直波导131下部的环形谐振腔132间存在第一耦合区10,输出直波导133和位于输出直波导133上部的环形谐振腔132间存在第二耦合区12。The
所述微环谐振滤波器130的自由光谱仪区FSR要大于阵列波导光栅110的相邻通道间隔。The FSR of the free spectrometer region of the
所述微环谐振滤波器130每个微环谐振滤波器的谐振波长必须与相连的阵列波导光栅110输出波导5输出的光信号中心波长相同或相近。The resonant wavelength of each micro-ring resonant filter of the
所述微环谐振滤波器130的输入直波导131分为输入直波导输入端6和输入直波导直输出端7,输出直波导133分为输出直波导下载端8和输出直波导上载端9。不同波长的光信号从输入直波导131的输入端6输入,在第一耦合区10耦合进入环形谐振腔132,光信号在环形谐振腔132传输时,仅满足谐振条件的波长在环中引起谐振并在第二耦合区12耦合进入输出直波导133,并从下载端8输出。The input
所述微环谐振滤波器130的波长调谐结构11为作用在环形谐振腔132上连接驱动电源的加热器,位于波导层且由离子(Ni离子)掺杂形成(NiSi),或者位于波导的SiO2上包层由高电阻材料(TiN或TaN等)构成。基于热光/电光效应的波长调谐结构11在驱动电源作用下,可以改变微环谐振滤波器130的谐振波长,使其与阵列波导光栅110输出通道对应输出光信号波长一致,实现信号的二次滤波。The
本微环集成的阵列波导光栅波分复用器的工作原理为:基于阵列波导光栅的原理,一束含多个波长的光信号从阵列波导光栅110的输入波导1进入输入平板波导2,在平板波导中衍射以等相位耦合进入阵列波导3,由于相邻阵列波导3间存在固定长度差,不同波长的光经阵列波导3传输后聚焦在输出平板波导4的不同位置,经输出波导5的每个输出端口将通道间隔一定(Δλ)的波长信号输出,实现第一次滤波。由于制备工艺等原因,实际相邻信道之间存在串扰。为降低这部分串扰,在阵列波导光栅输出端集成微环谐振滤波器130,经阵列波导光栅110AWG输出并与环形谐振腔产生作用的波长信号由微环谐振滤波器130的输出直波导下载端9输出,实现二次滤波,达到降低串扰的目的。为确保二次滤波,需要使微环谐振波长与阵列波导光栅110输出光信号波长对应一致。通过热光/电光效应可以改变微环谐振滤波器的波导折射率,从而对谐振波长进行调制,保证微环谐振滤波器的谐振波长与AWG输出端的波长一致。为确保该方案的可行性,还需对微环谐振滤波器130的自由光谱区(FSR)进行设计,使其自由光谱区(FSR)大于阵列波导光栅10输出信号的通道间隔(Δλ)。由于微环谐振器的插入损耗极低,因此,此器件的总损耗与单个AWG器件近似,能够在取得优异低串扰特性的结果下不明显增大器件总体损耗。The working principle of the arrayed waveguide grating wavelength division multiplexer integrated with the microring is as follows: based on the principle of the arrayed waveguide grating, a beam of optical signals with multiple wavelengths enters the
所述微环集成的阵列波导光栅波分复用器工艺流程图如图4所示。采用半导体SOI晶圆,基于CMOS制作工艺,主要集成工艺流程如下。The process flow diagram of the arrayed waveguide grating wavelength division multiplexer integrated with the microring is shown in FIG. 4 . Using semiconductor SOI wafer, based on CMOS fabrication process, the main integration process flow is as follows.
步骤一:如图4-1所示,器件是基于SOI晶圆。经过光刻、曝光形成阵列波导光栅、传输波导、微环谐振滤波器的结构图形;再用Si浅刻蚀工艺形成阵列波导光栅、传输波导、微环谐振滤波器的脊型波导初步结构,如图4-2所示。Step 1: As shown in Figure 4-1, the device is based on SOI wafers. After photolithography and exposure, the structure patterns of arrayed waveguide gratings, transmission waveguides, and microring resonant filters are formed; then Si shallow etching process is used to form the preliminary structures of ridge waveguides of arrayed waveguide gratings, transmission waveguides, and microring resonant filters, such as shown in Figure 4-2.
步骤二:采用二次光刻、曝光及Si刻蚀工艺,制备得到完整的脊型和条形波导结构,完成阵列波导光栅、微环谐振滤波器和传输波导结构,如图4-3所示。Step 2: Use secondary lithography, exposure and Si etching processes to prepare complete ridge and strip waveguide structures, and complete arrayed waveguide gratings, micro-ring resonant filters and transmission waveguide structures, as shown in Figure 4-3 .
步骤三:经过清洗,用PECVD沉积方法,在硅光子波导上方沉积一层厚的SiO2包层,通过反向SiO2刻蚀和抛光得到平整的上表面,如图4-4所示。Step 3: After cleaning, a thick SiO 2 cladding layer is deposited over the silicon photonic waveguide by the PECVD deposition method, and a flat upper surface is obtained by reverse SiO 2 etching and polishing, as shown in Figure 4-4.
步骤四:在SiO2表面通过PVD沉积TiN金属,并通过光刻与干法刻蚀技术形成加热电极,完成后通过PECVD方法在TiN电极上沉积一层SiO2,如图4-5所示。Step 4: Deposit TiN metal on the surface of SiO 2 by PVD, and form a heating electrode by photolithography and dry etching technology. After completion, deposit a layer of SiO 2 on the TiN electrode by PECVD method, as shown in Figure 4-5.
步骤五:通过光刻、曝光和SiO2刻蚀工艺在加热TiN电极上方制备引线孔,刻蚀停到TiN金属上,形成金属沉积孔,如图4-6所示。Step 5: Prepare lead holes above the heated TiN electrodes through photolithography, exposure and SiO 2 etching processes, and stop etching to the TiN metal to form metal deposition holes, as shown in Figure 4-6.
步骤六:最后,通过PVD沉积金属引线材料Al,并通过光刻/刻蚀技术形成金属引线图形,如图4-7所示。Step 6: Finally, the metal lead material Al is deposited by PVD, and the metal lead pattern is formed by photolithography/etching technology, as shown in Figure 4-7.
通过上述工艺,可以在SOI晶圆上制备成微环集成的阵列波导光栅波分复用器。Through the above process, an arrayed waveguide grating wavelength division multiplexer integrated with microrings can be fabricated on an SOI wafer.
本实用新型的有益效果是:The beneficial effects of the present utility model are:
本实用新型使用的硅基阵列波导光栅和微环谐振滤波器体积小,易于集成,制备工艺简单且成熟;器件中仅增加一个微环谐振滤波器和波长调谐结构,引入的功耗小;同时微环谐振滤波器的插入损耗极小,不但能够通过AWG进行一次滤波、微环谐振滤波器进行二次滤波得到优异的串扰特性,同时确保器件的总损耗与单个AWG相当。该器件在光通信的波分复用领域有着广泛的应用。The silicon-based array waveguide grating and the micro-ring resonant filter used in the utility model are small in size, easy to integrate, simple and mature in preparation process; only one micro-ring resonant filter and a wavelength tuning structure are added to the device, and the introduced power consumption is small; The insertion loss of the micro-ring resonator filter is extremely small. It can not only perform primary filtering by AWG and secondary filtering by micro-ring resonant filter to obtain excellent crosstalk characteristics, but also ensure that the total loss of the device is equivalent to that of a single AWG. The device has a wide range of applications in the field of wavelength division multiplexing of optical communications.
附图说明Description of drawings
图1是本实用新型微环集成的阵列波导光栅波分复用器连接示意图;1 is a schematic diagram of the connection of an arrayed waveguide grating wavelength division multiplexer integrated with a micro-ring of the present invention;
图2是本实用新型阵列波导光栅结构示意图;FIG. 2 is a schematic diagram of the structure of the arrayed waveguide grating of the present invention;
图3是本实用新型微环谐振滤波器结构示意图;3 is a schematic structural diagram of the micro-ring resonant filter of the present invention;
图4是本实用新型微环谐振滤波器波导上包层加热电极工艺处理流程图;Fig. 4 is the process flow chart of the utility model micro-ring resonant filter waveguide upper cladding heating electrode process;
图5是本实用新型微环谐振滤波器波导层加热电极工艺处理流程图。FIG. 5 is a flow chart of the processing flow of the heating electrode of the waveguide layer of the micro-ring resonant filter of the present invention.
图中:1-输入波导,2-输入平板波导,3-阵列波导,4-输出平板波导,5-输出波导,6-输入直波导输入端,7-输入直波导直输出端,8-输出直波导下载端,9-输出直波导上载端,10-第一耦合区,11-波长调谐结构,12-第二耦合区,110-阵列波导光栅,120-传输波导,130-微环谐振滤波器,131-输入直波导,132-环形谐振腔,133-输出直波导。In the figure: 1-input waveguide, 2-input slab waveguide, 3-array waveguide, 4-output slab waveguide, 5-output waveguide, 6-input straight waveguide input end, 7-input straight waveguide straight output end, 8-output Straight waveguide download end, 9-output straight waveguide upload end, 10-first coupling region, 11-wavelength tuning structure, 12-second coupling region, 110-array waveguide grating, 120-transmission waveguide, 130-microring resonance filter 131-input straight waveguide, 132-ring resonator, 133-output straight waveguide.
具体实施方式Detailed ways
下面结合附图和具体实施方式,对本实用新型作进一步说明。The present utility model will be further described below with reference to the accompanying drawings and specific embodiments.
实施例1Example 1
如图1至图3所示,该微环集成的阵列波导光栅波分复用器基于SOI晶圆,从上至下包括衬底层、埋氧层、波导层和SiO2上包层,所述波导层分别有阵列波导光栅110(AWG)、传输波导120和微环谐振滤波器130(MRR),阵列波导光栅110通过传输波导120与微环谐振滤波器130相连。As shown in Fig. 1 to Fig. 3, the micro-ring integrated arrayed waveguide grating WDM multiplexer is based on SOI wafer, and includes a substrate layer, a buried oxide layer, a waveguide layer and a SiO 2 upper cladding layer from top to bottom. The waveguide layer respectively includes an arrayed waveguide grating 110 (AWG), a
其中阵列波导光栅110包括输入波导1、输入平板波导2、阵列波导3、输出平板波导4和输出波导5,输入波导1连接输入平板波导2,输入平板波导2通过阵列波导3连接输出平板波导4,输入平板波导2和输出平板波导4设置成罗兰圆结构,输出平板波导4连接输出波导5。一束含不同波长光信号从输入波导1进入输入平板波导2发生衍射,经阵列波导3,不同波长光聚焦在输出平板波导4的不同位置,最后,经输出波导5输出,实现信号的第一次滤波;微环谐振滤波器130包括输入直波导131、环形谐振腔132、波长调谐结构11和输出直波导133,输入直波导131与环形谐振腔132间存在第一耦合区10,环形谐振腔132和输出直波导133间存在第二耦合区12,输入直波导131分为输入直波导输入端6和输入直波导直输出端7,输出直波导133分为下载端8和上载端9。经传输波导120传输的光信号从输入直波导131的输入端6输入,在第一耦合区10耦合进入环形谐振腔132,满足谐振条件的波长在环中引起谐振并在第二耦合区12耦合进入输出直波导133,并从下载端8输出,实现分波信号的二次滤波。基于热光效应的波长调谐结构11在驱动电源作用下,可使微环谐振滤波器130的谐振波长与AWG对应输出通道信号波长匹配。在本实例中,由于AWG的通道间隔固定,因此各微环谐振滤波器的设计完全相同,通过波长调谐结构保证每个微环谐振滤波器的谐振波长与AWG输出通道的输出信号中心波长一致,且其自由光谱区大于AWG输出信号的通道间隔。此波长调谐结构加热电极位于波导的SiO2上包层由高电阻材料TiN构成。The arrayed waveguide grating 110 includes an
阵列波导光栅110、传输波导120和微环谐振滤波器130均在SOI晶圆相同顶层硅上。SOI晶圆尺寸为8英寸,晶圆厚度为725µm,埋氧层厚度为2µm,顶层硅厚度为220nm。阵列波导光栅110的阵列波导3为宽度450nm、刻蚀深度100nm的脊型波导,阵列波导3的长度差为12.95µm,罗兰圆半径为89.3µm,最小完全半径为50µm,衍射级数为20,通道间隔为6.4nm。传输波导120为宽度450nm、高度200nm的脊型波导。微环谐振滤波器130的输入波导131/输出波导133均为宽度450nm的条形波导,环形谐振腔132和耦合区(第一耦合区10和第二耦合区12)均为宽度为450nm、刻蚀深度为100nm的脊型波导,输入/输出波导与环形谐振腔的最小间距为200nm,环形谐振腔直径为23µm,自由光谱区FSR为6.8nm。在SOI晶圆上通过多次光刻/刻蚀半导体工艺,制作本实用新型器件的波导结构,在波导形成后,通过PECVD工艺沉积1.5µm厚的SiO2上包层,并通过反向刻蚀和抛光工艺得到平整而光滑的表面(图4-1至图4-4所示);在此平滑表面通过PVD技术沉积一层110nm厚的高电阻材料TiN,并通过光刻/刻蚀形成TiN加热电极(图4-5所示),其为宽度5µm、总长200µm折返分布结构,在TiN电极材料上方采用PECVD工艺沉积450nm厚的SiO2隔离层;通过光刻/刻蚀技术在TiN电极上方形成加热电极引线孔(图4-6所示),引线孔刻蚀停在TiN加热电极上;最后在采用PVD技术沉积2µm的金属引线材料Al,Al材料与TiN加热电极相连,并通过光刻/刻蚀技术形成宽度为10µm的Al金属引线(图4-7所示),Al金属引线与探测接触的终端结构为边长70µm的正方形。The arrayed waveguide grating 110, the
实施例2Example 2
如图1至3所示,该微环集成的阵列波导光栅波分复用器基于SOI晶圆,从下至上包括衬底层、埋氧层、波导层和SiO2上包层,所述波导层分别有阵列波导光栅110(AWG)、传输波导120和微环谐振滤波器130(MRR),阵列波导光栅110通过传输波导120与微环谐振滤波器130相连。As shown in Figures 1 to 3, the micro-ring integrated arrayed waveguide grating WDM multiplexer is based on SOI wafer, which includes a substrate layer, a buried oxide layer, a waveguide layer and an SiO2 upper cladding layer from bottom to top, the waveguide layer There are respectively an arrayed waveguide grating 110 (AWG), a
其中阵列波导光栅110包括输入波导1、输入平板波导2、阵列波导3、输出平板波导4和输出波导5,输入波导1连接输入平板波导2,输入平板波导2通过阵列波导3连接输出平板波导4,输入平板波导2和输出平板波导4设置成罗兰圆结构,输出平板波导4连接输出波导5。一束含不同波长光信号从输入波导1进入输入平板波导2发生衍射,经阵列波导3,不同波长光聚焦在输出平板波导4的不同位置,最后,经输出波导5输出,实现信号的第一次滤波;微环谐振滤波器130包括输入直波导131、环形谐振腔132、输出直波导133和波长调谐结构11,输入直波导131与环形谐振腔132间存在第一耦合区10,环形谐振腔132和输出直波导133间存在第二耦合区12,输入直波导131分为输入直波导输入端6和输入直波导直输出端7,输出直波导133分为下载端8和上载端9。经传输波导120传输的光信号从输入直波导131的输入端6输入,在第一耦合区10耦合进入环形谐振腔132,满足谐振条件的波长在环中引起谐振并在第二耦合区12耦合进入输出直波导133,并从下载端8输出,实现分波信号的二次滤波。基于热光效应的波长调谐结构11在驱动电源作用下,可使微环谐振滤波器130的谐振波长与AWG任意输出通道信号波长匹配。在本实例中,由于AWG的通道间隔固定,因此各微环谐振滤波器的设计完全相同,通过波长调谐结构保证各器件的谐振波长与AWG的输出波长一致,且其自由光谱区大与AWG的通道间隔。此波长调谐结构加热电极位于波导Si层且由Ni离子掺杂形成(NiSi)。The arrayed waveguide grating 110 includes an
该低串扰波分复用器基于SOI晶圆,阵列波导光栅110(AWG)、传输波导120、微环谐振滤波器130(MRR)均在SOI晶圆的相同顶层硅上。SOI晶圆尺寸为8英寸,晶圆厚度为725µm,埋氧层厚度为2µm,顶层硅厚度为220nm。阵列波导光栅由阵列波导宽度为400nm、刻蚀深度为110nm的脊型波导构成,阵列波导长度差为7.243µm,罗兰圆半径为268.76µm,最小完全半径为75µm,衍射级数为8,通道间隔为6.8nm。传输波导宽度为400nm、高度为220nm的脊型波导。微环谐振滤波器的输入/输出波导均为宽度450nm的脊型波导。微环谐振滤波器的谐振腔和耦合区均为宽度为450nm、刻蚀深度为110nm的脊型波导,输入/输出波导与微环谐振腔波导最小间距为150nm,微环谐振腔直径为31.25µm,自由光谱区FSR为6.4nm。本器件工艺如图5所示,在SOI晶圆上通过两次光刻/刻蚀半导体工艺,形成本实用新型器件完整的脊型波导结构(图5-1至图5-2所示);在波导形成后,通过PECVD工艺沉积300nm厚的SiO2层,并通过反向刻蚀和抛光工艺得到平整而光滑的表面(图5-3所示);通过曝光、光刻、清洗与沉积工艺,根据NiSi加热器的图形在环形谐振腔的平板波导上开一窗口并沉积20nm的Ni,并在280°C温度200s的条件下退火,用H2SO4洗去未反应Ni,波导层形成NiSi加热电极(图5-4至5-5所示);随后在NiSi电极上采用PVD技术沉积10µm的金属引线材料Al,Al材料与NiSi加热电极相连,并通过光刻/刻蚀技术形成宽度为20µm的Al金属引线,Al金属引线与探测接触的终端结构为边长70µm的正方形(图5-6所示);最后通过光刻和刻蚀技术形成热隔离的镂空结构(图5-7所示)。The low crosstalk wavelength division multiplexer is based on an SOI wafer, and the arrayed waveguide grating 110 (AWG),
以上结合附图对本实用新型的具体实施方式作了详细说明,但是本实用新型并不限于上述实施方式,在本领域普通技术人员所具备的知识范围内,还可以在不脱离本实用新型宗旨的前提下作出各种变化。The specific embodiments of the present utility model have been described in detail above in conjunction with the accompanying drawings, but the present utility model is not limited to the above-mentioned embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, the present utility model can also be used without departing from the purpose of the present utility model. Various changes are made under the premise.
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