CN211295099U - Vertical integrated packaging assembly - Google Patents
Vertical integrated packaging assembly Download PDFInfo
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- CN211295099U CN211295099U CN202020442695.XU CN202020442695U CN211295099U CN 211295099 U CN211295099 U CN 211295099U CN 202020442695 U CN202020442695 U CN 202020442695U CN 211295099 U CN211295099 U CN 211295099U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 238000005538 encapsulation Methods 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000010949 copper Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 15
- 239000000956 alloy Substances 0.000 description 13
- 229910045601 alloy Inorganic materials 0.000 description 13
- 238000000034 method Methods 0.000 description 11
- 238000005452 bending Methods 0.000 description 9
- 239000004033 plastic Substances 0.000 description 6
- 102100022094 Acid-sensing ion channel 2 Human genes 0.000 description 5
- 101710099902 Acid-sensing ion channel 2 Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000005022 packaging material Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
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- 230000005693 optoelectronics Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application relates to a vertical integrated packaging assembly, which comprises a circuit substrate, a functional chip, a drive control ASIC (application specific integrated Circuit) and a packaging structure, wherein the circuit substrate comprises a main substrate and an auxiliary substrate which are spaced apart from each other, conductive circuits are arranged on the upper surface and the lower surface of the main substrate and the auxiliary substrate, the functional chip and the drive control ASIC are respectively arranged on the upper side and the lower side of the main substrate, the functional chip is electrically connected with the conductive circuits on the auxiliary substrate through a connecting wire, and the drive control ASIC is also electrically connected with the conductive circuits on the auxiliary substrate through the connecting; and packaging structures are arranged outside the functional chip and the drive control ASIC. This application has realized integrating, miniaturization and the electrical connection line's of encapsulation device the shortest, and preparation is simple moreover, and the yields is high, can satisfy the demand of extensive volume production.
Description
Technical Field
The application relates to a vertical integrated packaging assembly, which is applicable to the technical field of semiconductor packaging.
Background
In recent years, electronic terminal products tend to be miniaturized, lightweight and diversified in application space, especially the intelligentization of various products and the development trend of the universal joint of everything, and many components with single functions are required to be integrated or modularized in function devices and drive control. It is further desirable that multiple functionally distinct, interrelated components be placed in a packaged device.
For example, in optoelectronic semiconductors, Light Emitting Diodes (LEDs) and their drive control Application Specific Integrated Circuits (ASICs) are two independent packaged devices, and in future package development, the integration of LEDs and their ASICs is a trend. Similarly, there is integration of the sensor with its ASIC, etc. Current packages include the most mature individual packages, planar integrated packages. The independent packaging is not conducive to miniaturization of products and energy loss in interconnection of components. Planar integrated form encapsulation is packed into the components and parts that have further integrated different functional types, and size and the electrical connection of product have all optimized one step more than independent encapsulation, because be planar's encapsulation, the encapsulation size is the stack of a plurality of components and parts sizes, and every components and parts all independently occupy the space to electrical connection also is close to the connection, all has the restriction on the integrated size of components and parts and on the electrical connection, can not further satisfy the demand of future product.
Recently, some enterprises have developed additive vertical integrated packages, which can greatly reduce the package space of components and make the electrical connection lines shorter. However, the packaging structure relates to the manufacture of multilayer circuits and insulating layers, the circuits are mutually communicated by drilling holes in the vertical direction, the process is extremely complex, the yield is always poor, the cost is high, and large-scale mass production is difficult to realize.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an integrated encapsulation subassembly of rectilinear, not only realized integrating, miniaturization and the electrical connection line's of encapsulation device the minimizing, preparation is simple moreover, and the yields is high, can satisfy the demand of extensive volume production.
The first aspect of the application relates to a vertical integrated packaging assembly, which comprises a circuit substrate, a functional chip, a drive control ASIC (application specific integrated Circuit) and a packaging structure, wherein the circuit substrate comprises a main substrate and an auxiliary substrate which are spaced apart from each other, conductive circuits are arranged on the upper surface and the lower surface of the main substrate and the upper surface and the lower surface of the auxiliary substrate, the functional chip and the drive control ASIC are respectively arranged on the upper side and the lower side of the main substrate, the functional chip is electrically connected with the conductive circuits on the auxiliary substrate through a connecting wire, and the drive control ASIC is also electrically connected with the; and packaging structures are arranged outside the functional chip and the drive control ASIC.
The two auxiliary substrates are respectively positioned on two sides of the main substrate, and the far ends of the auxiliary substrates on the two sides are bent downwards to form a C shape; the drive control ASIC is positioned on the lower side of the main substrate, and the ASIC packaging layer is positioned in a cavity surrounded by the circuit substrate; the functional chip is positioned on the upper side of the main substrate, package limiting parts are formed on two sides of the auxiliary substrate and in the interval between the auxiliary substrate and the main substrate, and a functional chip package layer is arranged in a cavity defined by the package limiting parts and the circuit substrate; or
The auxiliary substrate is provided with a block, and the far end of the auxiliary substrate is bent downwards to form a C shape; the drive control ASIC is positioned on the lower side of the main substrate, the far end of the main substrate is also bent downwards to form a C shape, and the ASIC packaging layer is positioned in a cavity surrounded by the circuit substrates; the functional chip is located the upside of main substrate, is formed with the encapsulation locating part in the interval between both sides on the circuit substrate, vice base plate and the main substrate, is provided with the functional chip encapsulation layer in the cavity that encapsulation locating part and circuit substrate enclose.
Preferably, the ASIC package layer and the package stopper are integrally injection molded; the ASIC packaging layer and the functional chip packaging layer are plastic packaging layers; the connecting wire is a gold wire with the diameter of 0.5-2.0 mil; the functional chip is a light emitting diode or a sensor; a step is formed on a solid-crystal surface of the drive control ASIC.
The beneficial technical effect of rectilinear integrated package subassembly of this application includes:
(1) the traditional planar integrated package of the functional chip and the drive control thereof is changed into a vertical package structure, so that the integration and miniaturization of a package device and the shortest electrical connection circuit are realized;
(2) the conventional vertical packaging is expanded from passive component packaging to ASIC-driven embedded packaging, so that the application range of the vertical packaging is expanded.
Drawings
Fig. 1 shows a schematic structural diagram of one embodiment of a vertical integrated package assembly according to the present application.
Fig. 2 shows a circuit substrate forming a portion of the circuit substrate of fig. 1 of the present application.
Fig. 3 is a sectional view a-a in fig. 2.
Fig. 4 shows a schematic structure diagram of another embodiment of a vertical integrated package assembly according to the present application.
Fig. 5 shows a circuit substrate forming a portion of the circuit substrate of fig. 4 of the present application.
Fig. 6 is a sectional view B-B in fig. 5.
Fig. 7 shows a schematic view of the components used to assist in bending the end of the wiring substrate in the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
As shown in fig. 1, there is shown a schematic structural diagram of a preferred mode of a vertical integrated package assembly according to the present application, which includes a circuit substrate 5, a functional chip 1, a driving control ASIC2 and a package structure, wherein the circuit substrate 5 includes a main substrate 51 and a sub-substrate 52, and conductive traces, such as plated copper traces, are etched on the upper and lower surfaces of the main substrate 51 and the sub-substrate 52. The main substrate 51 is separated from the sub-substrate 52, the upper side and the lower side of the main substrate 51 are respectively provided with a functional chip 1 and a driving control ASIC2, the functional chip 1 is electrically connected with a conductive circuit on the sub-substrate 52 through a connecting wire 6, and the driving control ASIC2 is also electrically connected with a conductive circuit on the sub-substrate 52 through the connecting wire 6; the functional chip 1 and the drive control ASIC2 are each provided with a package structure on the outside.
In the embodiment shown in fig. 1, two sub boards 52 are provided, and are located on both sides of the main board 51. The drive control ASIC2 is located on the lower side of the main substrate 51, the far ends of the auxiliary substrates 52 on the two sides are bent downwards to form a C shape, and the ASIC packaging layer 4 is located in a cavity surrounded by the circuit substrates; the functional chip 1 is located on the upper side of the main substrate 51, the package limiting parts 3 are formed on two sides of the auxiliary substrate 52 and in the interval between the auxiliary substrate 52 and the main substrate 51, and the functional chip package layer 7 is arranged in a cavity defined by the package limiting parts 3 and the circuit substrate 5.
Preferably, the ASIC package layer 4 may be integrally injection-molded with the package stopper 3; the ASIC packaging layer 4 and the functional chip packaging layer 7 can be plastic packaging layers, a rough interface can be etched on a plastic packaging contact interface to improve the bonding force of a bonding interface, and the high reliability and stability of the interface determine the reliability and stability of the whole packaging component. In a preferred embodiment, gold wires with a diameter of 0.5-2.0mil are selected as the connection wires, the gold wires have higher reliability and stability and are not easily oxidized, and the ratio of the diameter of the connection wires to the thickness of the wiring substrate may be 0.01-100. The functional chip in this application may be a light emitting diode or a sensor component.
In the embodiment shown in fig. 4, only one sub-substrate 52 may be provided, and the other components are the same as those in the embodiment of fig. 1, and are not described again.
Fig. 2 shows a portion of an alloy copper material forming the circuit substrate of fig. 1 of the present application, wherein the alloy copper material unit used to form four package assemblies is shown; when the package assembly is prepared, the alloy copper material is firstly cut along the longitudinal direction in the figure to form a strip-shaped package assembly substrate, and the strip-shaped package assembly substrate is bent into a C shape at the end part of the strip-shaped package assembly substrate so as to support the package structure, and then the strip-shaped package assembly substrate is cut along the transverse direction to form an independent package assembly. Fig. 3 is a cross-sectional view a-a of fig. 2, with the dashed line at the bend line of the C-shaped support structure formed during packaging. Fig. 5 shows a portion of an alloy copper material forming the wiring substrate shown in fig. 4 of the present application, and fig. 6 is a cross-sectional view B-B of fig. 5.
The method of packaging the vertical integrated package assembly of the present application is illustrated by the package assembly shown in fig. 1-3, comprising the steps of:
(1) etching the conductive circuit patterns on the upper side and the lower side of the whole circuit substrate;
(2) mounting the drive control ASIC on the lower side of the main substrate through a die bonding and wire bonding process, and connecting the drive control ASIC with a conductive circuit on the secondary substrate;
(3) injecting a packaging material below the circuit substrate by using a transfer molding method to form a packaging structure of the drive control ASIC, and simultaneously injecting a packaging limiting part;
(4) stamping and cutting the whole circuit substrate along a dividing line in the vertical direction to form a strip shape, and bending and forming the end part of the strip-shaped alloy copper plate to form a bending structure for supporting the packaging material;
(5) installing the functional chip on the upper side of the main substrate through a die bonding and wire bonding process, and connecting the functional chip with the conductive circuit on the auxiliary substrate;
(6) forming a functional chip packaging layer outside the functional chip by injection molding;
(7) and cutting according to the dividing line of the single packaging assembly to form a final single packaging structure.
Examples
The packaging method of the vertical integrated package assembly of the present application is described below by way of example, and includes the following steps:
(1) the circuit diagram is etched on the whole block of alloy copper material, an alloy copper plate with the thickness of 6mil or 8mil is generally selected, the pin clearance is between 0.1 and 0.2mm, and the specific pin number depends on the design of the ASIC function. And completely covering the covering film on the whole copper plate, activating the circuit covering film by using UV or laser, and etching a circuit pattern on the alloy copper plate by a chemical method. The covering film can be washed away by chemical reagent after being activated, the copper material which does not need to be etched is protected by the covering film without activation, the copper material can be exposed at the washed away part, and then the copper material is etched into a required circuit diagram by chemical reagent;
(2) through a die bonding and wire welding process, selecting proper die bonding glue and gold wires, alloy wires or copper wires to weld the drive control ASIC to the lower side of the main substrate and connect the drive control ASIC with a conductive circuit on the auxiliary substrate; preferably, the step can be punched on the solid crystal surface of the ASIC, because the height of the whole ASIC is inconsistent with the thickness of some wafers, the shortest connecting line is ensured in the whole subsequent electrical connection, and the step can be designed to compensate for the difference of inconsistent thickness;
(3) injecting a packaging material, such as an epoxy resin material, below the alloy copper material by using a transfer molding method to form a packaging structure of the drive control ASIC, and simultaneously injecting and forming a packaging limiting part; in the plastic transmission process, a compound filling material with the thickness less than 50um is preferably selected, so that the superfine pins can be fully filled, and an epoxy resin material containing a nano filler can be filled into a structure with a smaller distance;
(4) stamping the whole alloy copper material along a dividing line vertical to the circuit substrate to form a strip shape, and bending and molding the end part of the strip-shaped alloy copper plate to form a C-shaped bending structure for supporting the packaging material;
(5) welding the functional chip on the upper side of the main substrate by a die bonding and wire bonding process, and connecting the functional chip with the conductive circuit on the auxiliary substrate;
(6) forming a functional chip packaging layer outside the functional chip by injection molding;
(7) and cutting the alloy copper plate according to the dividing line of the single packaging assembly to form a final single packaging structure.
In the bending process of step (4), in order to avoid damaging the already packaged functional chip and the drive control ASIC, an auxiliary bending tool as shown in fig. 7 may be employed. Specifically, the upper surface and the lower surface of the copper plate close to the plastic package material can be respectively provided with a triangular pressing block 10, and the pressing blocks tightly push the plastic package material during bending, so that the damage to the package body during bending can be reduced to the greatest extent.
Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Claims (8)
1. A vertical integrated packaging assembly comprises a circuit substrate, a functional chip, a drive control ASIC and a packaging structure, and is characterized in that the circuit substrate comprises a main substrate and an auxiliary substrate which are spaced from each other, conductive circuits are arranged on the upper surface and the lower surface of the main substrate and the auxiliary substrate, the functional chip and the drive control ASIC are respectively arranged on the upper side and the lower side of the main substrate, the functional chip is electrically connected with the conductive circuits on the auxiliary substrate through a connecting wire, and the drive control ASIC is also electrically connected with the conductive circuits on the auxiliary substrate through the connecting wire; and packaging structures are arranged outside the functional chip and the drive control ASIC.
2. The vertical integrated package assembly of claim 1, wherein the two sub-substrates are respectively disposed at two sides of the main substrate, and distal ends of the two sub-substrates are bent downward to form a C-shape; the drive control ASIC is positioned on the lower side of the main substrate, and the ASIC packaging layer is positioned in a cavity surrounded by the circuit substrate; the functional chip is located the upside of main substrate, is formed with the encapsulation locating part in the both sides on the auxiliary substrate, the interval between auxiliary substrate and the main substrate, is provided with the functional chip encapsulation layer in the cavity that encapsulation locating part and circuit substrate enclose.
3. The vertical integrated package assembly of claim 1, wherein the sub-substrate is provided with a piece, and a distal end of the sub-substrate is bent downward to form a C-shape; the drive control ASIC is positioned on the lower side of the main substrate, the far end of the main substrate is also bent downwards to form a C shape, and the ASIC packaging layer is positioned in a cavity surrounded by the circuit substrates; the functional chip is located the upside of main substrate, is formed with the encapsulation locating part in the interval between both sides on the circuit substrate, vice base plate and the main substrate, is provided with the functional chip encapsulation layer in the cavity that encapsulation locating part and circuit substrate enclose.
4. The vertical integrated package assembly of claim 2 or 3, wherein the ASIC package layer and the package stopper are integrally injection molded.
5. The vertical integrated package assembly of claim 2 or 3, wherein the ASIC package layer and the functional chip package layer are molding layers.
6. The vertical integrated package assembly of any one of claims 1-3, wherein the connecting lines are gold wires having a diameter of 0.5-2.0 mil.
7. The vertical integrated package assembly of any one of claims 1-3, wherein the functional chip is a light emitting diode or a sensor.
8. The vertical integrated package assembly of any one of claims 1-3, wherein a step is formed on a die bonding surface of the drive control ASIC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020442695.XU CN211295099U (en) | 2020-03-31 | 2020-03-31 | Vertical integrated packaging assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020442695.XU CN211295099U (en) | 2020-03-31 | 2020-03-31 | Vertical integrated packaging assembly |
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| CN211295099U true CN211295099U (en) | 2020-08-18 |
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| CN202020442695.XU Active CN211295099U (en) | 2020-03-31 | 2020-03-31 | Vertical integrated packaging assembly |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111430343A (en) * | 2020-03-31 | 2020-07-17 | 深圳市唯亮光电科技有限公司 | Vertical integrated packaging assembly and packaging method thereof |
| CN111863800A (en) * | 2020-09-17 | 2020-10-30 | 深圳市方晶科技有限公司 | An optoelectronic integrated LED lamp bead packaging structure and method |
-
2020
- 2020-03-31 CN CN202020442695.XU patent/CN211295099U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111430343A (en) * | 2020-03-31 | 2020-07-17 | 深圳市唯亮光电科技有限公司 | Vertical integrated packaging assembly and packaging method thereof |
| CN111863800A (en) * | 2020-09-17 | 2020-10-30 | 深圳市方晶科技有限公司 | An optoelectronic integrated LED lamp bead packaging structure and method |
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