CN210895158U - E/D NMOS reference voltage source and low dropout voltage regulator - Google Patents

Abstract

The utility model provides a E/D NMOS reference voltage source and low dropout voltage regulator, in the E/D NMOS reference voltage source, no matter how the applied mains voltage changes, through the pre-reference source circuit based on N channel JFET can be with the output voltage of pre-reference as the fixed value, the scope of output voltage of pre-reference is wide, the technology adjustment is convenient; because the pre-reference source circuit bears withstand voltage and preliminary voltage stabilization, the input voltage of the E/D NMOS reference source circuit has small change by the power supply voltage, the wide input voltage range and the power supply rejection ratio of the E/D NMOS reference source circuit are greatly improved, and the E/D NMOS reference source circuit has the property of micro power consumption of the E/D NMOS reference; the E/D NMOS reference voltage source has a simple and reasonable circuit structure, does not need a triode, a resistor, a capacitor and the like, is additionally manufactured on the basis of a silicon gate P well E/D CMOS process, only needs to adjust the threshold voltage of the N-channel junction field effect transistor, greatly simplifies the process and reduces the cost.

Description

E/D NMOS Reference Voltage Source and Low Dropout Voltage Regulator

technical field

The utility model relates to the technical field of power management, in particular to an E/D NMOS reference voltage source and a low-dropout voltage regulator.

Background technique

In the design of the power management circuit of the analog integrated circuit, the reference voltage source determines the performance index of the low dropout power supply. At present, there are many kinds of reference voltage sources, including Zener reference source, bandgap reference source, bandgap reference source with second-order compensation, and E/D NMOS reference source with high power supply rejection ratio.

Among them, the Zener reference voltage source adopts a bipolar circuit structure combined with a Zener diode with process characteristics to achieve high performance of the Zener reference source; the bandgap reference source adopts a standard bandgap structure to achieve high-performance bandgap reference output; The bandgap reference source with second-order compensation is designed on the basis of the gap reference source, which further improves the temperature performance of the bandgap reference. The two-stage structure of the tube in series realizes a micro-power reference voltage source with a high power supply rejection ratio.

However, it is difficult for the above reference voltage sources to meet the requirements of high voltage (40V), high power supply rejection ratio (60dB), and low power consumption (≤10uA) at the same time, which further limits the above reference voltage source in high voltage, high power supply rejection ratio, and micro power consumption. applications of low dropout voltage regulators.

Utility model content

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an E/D NMOS reference voltage source with a wide input voltage range for solving the above-mentioned technical problems.

In order to achieve the above-mentioned purpose and other related purposes, the utility model provides an E/D NMOS reference voltage source, including:

A pre-reference source circuit, including an N-channel junction field effect transistor, the gate of the N-channel junction field effect transistor is grounded, the drain is connected to the power supply voltage, and the source outputs a pre-reference voltage;

The E/D NMOS reference source circuit is connected to the pre-reference source circuit, receives the pre-reference voltage and outputs the reference voltage externally.

Optionally, the N-channel junction field effect transistor includes a depletion-type N-channel junction field effect transistor.

Optionally, the E/D NMOS reference source circuit includes:

a reference voltage starter circuit, connected to the pre-reference source circuit, receiving the pre-reference voltage and outputting the reference voltage to the outside;

The reference voltage adjusting sub-circuit and the reference voltage enabling sub-circuit adjust the reference voltage.

Optionally, the reference voltage promoter sub-circuit includes a plurality of NMOS transistors connected in series, and the reference voltage regulator sub-circuit includes a plurality of NMOS transistors connected in series.

Optionally, the reference voltage promoter circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the drain of the first NMOS transistor is connected to the N-channel junction type The source of the field effect transistor, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, and the first NMOS transistor is connected to the source of the second NMOS transistor. The drain of the four NMOS transistors is connected to the source of the third NMOS transistor, and the source of the fourth NMOS transistor is used as a reference voltage output terminal; the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the third NMOS transistor The gates of the four NMOS transistors are connected together and connected to the reference voltage output terminal; the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are connected together and connected to all The reference voltage output terminal.

Optionally, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor include: depletion-mode NMOS transistors.

Optionally, the reference voltage promoter circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the drain of the fifth NMOS transistor is connected to the reference voltage output terminal, The drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor, and the drain of the eighth NMOS transistor is connected to The source of the seventh NMOS transistor and the source of the eighth NMOS transistor are grounded; the gates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are connected together, and connected to the reference voltage output terminal; the substrates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are connected together and grounded.

Optionally, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor include: enhancement mode NMOS transistors.

In addition, in order to achieve the above purpose and other related purposes, the present invention also provides a low dropout voltage regulator, including the E/D NMOS reference voltage source described in any one of the above.

As mentioned above, the E/D NMOS reference voltage source of the present invention has the following beneficial effects:

In the pre-reference source circuit, the drain of the N-channel junction field effect transistor whose gate is grounded is subjected to the power supply voltage. When the N-channel junction field effect transistor is turned on, the pre-reference voltage output by its source is equal to its The threshold voltage is a fixed value; when the power supply voltage changes in a wide range (high level), the N-channel junction field effect transistor is always turned on, and the gate output of the N-channel junction field effect transistor is The pre-reference voltage is always a constant threshold voltage, which avoids the fluctuation of the power supply of the subsequent E/D NMOS reference source circuit with the external power supply voltage, and improves the working voltage range and high power supply rejection ratio of the E/D NMOS reference source circuit.

Description of drawings

FIG. 1 shows a circuit diagram of an E/D NMOS reference voltage source in an embodiment of the present invention.

Figure 2 shows an equivalent circuit diagram of the E/D NMOS reference in Figure 1.

Description of reference numerals

N1 first NMOS transistor

N2 second NMOS transistor

N3 third NMOS transistor

N4 fourth NMOS tube

N5 fifth NMOS tube

N6 sixth NMOS tube

N7 seventh NMOS tube

N8 Eighth NMOS tube

NJ N-Channel Junction Field Effect Transistor

N1* first equivalent NMOS transistor

N2* second equivalent NMOS transistor

V _IN supply voltage

V _pre-vref pre-reference voltage

_Vref reference voltage

GND ground

Detailed ways

As mentioned above in the Background Art, the existing reference voltage sources such as Zener reference sources, bandgap reference sources, bandgap reference sources with second-order compensation, and E/D NMOS reference sources with high power supply rejection ratio are very difficult to achieve. It is difficult to meet the requirements of high voltage, high power supply rejection ratio and low power consumption at the same time, which limits the application of reference voltage sources in low dropout voltage regulators with high voltage, high power supply rejection ratio and micro power consumption.

Based on this, the present utility model proposes an E/D NMOS reference voltage source with a new structure, which includes a pre-reference source circuit based on an N-channel junction field effect transistor and an E/D NMOS reference source circuit. The gate of the FET is grounded and the drain is connected to the power supply voltage. The N-channel junction FET is subjected to withstand voltage. When the power supply voltage changes in a wide range, the pre-reference voltage output by the gate is always The constant threshold voltage avoids the fluctuation of the input power supply of the E/D NMOS reference source circuit with the external power supply voltage, and improves the working voltage range and high power supply rejection ratio of the E/D NMOS reference source circuit.

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 to 2. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, and only the components related to the present invention are shown in the drawings instead of the number of components in the actual implementation, In the drawing of shape and size, the type, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complicated. The structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the technology, and are not intended to limit the implementation of the present invention. condition, therefore does not have technical substantive significance, any modification of structure, the change of proportional relationship or the adjustment of size, without affecting the effect that the utility model can produce and the purpose that can be achieved, all should still fall within the present utility model. The technical content disclosed by the new model must be within the scope of coverage.

As shown in FIG. 1, the present utility model provides an E/D NMOS reference voltage source, which includes:

The pre-reference source circuit includes an N-channel junction field effect transistor NJ, the gate of the N-channel junction field effect transistor NJ is grounded to GND, the drain is connected to the power supply voltage V _IN , and the source outputs a pre-reference voltage V _pre-vref ;

The E/D NMOS reference source circuit is connected to the pre-reference source circuit, receives the pre-reference voltage V _pre-vref and outputs the reference voltage V _ref to the outside.

Optionally, the N-channel junction field effect transistor NJ includes a depletion-type N-channel junction field effect transistor, that is, a conductive channel already exists when its gate voltage is zero.

As shown in Figure 1, the gate of the N-channel junction field effect transistor NJ is grounded to GND and the drain is connected to the power supply voltage V _IN . When the power supply voltage V _IN is at a high level, the N-channel junction field effect transistor NJ is turned on , the gate output pre-reference voltage V _pre-vref is a constant threshold voltage V _TH , even if the power supply voltage V _IN varies within a wide range, the gate output pre-reference voltage V _pre-vref is always a fixed value. Among them, the value of the threshold voltage V _TH in the N-channel junction field effect transistor NJ can be adjusted through a process, which is usually (-4.8V～-6.8V).

In detail, the E/D NMOS reference circuit includes:

The reference voltage starter circuit is connected to the pre-reference source circuit, receives the pre-reference voltage V _pre-vref and externally outputs the reference voltage V _ref ;

The reference voltage adjusting sub-circuit and the reference voltage enabling sub-circuit adjust the value of the reference voltage V _ref and the temperature characteristic parameter.

Among them, the reference voltage booster circuit is used as the startup circuit of the E/D NMOS reference source circuit to determine the current of the E/D NMOS reference source circuit; the reference voltage regulator subcircuit performs pull-down regulation on the reference voltage _Vref ; the reference voltage booster circuit includes: A plurality of NMOS transistors connected in series, and the reference voltage adjustment sub-circuit includes a plurality of NMOS transistors connected in series.

Optionally, in an embodiment of the present invention, as shown in FIG. 1 , the reference voltage starter circuit includes: a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4 ; The drain of the first NMOS transistor N1 is connected to the source of the N-channel junction field effect transistor NJ (ie, connected to the pre-reference voltage V _pre-vref ), and the drain of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1 The drain of the third NMOS transistor N3 is connected to the source of the second NMOS transistor N2, the drain of the fourth NMOS transistor N4 is connected to the source of the third NMOS transistor N3, and the source of the fourth NMOS transistor N4 is used as the reference voltage output terminal, the reference voltage V _ref is externally output; the gates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected together, and connected to the reference voltage output terminal (that is, the fourth NMOS transistor The substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected together, and connected to the reference voltage output terminal (that is, the fourth NMOS transistor N4 source).

The first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are all depletion-mode NMOS transistors.

Optionally, in an embodiment of the present invention, as shown in FIG. 1 , the reference voltage starter circuit includes: a fifth NMOS transistor N5 , a sixth NMOS transistor N6 , a seventh NMOS transistor N7 and an eighth NMOS transistor N8 The drain of the fifth NMOS transistor N5 is connected to the reference voltage output terminal (ie, the source of the fourth NMOS transistor N4), the drain of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5, and the drain of the seventh NMOS transistor N7 The drain is connected to the source of the sixth NMOS transistor N6, the drain of the eighth NMOS transistor N8 is connected to the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8 is grounded to GND; the fifth NMOS transistor N5, the sixth NMOS transistor The gates of the transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected together, and are connected to the reference voltage output terminal (ie, the source of the fourth NMOS transistor N4); the fifth NMOS transistor N5 and the sixth NMOS transistor N6 The substrates of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected together and grounded to GND.

Among them, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are all enhancement type NMOS transistors.

In detail, as shown in Figures 1 and 2, the working principle of the E/D NMOS reference voltage source is as follows:

The pre-reference source circuit is composed of an N-channel junction field effect transistor NJ. The drain of the N-channel junction field effect transistor NJ is connected to the power supply voltage V _IN , the gate is grounded GND, and the source outputs a pre-reference voltage V _pre-vref , No matter how the applied power supply voltage V _IN changes, the pre-reference voltage V _pre-vref output by its source is a stable threshold voltage V _TH ;

At the same time, in order to facilitate the calculation, as shown in FIG. 2, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are equivalent to the first equivalent NMOS transistor N1*. The voltage is V _T1 , the channel width is W _N1 , and the channel length is L _N1 ; similarly, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are equivalent to the Two equivalent NMOS transistors N2*, whose threshold voltage is V _T2 , the channel width is W _N2 , and the channel length is L _N2 ; when the circuit is working, the reference voltage V _ref is output, and the current flowing through all NMOS transistors is I _dd ;

For the first equivalent NMOS transistor N1*: since V _GS1 -V _T1 ≤V _DS1 , equation (1) holds:

I _dd =k _p1 ×(V _GS1 -V _T1 ) ² (1)

In formula (1), V _GS1 represents the gate-source voltage of the first equivalent NMOS transistor N1*, V _DS1 represents the drain-source voltage of the first equivalent NMOS transistor N1*, and the corresponding coefficient

For the second equivalent NMOS transistor N2*: since V _GS2 -V _T2 ≤V _DS2 , equation (2) holds:

I _dd =k _p2 ×(V _GS2 -V _T2 ) ² (2)

In formula (2), V _GS2 represents the gate-source voltage of the second equivalent NMOS transistor N2*, V _DS2 represents the drain-source voltage of the second equivalent NMOS transistor N2*, and the corresponding coefficient

According to formulas (1) and (2), we can get:

k _p1 ×(V _GS1 -V _T1 ) ² =k _p2 ×(V _GS2 -V _T2 ) ² (3)

It can be seen from Fig. 2 that V _GS1 =0, V _GS2 =V _ref , equation (3) can be simplified as:

k _p1 ×V _T1 ² =k _p2 ×(V _ref -V _T2 ) ²

Since the second equivalent NMOS transistor N2* is to be turned on, V _ref must be higher than the threshold voltage V _T2 of the second equivalent NMOS transistor N2*, so the smaller value of V _ref is taken as a larger value:

At the moment of power-on of the whole circuit, the N-channel junction field effect transistor NJ is turned on, and the pre-reference voltage V _{pre_vref} output by its source is equal to its threshold voltage V _TH , which is used as the reference voltage to start the power supply voltage of the sub-circuit; the reference voltage The first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 in the voltage starter circuit are turned on, so that the reference voltage _Vref outputs a high level; because the reference voltage _Vref is a high level , then the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 in the reference voltage regulator sub-circuit are turned on, the reference voltage _Vref is pulled down, and then gradually reaches a balance, and finally reaches a Stable value, the value of this value is the same as that of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7. The size and threshold voltage of the eighth NMOS transistor N8 are related to the input power supply voltage V _IN and the threshold voltage V _TH of the N-channel junction field effect transistor NJ.

It can be seen from the above analysis that the reference voltage V _ref output by the E/D NMOS reference voltage source is only related to the threshold voltage of the NMOS tube and the size parameters of the NMOS tube. As long as the correct parameters of the NMOS tube are designed, all the The required reference voltage V _ref .

Optionally, in an embodiment of the present invention, the basic parameter requirements are:

1), the threshold voltage V _TH of N-channel junction field effect transistor NJ: -4.8V ~ 6.8V, the source-drain breakdown voltage V _DS ≥ 40V;

2) The threshold voltage of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4: -0.8～-1.6V, the voltage between the source and the drain ≥16V;

3) The threshold voltage of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8: 0.8-1.2V, the voltage between the source and the drain is ≥16V;

4), the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 The gate oxide thickness is 35nm ~ 45nm;

5) The output voltage V _pre-vref of the pre-reference source circuit: 5.8V±1.0V (typical value is 5.8V);

6), the output voltage _Vref of the E/D NMOS reference source circuit: 1.66V±0.1V;

7) The power supply rejection ratio of the E/D NMOS reference voltage source: ≥75dB;

8) The quiescent current of the E/D NMOS reference voltage source: ≤10μA.

It can be understood that the number of NMOS transistors in the reference voltage booster sub-circuit and the reference voltage regulator sub-circuit are not necessarily the same, and the number of corresponding NMOS transistors is not limited to the four in Figure 1, which can be flexible according to the design requirements of the circuit. choose.

In addition, the present invention also provides a low-dropout voltage regulator, which includes the above-mentioned E/D NMOS reference voltage source. When the above-mentioned E/D NMOS reference voltage source is used to provide the reference voltage for the low dropout voltage regulator, it can meet the requirements of high voltage (wide input voltage range), high power supply rejection ratio, and micro power consumption. The detailed structure of the low dropout voltage regulator may refer to the prior art, which is not limited herein.

To sum up, in the E/D NMOS reference voltage source provided by the present invention, no matter how the applied power supply voltage changes, it is composed of an N-channel junction field effect transistor whose gate is grounded and the drain is connected to the power supply voltage. The pre-reference source circuit can stabilize the pre-reference output voltage to the threshold voltage of the N-channel junction field effect transistor, the range of the pre-reference output voltage is wide, and the process adjustment is convenient; Voltage regulation makes the input voltage of the E/D NMOS reference source circuit change little by the power supply voltage, which greatly improves the wide input voltage range and power supply rejection ratio of the E/D NMOS reference source circuit. The nature of power consumption; the reference voltage starter circuit, as the start-up circuit of the E/D NMOS reference source circuit, can determine the current of the E/D NMOS reference source circuit, and the reference voltage adjustment subcircuit can adjust the output voltage of the E/DNMOS reference source circuit It is easy to adjust the value and temperature characteristic parameters of the E/D NMOS reference source circuit; and the circuit structure of the E/D NMOS reference voltage source is simple and reasonable, and does not require transistors, resistors, capacitors, etc., and its fabrication process is only in the silicon gate P well On the basis of the E/D CMOS process, the fabrication of N-channel junction field effect transistors is added. In the process, only the threshold voltage of the N-channel junction field effect transistors needs to be adjusted, which greatly simplifies the process and reduces the cost.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention shall still be covered by the claims of the present invention.

Claims (9)

1. an E/D NMOS reference voltage source, is characterized in that, comprises: A pre-reference source circuit, including an N-channel junction field effect transistor, the gate of the N-channel junction field effect transistor is grounded, the drain is connected to the power supply voltage, and the source outputs a pre-reference voltage; The E/D NMOS reference source circuit is connected to the pre-reference source circuit, receives the pre-reference voltage and outputs the reference voltage externally. 2 . The E/D NMOS reference voltage source according to claim 1 , wherein the N-channel junction field effect transistor comprises a depletion-type N-channel junction field effect transistor. 3 . 3. The E/D NMOS reference voltage source according to claim 1 or 2, wherein the E/D NMOS reference voltage source circuit comprises: a reference voltage starter circuit, connected to the pre-reference source circuit, receiving the pre-reference voltage and outputting the reference voltage to the outside; The reference voltage adjusting sub-circuit and the reference voltage enabling sub-circuit adjust the reference voltage. 4 . The E/D NMOS reference voltage source according to claim 3 , wherein the reference voltage start-up sub-circuit comprises a plurality of NMOS transistors connected in series, and the reference voltage regulator sub-circuit comprises a plurality of NMOS transistors connected in series. 5 . . 5. The E/D NMOS reference voltage source according to claim 4, wherein the reference voltage starter circuit comprises: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The drain of the first NMOS transistor is connected to the source of the N-channel junction field effect transistor, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, and the third NMOS transistor The drain of the second NMOS transistor is connected to the source of the second NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, and the source of the fourth NMOS transistor is used as the reference voltage output terminal; The gates of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected together, and connected to the reference voltage output terminal; the first NMOS tube, the second NMOS tube, the third NMOS tube The substrates of the NMOS transistor and the fourth NMOS transistor are connected together and connected to the reference voltage output terminal. 6 . The E/D NMOS reference voltage source according to claim 5 , wherein the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor comprise: depletion-mode NMOS transistors. 7 . 7. The E/D NMOS reference voltage source according to claim 6, wherein the reference voltage starter circuit comprises: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The drain of the fifth NMOS transistor is connected to the reference voltage output terminal, the drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, and the drain of the seventh NMOS transistor is connected to the first NMOS transistor. The source of the six NMOS tubes, the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube, and the source of the eighth NMOS tube is grounded; the fifth NMOS tube, the sixth NMOS tube, The gates of the seventh NMOS tube and the eighth NMOS tube are connected together and connected to the reference voltage output terminal; the substrates of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are connected together, and grounded. 8 . The E/D NMOS reference voltage source according to claim 7 , wherein the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor comprise: enhancement mode NMOS transistors. 9 . 9 . A low-dropout voltage regulator, comprising the E/D NMOS reference voltage source according to any one of claims 1 to 8 . 10 .

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