CN210377460U

CN210377460U - CPU single Data line and double DDR internal memory connecting structure

Info

Publication number: CN210377460U
Application number: CN201921166804.3U
Authority: CN
Inventors: 尹秋峰; 韩小江; 张坤
Original assignee: Jingchen Semiconductor Shenzhen Co ltd
Current assignee: Jingchen Semiconductor Shenzhen Co ltd
Priority date: 2019-07-23
Filing date: 2019-07-23
Publication date: 2020-04-21
Anticipated expiration: 2029-07-23

Abstract

The utility model provides a single Data line of CPU and two DDR memory connection structure, single Data line of CPU and two DDR memory connection structure include: the system comprises a first memory module, a second memory module, a central processor module and a Data line; one end of the Data wire is electrically connected with the CPU module, the other end of the Data wire is provided with a first branch wire and a second branch wire which are electrically connected with the Data wire, one end of the first branch wire, which is far away from the Data wire, is electrically connected with the first memory module, and one end of the second branch wire, which is far away from the Data wire, is electrically connected with the second memory module; the utility model provides a CPU single Data line and two DDR memory connection structure's second branch line is equal with the length of first branch line or the length difference is in 1mm to make the signal initial delay greatly reduced with this improve the frequency of DDR memory.

Description

CPU single Data line and double DDR internal memory connecting structure

Technical Field

The utility model relates to a semiconductor field especially relates to a single Data line of CPU and two DDR memory connection structure.

Background

In electronic products such as smart televisions, set top boxes and smart sound boxes, DDR memory frequency is a core reason for whether a system can run high performance, and for designing the DDR memory, the higher the DDR memory can run frequency, the better the system performance is;

referring to fig. 1, in a conventional connection structure design of the SOC/CPU and the DDR memory, the SOC/CPU and the DDR memory are respectively connected by 1 DDR Data pin of the SOC/CPU to 1 DDR Data pin of the DDR memory, and when the SOC/CPU needs to connect 4 DDR memories (16 bits), the SOC/CPU needs 64 separate Data pins to be respectively connected to the Data pins of the 4 DDR memories (16 bits);

referring to fig. 2, but as the market competition becomes more and more reluctant, reducing the cost of the system and the chip is the core of improving the product competitiveness; at present, an SOC/CPU reduces a 64-bit Data bandwidth to a 32-bit Data bandwidth to support 4 DDR memories with 16 bits; or the existing 32-bit Data bandwidth is reduced to 16-bit Data bandwidth to support 2 DDR memories with 16 bits; however, it is necessary to use 1Data pin of SOC/CPU to connect the same pin of 2 DDR memories, taking the CPU (16bit) to support two 16bit DDR memories as an example:

for the DDR Data pin of the CPU, the following connection methods exist:

CPU Data [0] < -to-DDR 1Data [0] and DDR2Data [0]

CPU Data 1-DDR 1Data 1 and DDR2Data 1

...

CPU Data [14] < -to-DDR 1Data [14] and DDR2Data [14]

CPU Data [15] < -to-DDR 1Data [15] and DDR2Data [15]

In the above design, it is difficult to increase the frequency of the DDR memory, which is basically within 800MHz, and the main reason for the low frequency of the DDR memory is that the initial delay of the signal due to the branch length difference is very high, as shown in fig. 3:

the length of the first branch line is: a (assuming 20mm)

The length of the second branch is: b (assume 35mm)

The branch length difference is: B-A is 35mm-20mm is 15mm

The speed of light is: 299792458m/s

Initial delay of signal due to branch length difference: length difference/speed of light (15mm)/(299792458m/s) 50ps (picosecond);

for high-speed DDR memory signal transmission, because the length difference between the first branch line and the second branch line is 15mm, when CPU Data [0] reaches two different DDR, the effective margin is directly lost by 50ps, and further, the frequency of the DDR memory cannot be increased.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problem, the utility model provides a CPU list Data line and two DDR memory connection structure and the equal isometric method of branch line of control Data line.

The utility model discloses a following technical scheme realizes:

the utility model provides a single Data line of CPU and two DDR memory connection structure, single Data line of CPU and two DDR memory connection structure include: the system comprises a first memory module, a second memory module, a central processor module and a Data line; one end of the Data wire is electrically connected with the CPU module, the other end of the Data wire is provided with a first branch wire and a second branch wire which are electrically connected with the Data wire, one end of the first branch wire, far away from the Data wire, is electrically connected with the first memory module, and one end of the second branch wire, far away from the Data wire, is electrically connected with the second memory module.

Further, the lengths of the first branch line and the second branch line are equal or the length difference is within 1 mm.

Further, the first memory module and the second memory module are both DDR memories.

Further, the central processing unit module is a CPU or an SOC.

A method for controlling branch lines of Data lines to be equal in length comprises the following steps:

s1: and (3) length measurement: respectively measuring the lengths from one end of the Data line far away from the central processing unit module to the first memory module and the second memory module;

s2: length comparison: comparing the length from one end of the Data line far away from the central processing unit module to the first memory module with the length from one end of the Data line far away from the central processing unit module to the second memory module, wherein the longest length is a first branch line;

s3: bending treatment: the second branch line is bent at a plurality of positions so that the length of the second branch line is equal to that of the first branch line or the length difference is within 1 mm.

The utility model has the advantages that:

1. the utility model provides a CPU single Data line and two DDR memory connection structure's second branch line is equal with the length of first branch line or the length difference is in 1mm to make the signal initial delay greatly reduced with this improve the frequency of DDR memory.

2. The utility model provides a method of the branch line isometric of control Data line, the process is simple and easy, and easy operation can be suitable for on the PCB board of various products.

Drawings

FIG. 1 is a schematic diagram of a conventional connection structure of an SOC/CPU and a DDR memory;

FIG. 2 is a schematic diagram of a connection structure of 1Data pin of the SOC/CPU connected with 2 DDR memories;

FIG. 3 is a schematic diagram illustrating the calculation of the initial delay of a signal;

fig. 4 is a schematic diagram of the connection structure of the CPU single Data line and the double DDR memory.

Detailed Description

For a more clear and complete description of the technical solution of the present invention, the following description is made with reference to the accompanying drawings.

Referring to fig. 4, the present invention provides a connection structure of a CPU single Data line 40 and a double DDR memory, where the connection structure of the CPU single Data line 40 and the double DDR memory includes: a first memory module 10, a second memory module 20, a central processor module 30 and a Data line 40; one end of the Data line 40 is electrically connected with the central processor module 30, the other end of the Data line 40 is provided with a first branch line 41 and a second branch line 42 which are electrically connected with the Data line 40, one end of the first branch line 41, which is far away from the Data line 40, is electrically connected with the first memory module 10, and one end of the second branch line 42, which is far away from the Data line 40, is electrically connected with the second memory module 20; the first branch line 41 and the second branch line 42 have the same length or have a length difference of 1mm or less.

In this embodiment, reducing the length difference between the first branch line 41 and the second branch line 42 can eliminate the influence of initial signal delay, thereby increasing the frequency of the DDR memory; when the length difference between the first branch line 41 and the second branch line 42 is 1mm, the initial delay of the signal caused by the branch length difference is: the length difference/optical speed is (1mm)/(299792458m/s) 3.33564ps, and compared with the original 15mm length difference, the design of 1mm branch length difference is adopted, so that the effective margin can be recovered to 46.66436ps, the frequencies of the first memory module 10 and the second memory module 20 are greatly increased, and the frequencies of the first memory module 10 and the second memory module 20 can reach 1200 MHz; when the lengths of the first branch line 41 and the second branch line 42 are equal, the T topology is completely symmetrical, the reflection waveforms of the receiving ends of the first branch line 41 and the second branch line 42 are overlapped, and have equal magnitudes and opposite directions, so that the influence of the initial delay of the signal can be completely eliminated; one of the first branch line 41 and the second branch line 42, which is short in length, is bent so that the difference in length between the first branch line 41 and the second branch line 42 is controlled to be within 1 mm.

Further, the first memory module 10 and the second memory module 20 are both DDR memories.

In this embodiment, the first memory module 10 and the second memory module 20 are both DDR memories, and the DDR memories are all referred to as DDR SDRAMs (Double Data Rate SDRAMs).

Further, the central processing unit module 30 is a CPU or an SOC.

In the present embodiment, the CPU is collectively referred to as: a Central Processing Unit (Central Processing Unit); the overall SOC is: chip level systems (System on Chip).

A method for controlling branch lines of a Data line 40 to be equal in length, the method for controlling branch lines of the Data line 40 to be equal in length comprising the steps of:

s1: and (3) length measurement: measuring the lengths from one end of the Data line 40 far away from the central processor module 30 to the first memory module 10 and the second memory module 20 respectively;

s2: length comparison: comparing the length from the end of the Data line 40 far away from the central processor module 30 to the first memory module 10 with the length from the end of the Data line 40 far away from the central processor module 30 to the second memory module 20, wherein the longest length is the first branch line 41;

s3: bending treatment: the second branch line 42 is bent at a plurality of positions so that the lengths of the second branch line 42 and the first branch line 41 are equal to each other or the difference in length is within 1 mm.

In the present embodiment, the method for controlling the branch lines of the Data line 40 to have equal lengths is simple in process and easy to operate, and can be applied to PCB boards of various products.

Of course, the present invention can also have other various embodiments, and based on the embodiments, those skilled in the art can obtain other embodiments without any creative work, and all of them belong to the protection scope of the present invention.

Claims

1. A CPU single Data line and double DDR memory connection structure is characterized in that the CPU single Data line and double DDR memory connection structure comprises: the system comprises a first memory module, a second memory module, a central processor module and a Data line; one end of the Data wire is electrically connected with the CPU module, the other end of the Data wire is provided with a first branch wire and a second branch wire which are electrically connected with the Data wire, one end of the first branch wire, which is far away from the Data wire, is electrically connected with the first memory module, and one end of the second branch wire, which is far away from the Data wire, is electrically connected with the second memory module; the lengths of the first branch line and the second branch line are equal or the length difference is within 1 mm.

2. The CPU single Data line and double DDR memory connection structure of claim 1, wherein the first memory module and the second memory module are both DDR memories.

3. The CPU single Data line and double DDR memory connection structure of claim 1, wherein the CPU module is a CPU or SOC.