CN220653601U - Multi-load DDRX interconnection equal-arm branch topology optimization structure - Google Patents

Abstract

The utility model discloses a multi-load DDRX interconnection equal-arm branch topology optimization structure, which includes a main chip. The main chip is connected with a trunk line, and the trunk line is connected with at least two branch lines, each of which is The branch line is connected to a load chip, and the characteristic impedance of the branch line is greater than the characteristic impedance of the trunk line. The utility model optimizes the characteristic impedance of the branch wiring by increasing the characteristic impedance of the branch wiring, making the impedance of the signal path consistent, improving the impedance continuity of the signal path, thereby achieving the purpose of reducing signal reflection.

Description

A multi-load DDRX interconnection equal-arm branch topology optimization structure

Technical field

The utility model relates to the technical field of PCB design, and specifically relates to a multi-load DDRX interconnection equal-arm branch topology optimization structure.

Background technique

Printed Circuit Board (PCB), also known as printed circuit board, is an important part of the physical support and signal transmission of electronic products. With the update and upgrade of DDR (Double Data Rate Synchronous Dynamic Random Access Memory) technology, the signal rate continues to increase, and the non-ideal effect of the interconnection link becomes more and more significant, mainly in the case of multiple loads. Due to the large number of branches and load chips, the influence of capacitive load is inevitable. First, ordinary vias are capacitive, and secondly, there is the parasitic capacitance on the chip package (about 0.33-0.44pF), and there is also the parasitic capacitance on the die (bare chip, before packaging) (about 0.77-2.12pF). All these capacitive effects will reduce the effective characteristic impedance of the signal transmission path, resulting in discontinuity of the signal path impedance, and then cause signal reflection, thereby restricting the realization of high-speed multi-load DDRX ("X" represents different generations of DDR technology) interconnection design.

Currently, the existing multi-load DDRX interconnection equal-arm branch topology (as shown in Figure 1) controls each segment of the same signal to the same characteristic impedance value (usually, the single-ended line impedance is controlled to 50 ohms). In fact, due to capacitance Under the influence of the load, the effective characteristic impedance of the signal path will change, resulting in discontinuity in the impedance of the signal path, thereby causing signal reflection.

The above shortcomings need to be improved.

Utility model content

In order to overcome the problem of signal path impedance discontinuity in the multi-load DDRX interconnection equal-arm branch topology in the prior art, causing signal reflection, the utility model provides a multi-load DDRX interconnection equal-arm branch topology optimization structure.

The technical solution of the present utility model is as follows:

A multi-load DDRX interconnection equal-arm branch topology optimization structure, including a main chip, the main chip is connected to a trunk line, the trunk line is connected to at least two branch lines, and each of the branch lines is connected to There is a load chip, and the characteristic impedance of the branch trace is greater than the characteristic impedance of the trunk trace.

According to the multi-load DDRX interconnection equal-arm branch topology optimization structure of the above solution, the characteristic impedance of the trunk wiring is 50 ohms, and the characteristic impedance of the branch wiring is 52.5-65 ohms.

Further, when the number of load chips is 2, the characteristic impedance of the branch trace is 52.5 ohms.

According to the multi-load DDRX interconnection equal-arm branch topology optimization structure of the above solution, the branch wiring includes a first-level branch wiring and a second-level branch wiring, and the trunk wiring is connected to at least two of the first-level branch wiring. lines, each of the first-level branch lines is connected to at least two of the second-level branch lines, each of the second-level branch lines is connected to one of the load chips, the main line and all the The characteristic impedance of the secondary branch wiring is the same, and the characteristic impedance of the first level branch wiring is greater than the characteristic impedance of the main trunk wiring.

Further, the characteristic impedance of the main trunk line and the secondary branch line is 50 ohms, and the characteristic impedance of the first level branch line is 52.5-65 ohm.

Further, when the number of load chips is 4, the characteristic impedance of the first-level branch line is 55 ohms.

Further, when the number of load chips is 8, the characteristic impedance of the first-level branch line is 60 ohms.

Further, when the number of load chips is 16, the characteristic impedance of the first-level branch line is 65 ohms.

Further, via holes are provided at both ends of the trunk trace, and via holes are provided at one end of the first-level branch trace.

Further, the length and width of all other traces except the first-level branch trace are the same.

According to the multi-load DDRX interconnection equal-arm branch topology optimization structure of the above solution, the number of branch lines is an even number.

Compared with the existing technology, the beneficial effects of this utility model are:

The multi-load DDRX interconnection equal-arm branch topology optimization structure provided by the utility model improves the wiring characteristics by increasing the characteristic impedance of the branch wiring within a certain range (that is, reducing the line width of the branch wiring under the premise of determining the stacking). The impedance is optimized to make the impedance of the signal path consistent, improving the impedance continuity of the signal path, thereby achieving the purpose of reducing signal reflection; at the same time, the characteristic impedance of the branch wiring is adjusted as the number of driven load chips changes. , the number of load chips increases, and the characteristic impedance of the branch traces increases.

Description of drawings

In order to explain the technical solutions in the embodiments of the present invention more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of the present utility model. For some embodiments of the new type, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a multi-load DDRX interconnection equal-arm branch topology in the prior art. Z0 in the figure represents the characteristic impedance of each section of wiring;

Figure 2 is a structural schematic diagram of the multi-load DDRX interconnection equal-arm branch topology optimization structure in Embodiment 1 of the present invention. In the figure, Z0 and Z1 represent the characteristic impedance of each section of wiring;

Figure 3 is a signal receiving waveform diagram of the load chip in Figure 1;

Figure 4 is the signal receiving waveform diagram of the load chip in Figure 2;

Figure 5 is a structural schematic diagram of the multi-load DDRX interconnection equal-arm branch topology optimization structure in Embodiment 2 of the present invention. In the figure, Z0 and Z1 represent the characteristic impedance of each section of wiring;

Figure 6 shows the structure diagram of microstrip line impedance calculation;

Figure 7 is a structural diagram of stripline impedance calculation.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model more clear, the present utility model will be further described in detail below with reference to the drawings and examples. It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures. At the same time, it is stated that the embodiments described below are only used to explain the present utility model and are not used to limit the present utility model.

It should be noted that the terms "set", "connection" and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can It can be directly connected, or it can be indirectly connected through an intermediate medium. It can be the internal connection between two elements or the interactive relationship between two elements, unless otherwise clearly limited. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the applied product is customarily placed when used, or the orientation or positional relationship commonly understood by those skilled in the art, or the The orientation or positional relationship in which the applied product is customarily placed during use is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, therefore It should not be construed as a limitation on this application.

Example 1

Please refer to Figure 2. This embodiment provides a multi-load DDRX interconnection equal-arm branch topology optimization structure, including a main chip Memory Controller. The main chip Memory Controller is connected to a backbone trace L1, and the backbone trace L1 is connected to at least two Level branch trace L2. Each first-level branch trace L2 is connected to at least two second-level branch traces L3. All other traces except the first-level branch trace L2 have the same length and width. Each second-level branch trace L2 Each branch trace L3 is connected to a load chip DRAM, both ends of the trunk trace L1 are provided with via holes, and one end of the first-level branch trace L2 is provided with a via hole via. Among them, the characteristic impedance Z0 of the trunk trace L1 and the secondary branch trace L3 are both 50 ohms. The characteristic impedance Z1 of the first-level branch trace L2 is greater than the characteristic impedance Z0 of the trunk trace L1. The characteristic impedance Z0 of the first-level branch trace L2 is The characteristic impedance Z1 is 52.5-65 ohms.

This embodiment optimizes the characteristic impedance of the wiring by increasing the characteristic impedance Z1 of the first-level branch wiring L2 within a certain range (that is, reducing the line width of the first-level branch wiring L2 under the premise that the stacking is determined), so that the signal The impedance of the path tends to be consistent, which improves the impedance continuity of the signal path, thereby achieving the purpose of reducing signal reflection.

Figure 3 is a signal receiving waveform diagram of the load chip DRAM in the existing topology solution. Figure 4 is a signal receiving waveform diagram of the load chip DRAM after the characteristic impedance of the first-level branch line L2 is adjusted to 55 ohms according to the present invention. By comparison, it can be found , the eye diagram of this utility model that performs capacitive compensation on the first-level branch line L2 has a larger eye height, which is 78mV higher than the existing topology solution, which is equivalent to increasing the system margin by 17%. This utility model Compared with the existing topology solution, the solution can significantly improve the impedance continuity of the signal path, thereby achieving the purpose of reducing signal reflection.

In a preferred embodiment, as the number of driven load chip DRAMs changes, the characteristic impedance Z1 of the first-level branch line L2 is adjusted. As the number of load chip DRAMs increases, the characteristic impedance Z1 of the first-level branch line L2 increases accordingly. increase, at the same time, the processing capacity of the board factory should be comprehensively considered and the line width should be adjusted reasonably. When the characteristic impedance Z0 of the trunk trace L1 and the secondary branch trace L3 is controlled at 50 ohms, and the number of load chip DRAMs is 4, the characteristic impedance Z1 of the first-level branch trace L2 is adjusted to 52.5 or 55 Ohms; when the number of load chip DRAMs is 8, the characteristic impedance Z1 of the first-level branch trace L2 is adjusted to 60 ohms; when the number of load chip DRAMs is 16, the characteristic impedance Z1 of the first-level branch trace L2 is adjusted is 65 ohms.

In a preferred embodiment, the number of primary branch lines L2 and secondary branch lines L3 is both an even number, which can further make the characteristic impedance of the signal path consistent and improve impedance continuity.

Example 2

Please refer to Figure 5. This embodiment provides a multi-load DDRX interconnection equal-arm branch topology optimization structure, including a main chip Memory Controller. The main chip Memory Controller is connected to a trunk line L1, and the trunk line L1 is connected to at least two branches. Trace L3, the length and width of each branch trace L3 are the same, each branch trace L3 is connected to a load chip DRAM, and vias are provided at both ends of the trunk trace L1. Among them, the characteristic impedance Z0 of the trunk trace L1 is the same as 50 ohms, the characteristic impedance Z1 of the branch trace L3 is greater than the characteristic impedance Z0 of the trunk trace L1, and the characteristic impedance Z1 of the branch trace L3 is 52.5-65 ohms.

This embodiment optimizes the characteristic impedance of the trace by increasing the characteristic impedance Z1 of the branch trace L3 within a certain range (that is, reducing the line width of the branch trace L3 under the premise that the stacking is determined), so that the impedance of the signal path tends to be In line with each other, the impedance continuity of the signal path is improved, thereby achieving the purpose of reducing signal reflection.

In a preferred embodiment, as the number of driven load chip DRAMs changes, the characteristic impedance Z1 of the branch line L3 is adjusted. As the number of load chip DRAMs increases, the characteristic impedance Z1 of the branch line L3 increases accordingly. At the same time, The processing capacity of the board factory should be comprehensively considered and the line width should be adjusted reasonably. When the trunk line L1 is controlled at 50 ohms and the number of load chip DRAMs is 2, the characteristic impedance Z1 of the branch line L3 is adjusted to 52.5 ohms; when the number of load chip DRAMs is 4, the branch line L3 The characteristic impedance Z1 of the line L3 is adjusted to 55 ohms; when the number of load chip DRAMs is 8, the characteristic impedance Z1 of the branch line L3 is adjusted to 60 ohms; when the number of load chip DRAMs is 16, the branch line L3 The characteristic impedance Z1 is adjusted to 65 ohms.

In a preferred embodiment, the number of branch traces L3 is an even number, which can further make the characteristic impedance of the signal path consistent and improve impedance continuity.

In PCB design, in order to reduce or increase the characteristic impedance (Zo) of the trace, on the premise that the stackup is determined (the stackup of different boards will be different, which means that the Er and T in the trace characteristic impedance calculation formula , H are different. If the single board stackup is determined, Er, T, H will be determined accordingly). According to the microstrip line impedance and stripline impedance calculation formulas, the corresponding trace width can be increased or decreased (in the formula W) to achieve impedance adjustment:

As shown in Figure 6, the impedance of the microstrip line (surface line):

(Valid·when·0.1＜W/H＜2.0·and·1＜Er＜15)

Zo represents the characteristic impedance; Er represents the dielectric constant; W represents the trace width; T represents the copper thickness of the trace; H represents the spacing between the trace and the adjacent reference plane.

As shown in Figure 7, stripline impedance (inner layer wiring):

(Valid·when·W/H<0.35·and·T/H<0.25) Here, H represents the distance between adjacent reference planes.

It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the protection scope of the appended claims of the present invention.

The utility model patent has been exemplarily described above in conjunction with the accompanying drawings. Obviously, the implementation of the utility model patent is not limited by the above methods, as long as various improvements of the method concept and technical solution of the utility model patent are adopted, or If the concepts and technical solutions of the utility model patent are directly applied to other situations without improvement, they will all fall within the protection scope of the utility model.

Claims (10)

1. The utility model provides a multi-load DDRX interconnection equal arm branch topology optimization structure, includes the main chip, the main chip is connected with the trunk wiring, the trunk wiring is connected with two at least branch wirings, every branch wiring is connected with a load chip, its characterized in that, the characteristic impedance of branch wiring is greater than the characteristic impedance of trunk wiring.

2. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 1, wherein the characteristic impedance of the main trace is 50 ohms and the characteristic impedance of the branch trace is 52.5-65 ohms.

3. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 2, wherein the characteristic impedance of the branch trace is 52.5 ohms when the number of load chips is 2.

4. The multi-load DDRX interconnect equal-arm branch topology optimization structure of claim 1, wherein the branch trace comprises a first-stage branch trace and a second-stage branch trace, the trunk trace is connected with at least two first-stage branch traces, each first-stage branch trace is connected with at least two second-stage branch traces, each second-stage branch trace is connected with one load chip, the characteristic impedance of the trunk trace and the characteristic impedance of the second-stage branch trace are the same, and the characteristic impedance of the first-stage branch trace is larger than the characteristic impedance of the trunk trace.

5. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 4, wherein the characteristic impedance of the main trace and the secondary branch trace are both 50 ohms, and the characteristic impedance of the primary branch trace is 52.5-65 ohms.

6. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 5, wherein the characteristic impedance of the first stage branch trace is 55 ohms when the number of load chips is 4.

7. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 5, wherein the characteristic impedance of the primary branch trace is 60 ohms when the number of load chips is 8.

8. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 5, wherein the characteristic impedance of the first stage branch trace is 65 ohms when the number of load chips is 16.

9. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 4, wherein the two ends of the trunk trace are provided with vias, and one end of the primary branch trace is provided with a via.

10. The multi-load DDRX interconnect equal arm branch topology optimization structure of claim 1, wherein the number of branch traces is even.