CN210182390U

CN210182390U - Non-packaging diode

Info

Publication number: CN210182390U
Application number: CN201920611003.7U
Authority: CN
Inventors: Nianbo Wu; 吴念博
Original assignee: Suzhou Goodark Electronics Co ltd
Current assignee: Suzhou Goodark Electronics Co ltd; Suzhou Good Ark Electronics Co Ltd
Priority date: 2019-04-30
Filing date: 2019-04-30
Publication date: 2020-03-24
Anticipated expiration: 2029-04-30

Abstract

A package-free diode; the LED chip comprises an insulating hard radiating substrate, insulating heat-conducting glue and a diode chip; the lower surface of the insulating hard heat dissipation substrate is adhered and fixed with the upper surface of the diode chip through insulating heat conduction glue; the diode chip comprises a silicon chip substrate, wherein an N + region is formed on the lower surface of the silicon chip substrate through first impurity doping, a P + region is formed through second impurity doping, and the N + region and the P + region are arranged at intervals; the N + region and the P + region are formed on the same side of the silicon chip substrate, and metal electrodes are arranged on the surfaces of the N + region and the P + region to form two metal electrodes on the same side. The utility model discloses a simplify the encapsulation by a wide margin, can reduce material cost, labour cost, realize at most can reduce 30% processing cost to can promote the production efficiency of unit interval.

Description

Non-packaging diode

Technical Field

The utility model relates to a processing manufacturing field of diode, concretely relates to exempt from to encapsulate diode.

Background

The diode is widely used in various circuits, and the diodes are arranged at any circuit, so that alternating current is converted into direct current by utilizing the characteristic of unidirectional conduction, and a terminal component of the circuit can obtain stable direct current input. The conventional method for manufacturing a rectifying diode is to use an N-type < 111 > crystal orientation single crystal silicon wafer as a basic material, perform boron doping on the upper surface of the silicon wafer to form a flat P region, perform phosphorus diffusion on the lower surface of the silicon wafer to form a flat N region, perform photolithography, metallization, alloying and other processes to finally form a PN structure and an electrode metal of the diode, and manufacture a rectifying diode chip (also referred to as "grain" in the industry). And finally, manufacturing a final diode product through a packaging process, wherein the traditional packaging process generally comprises frame assembly, solder paste spot welding, crystal grain assembly, welding combination, cleaning, injection molding epoxy molding, curing, glue removal, rib cutting and pin bending, reflow soldering, electroplating, annealing, testing, laser printing and packaging.

The disadvantages of the prior art include:

firstly, the PN junction is formed by adopting the process of diffusing on two sides of the chip, which is not beneficial to the miniaturization of the product;

two sides of the chip are provided with electrodes and lead frames, the thickness is further increased, the complexity of a circuit connection process is increased, the chip cannot be in direct contact with an outer radiating fin in a subsequent packaging procedure, and the radiating effect is also influenced;

and thirdly, too many processes of the packaging process result in resource waste, cost improvement and overlong production period, and the excessive processes also improve the probability of processing errors.

Therefore, how to solve the above-mentioned deficiencies of the prior art is a problem to be solved by the present invention.

Disclosure of Invention

The utility model aims at providing an exempt from to encapsulate diode.

In order to achieve the above purpose, the utility model adopts the technical scheme that:

a package-free diode; the LED chip comprises an insulating hard radiating substrate, insulating heat-conducting glue and a diode chip from top to bottom in sequence;

the lower surface of the insulating hard heat dissipation substrate is fixedly adhered to the upper surface of the diode chip through the insulating heat conduction glue;

the diode chip comprises a silicon chip substrate with an N-type or P-type < 111 > crystal orientation, wherein the lower surface of the diode chip is provided with an N + region formed by doping first impurities and a P + region formed by doping second impurities, and the N + region and the P + region are arranged at intervals; the N + region and the P + region are formed on the same side of the silicon wafer substrate, and metal electrodes are arranged on the surfaces of the N + region and the P + region to form two metal electrodes which are located on the same side of the silicon wafer substrate.

The relevant content in the above technical solution is explained as follows:

1. in the above solution, the insulating hard heat dissipation substrate is a ceramic substrate, or a silicon carbide substrate or other substrates with the same or similar functions may be selected, and the ceramic substrate is preferred because the expansion coefficient of the ceramic substrate is closest to that of silicon, which can reduce the package stress.

2. In the above scheme, the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping.

3. In the above scheme, the silicon wafer substrate has an N-type < 111 > crystal orientation, and the edge region of the P + region is provided with a trench filled with a glass passivation layer.

4. In the above scheme, the silicon wafer substrate has a P-type < 111 > crystal orientation, and the edge region of the N + region is provided with a trench filled with a glass passivation layer.

5. In the above scheme, the number of the N + region and the number of the P + region are both at least one.

6. In the above-mentioned solution, the N + region and the P + region are arranged in parallel at an interval in the horizontal direction, or one of the N + region and the P + region is surrounded by the other in the horizontal direction.

The utility model discloses a theory of operation and advantage as follows:

the utility model relates to a non-encapsulated diode; the LED chip comprises an insulating hard radiating substrate, insulating heat-conducting glue and a diode chip; the lower surface of the insulating hard heat dissipation substrate is adhered and fixed with the upper surface of the diode chip through insulating heat conduction glue; the diode chip comprises a silicon chip substrate, wherein an N + region is formed on the lower surface of the silicon chip substrate through first impurity doping, a P + region is formed through second impurity doping, and the N + region and the P + region are arranged at intervals; the N + region and the P + region are arranged at the same side, and metal electrodes are arranged on the surfaces of the N + region and the P + region.

Compared with the prior art, the utility model has the advantages that:

the N + region and the P + region of the diode chip are positioned on the same surface of a silicon chip substrate, and a PN junction is formed by adopting a process of diffusing the same surface of the chip, so that the miniaturization of a product is facilitated, and the quality of high reliability can be ensured;

electrodes and lead frames are not needed to be arranged on two surfaces of the chip, the complexity of the circuit connection process is reduced, the chip can be in direct contact with an outer side radiating fin in the packaging process, and the radiating effect is greatly improved;

third, the conventional copper lead wire can be cancelled by combining the printing technology, the flow is greatly simplified, and the cost is saved; meanwhile, due to the increase of the integration level, the volume of the device can be greatly reduced;

fourthly, the heat-conducting resin can be directly applied to a circuit after being pasted with an insulating hard heat-radiating substrate, so that epoxy is eliminated, thermal resistance is reduced, and heat-radiating performance is improved;

fifthly, a shallow groove of 20-40 microns is adopted, and a PN junction is protected in a manner of passivating a polycrystalline silicon passivation composite film layer and glass, so that the process flow is simple, the consumption of chemicals is low, the forward power consumption is low, the manufacturing cost is low, and the quality is high;

forming a U-shaped PN junction through selective diffusion, increasing the effective area of the PN junction and obviously reducing the power consumption of the diode when the diode is applied in a circuit;

and seventhly, the structure is suitable for common rectifier diodes, fast recovery diodes, TVS protection diodes, voltage-regulator tubes and the like.

To sum up, the utility model discloses broken traditional diode packaging structure and technology, under the prerequisite of guaranteeing diode heat dissipation and insulating properties for the packaging technology of diode is more simple, effective. The method is favorable for reducing the processing cost of diode semiconductor devices in large batch, reducing the use energy consumption of clients, reducing the waste of resources (eliminating the consumption of materials such as resin, soldering tin, copper leads and the like), and contributing to environmental protection.

Compared with the traditional diode packaging structure and process, the utility model discloses a simplify the encapsulation by a wide margin, can reduce material cost, labour cost, realize at most can reduce 30% processing cost to can promote the production efficiency of unit interval.

Drawings

Fig. 1 is a perspective view of a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a first embodiment of the present invention;

fig. 3 is a schematic bottom view of a first embodiment of the present invention;

FIG. 4 is an exploded perspective view of a first embodiment of the present invention;

fig. 5 is a schematic structural diagram of a diode chip according to an embodiment of the present invention;

fig. 6 is a perspective view of a second embodiment of the present invention;

fig. 7 is a schematic bottom view of a second embodiment of the present invention;

fig. 8 is a perspective view of a third embodiment of the present invention;

fig. 9 is a schematic bottom view of a third embodiment of the present invention.

In the above drawings: 1. an insulating hard heat dissipation substrate; 2. insulating heat-conducting glue; 3. a diode chip; 5. a silicon wafer substrate; an N + region; a P + region; 8. a trench; 9. a glass passivation layer; 10. an electrode; d. distance.

Detailed Description

The invention will be further described with reference to the following drawings and examples:

the first embodiment is as follows: referring to fig. 1-5, a non-encapsulated diode; the LED chip comprises an insulating hard heat dissipation substrate 1, insulating heat conduction glue 2 and a diode chip 3 from top to bottom in sequence.

The lower surface of the insulating hard heat dissipation substrate 1 is fixedly adhered to the upper surface of the diode chip 3 through the insulating heat conduction glue 2. The insulating hard heat dissipation substrate 1 is preferably a ceramic substrate because the expansion coefficient of the ceramic substrate is closest to that of silicon, and the packaging stress can be reduced. Silicon carbide substrates or other substrates of the same or similar function may also be used.

As shown in fig. 5, the diode chip 3 includes a silicon substrate 5, an N + region 6 is formed on a lower surface of the silicon substrate by first impurity doping, a P + region 7 is formed by second impurity doping, and the N + region 6 and the P + region 7 are spaced apart from each other; the N + region 6 and the P + region 7 are formed on the same side of the silicon wafer substrate 5, and metal electrodes 10 are formed on the surfaces of the N + region and the P + region through metal layer deposition, so that the two metal electrodes 10 are located on the same side of the silicon wafer substrate 5.

The first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping. The surface of the N + region 6 has a doping concentration of at least 10²¹atm/cm³The diffusion depth is 30-50 μm; the surface of the P + region 7 has a doping concentration of at least 10²¹atm/cm³The diffusion depth is 50 to 70 μm.

The silicon wafer substrate 5 is in an N-type < 111 > crystal orientation, and a groove 8 is formed in the edge area of the P + area 7. Or, the silicon wafer substrate 5 is in a P-type < 111 > crystal orientation, and a groove 8 is formed in the edge region of the N + region 6.

The depth of the groove 8 is 20-40 um; the grooves 8 are filled with glass cement, the thickness of the glass cement is 25-35 mu m, and a glass passivation layer 9 is formed through high-temperature sintering.

The number of the N + regions 6 and the number of the P + regions 7 are one, and the N + regions and the P + regions are arranged in parallel at intervals in the horizontal direction. Wherein, the distance d between the N + area 6 and the P + area 7 is 200-300 um. The distance parameter is selected because the distance between the N + region 6 and the P + region 7 must be designed to be within a certain range, when an electric field is applied, the space charge region of the PN junction of the diode expands outwards, the distance between the N + region 6 and the P + region 7 is too close, which results in insufficient broadening of the space charge region, the diode breaks down in advance and does not meet the voltage requirement of the design, and if the distance is too wide, the size is increased and the material is wasted.

The utility model discloses the processing technology of diode includes following step:

step one, coating insulating heat-conducting glue 2 on the upper surface, namely a non-welding surface, of the diode chip 3, and attaching the insulating hard heat-radiating substrate 1 through the insulating heat-conducting glue 2.

And step two, baking the solid glue at high temperature, wherein the baking temperature is 150 +/-10 ℃, and the baking time is 0.5 +/-0.1 h. Thus, the wafer is processed.

And step three, after cooling, attaching a layer of blue film on the upper surface of the insulating hard heat-radiating substrate 1, and then dividing the substrate into a plurality of single crystal grains according to the size designed by a manufacturer by using a special wafer cutting machine, namely dividing the substrate into a plurality of diode chips 3. And the blue film is a PVC film with certain adhesiveness, is a universal carrier for wafer cutting, and is removed after the fifth step.

And step four, loading the blue film carried products on an automatic testing machine, carrying out electrical test on the whole number of the blue film carried products, carrying out laser printing on the tested finished products, loading qualified products into a carrier tape, and carrying out heat sealing on the surface of the carrier tape. The selection and use of the automatic testing machine, the specific manner of electrical testing, etc. are conventional techniques, and are not described in detail.

Wherein the insulating hard heat dissipation substrate 1 is a ceramic substrate, the thickness of the insulating hard heat dissipation substrate is 0.3-0.6 mm, the heat conductivity is 100-300W/m.K, and the linear thermal expansion coefficient is 2.4-4.8 (10)^-6K), the insulation strength is 10-20 kV/mm, and the volume resistivity is more than 10¹⁰And omega, m, wherein AN AN3170 model can be selected in practical application. The ceramic substrate has high heat conductivity and high insulation property, can improve the strength of the product, and is beneficial toThe diode chip 3 is protected, and the heat dissipation and insulation of the diode chip 3 are ensured.

The thickness of the insulating heat-conducting glue 2 is 0.02-0.05 mm, the heat conductivity is 1-3W/m.K, the insulating strength is 10-20 kV/mm, and the volume resistivity is less than 10¹⁵Omega, m, tensile modulus at 25 ℃ of 5000-10000N/mm²(psi) and a tensile modulus at 200 ℃ of 50 to 200N/mm²(psi), model 282-EN may be selected.

Example two: referring to fig. 6-7, a non-encapsulated diode; the difference from the first embodiment is that: the N + region 6 and the P + region 7 are each plural in number and are surrounded one by the other in the horizontal direction. Other parts are the same as those in the first embodiment, and thus are not described again.

Example three: referring to fig. 8-9, a non-encapsulated diode; the difference from the first embodiment is that: the number of the N + regions 6 and the number of the P + regions 7 are both multiple and are arranged in parallel at intervals in the horizontal direction. Other parts are the same as those in the first embodiment, and thus are not described again.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.

Claims

1. A package-free diode; the method is characterized in that:

the LED chip comprises an insulating hard radiating substrate, insulating heat-conducting glue and a diode chip from top to bottom in sequence;

the diode chip comprises a silicon chip substrate, wherein an N + region is formed on the lower surface of the silicon chip substrate through first impurity doping, a P + region is formed through second impurity doping, and the N + region and the P + region are arranged at intervals; the N + region and the P + region are formed on the same side of the silicon wafer substrate, and metal electrodes are arranged on the surfaces of the N + region and the P + region to form two metal electrodes which are located on the same side of the silicon wafer substrate.

2. The diode of claim 1, wherein: the insulating hard heat dissipation substrate is a ceramic substrate.

3. The diode of claim 1, wherein: the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping.

4. The diode of claim 1, wherein: the silicon wafer substrate is in an N-type < 111 > crystal orientation, a groove is formed in the edge area of the P + area, and a glass passivation layer is filled in the groove.

5. The diode of claim 1, wherein: the silicon wafer substrate is in a P-type < 111 > crystal orientation, a groove is formed in the edge area of the N + area, and a glass passivation layer is filled in the groove.

6. The diode of claim 1, wherein: the number of the N + region and the number of the P + region are both at least one.

7. The diode of claim 1, wherein: the N + region and the P + region are arranged in parallel at an interval in the horizontal direction, or one of the N + region and the P + region is surrounded by the other in the horizontal direction.