CN210111976U - Clock phase adjusting device, digital system and signal transmission system - Google Patents

Abstract

A clock phase adjusting device, a digital system and a signal transmission system are provided, wherein the clock phase adjusting device comprises: the phase-locked loop comprises a first clock for generating a first clock signal, a phase-locked loop for receiving the first clock signal and generating a high-frequency clock signal and a low-frequency clock signal according to the first clock signal, a serial-parallel converter for generating a parallel clock signal of a second clock signal according to the high-frequency clock signal and the low-frequency clock signal, and a controller for adjusting the output phase of the phase-locked loop according to the parallel clock signal so that the phase difference between the low-frequency clock signal and the second clock signal reaches a preset difference range. The phase difference between the low-frequency clock signal output by the phase-locked loop and the second clock signal from the outside can be minimized through the device, the consistency of the phase relation between the local system clock and the external system clock is achieved to the maximum extent, and meanwhile, the problems of power consumption and radiation caused by the fact that the second clock signal is transmitted all the time in the prior art are solved.

Description

Clock phase adjusting device, digital system and signal transmission system

Technical Field

The invention relates to the technical field of digital systems, in particular to a clock phase adjusting device, a digital system and a signal transmission system.

Background

The signal transmission between different digital systems is always one of the important problems required to face in the multi-system digital design, and the technical scheme adopted usually is to perform asynchronous processing on the signal to be transmitted in another clock domain, perform multi-beat delay processing on the signal or store the signal in an asynchronous FIFO.

For example, in the digital system illustrated in fig. 1, the FPGA1 needs to align the system clock 2 of the FPGA2 with the system clock 1 of the FPGA1 during the transmission of information to the FPGA2, so as to ensure the validity of the signals during the transmission. In order to meet the condition, in the prior art, the FPGA1 directly transmits the clock 1 with the frequency of AHz to the FPGA2, the clock 1 outputs the clock 2 with the same frequency and phase as the clock 1 after passing through the phase-locked loop of the FPGA2, and the clock 2 is used as the system clock of the FPGA 2. Although the digital system is designed in such a way that the clock phase time can be aligned, the clock 1 must be always in a transmission state, which may generate certain power consumption and heat, and also may generate a radiation effect, thus affecting the stability of other surrounding circuits, and adversely affecting the application of the digital system constituted by the FPGA.

Disclosure of Invention

The invention mainly solves the technical problem of how to avoid the phenomena of power consumption and radiation caused by the constant transmission of clock signals in the existing digital system. In order to solve the above technical problems, the present application provides a clock phase adjusting apparatus, a digital system, and a signal transmission system.

According to a first aspect, there is provided in an embodiment a clock phase adjustment apparatus comprising:

a first clock for generating a first clock signal;

the phase-locked loop is connected with the first clock, and is used for receiving the first clock signal and generating a high-frequency clock signal and a low-frequency clock signal according to the first clock signal, wherein the high-frequency clock signal and the low-frequency clock signal are used for forming various output phases of the phase-locked loop;

the serial-parallel converter is connected with the phase-locked loop and is also used for being connected with an external second clock, and the serial-parallel converter is used for receiving the high-frequency clock signal, the low-frequency clock signal and a second clock signal from the second clock and is used for generating a parallel clock signal of the second clock signal according to the high-frequency clock signal and the low-frequency clock signal;

and the controller is connected with the serial-parallel converter and the phase-locked loop and used for receiving the parallel clock signal and adjusting the output phase of the phase-locked loop according to the parallel clock signal so as to enable the phase difference between the low-frequency clock signal and the second clock signal to reach a preset difference range.

The phase-locked loop comprises a first input end, a first output end, a second output end and a control end; the first input end is connected with the first clock and used for receiving the first clock signal; the first output end and the second output end are respectively used for outputting a high-frequency clock signal and a low-frequency clock signal corresponding to the first clock signal; the control end is connected with the controller and used for receiving a control signal of the controller, and the control signal is used for adjusting the high-frequency clock signal and the low-frequency clock signal to configure any output phase of the phase-locked loop.

The serial-to-parallel converter comprises a second input end, a third input end, a fourth input end and a third output end; the second input terminal is used for receiving a second clock signal from the second clock; the third input end and the fourth input end are respectively connected with the first output end and the second output end of the phase-locked loop and are respectively used for receiving the high-frequency clock signal and the low-frequency clock signal; the third output end is connected with the controller; and the serial-parallel converter performs shift conversion on the second clock signal by using the low-frequency clock signal, samples the shift-converted second clock signal by using the high-frequency clock signal, obtains the parallel clock signal and outputs the parallel clock signal from the third output end.

The controller is configured to receive the parallel clock signal and adjust an output phase of the phase locked loop according to the parallel clock signal, and includes: the controller determines the phase difference between the low-frequency clock signal and the second clock signal according to the format of the received parallel clock signal; the controller judges that the phase difference is out of the difference range, and then adjusts the high-frequency clock signal and the low-frequency clock signal through the control signal to configure the next output phase of the phase-locked loop; if the controller judges that the phase difference is within the difference range, the high-frequency clock signal and the low-frequency clock signal are locked through the control signal so as to keep the output phase of the phase-locked loop; and the controller controls the serial-to-parallel converter to stop receiving the second clock signal from the second clock.

The high-frequency clock signal and the low-frequency clock signal are both frequency multiplication signals of the second clock signal, the frequency multiplication value of the low-frequency clock signal compared with the second clock signal is 1, and the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 8, 16 or 32.

The frequency multiplication value of the high-frequency clock signal compared with the second clock signal is used for setting the serial-parallel conversion bit number of the serial-parallel converter and setting a preset difference range in the controller; if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 8, the serial-parallel conversion bit number of the serial-parallel converter is 8, and the difference value range preset in the controller is 0-45 degrees; if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 16, the serial-parallel conversion bit number of the serial-parallel converter is 16, and the preset difference range in the controller is 0-22.5 degrees; and if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 32, the serial-parallel conversion bit number of the serial-parallel converter is 32, and the difference value range preset in the controller is 0-11.25 degrees.

According to a second aspect, there is provided in one embodiment a digital system comprising:

the first digital equipment is provided with a second clock, and the second clock is used for generating a second clock signal;

a second digital device comprising the clock phase adjusting apparatus of the first aspect, wherein the serial-to-parallel converter is connected to the first digital device for receiving a second clock signal from the first digital device; the controller is also connected with the first digital device and is used for controlling the first digital device to stop sending the second clock signal to the serial-parallel converter when the phase difference between the low-frequency clock signal and the second clock signal reaches a preset difference range.

The first digital device sends the second clock signal to the second digital device when the first digital device or the second digital device is started.

According to a third aspect, an embodiment provides a signal transmission system comprising the digital system of the second aspect, further comprising a signal transmitting device cooperating with the first digital device and a signal receiving device cooperating with the second digital device;

the signal transmitting device is used for transmitting a signal to the signal receiving device after the first digital device responds to the control of the second digital device and stops transmitting the second clock signal to the serial-parallel converter;

and the signal receiving equipment is used for carrying out synchronous processing on the received signals by using the low-frequency clock signals generated by the serial-parallel converter after the signals sent by the signal sending equipment are received.

The beneficial effect of this application is:

according to the clock phase adjusting device, the digital system and the signal transmission system of the embodiment, the clock phase adjusting device comprises: the phase-locked loop comprises a first clock for generating a first clock signal, a phase-locked loop for receiving the first clock signal and generating a high-frequency clock signal and a low-frequency clock signal according to the first clock signal, a serial-to-parallel converter for receiving the high-frequency clock signal, the low-frequency clock signal and a second clock signal and generating a parallel clock signal of the second clock signal according to the high-frequency clock signal and the low-frequency clock signal, and a controller for receiving the parallel clock signal and adjusting the output phase of the phase-locked loop according to the parallel clock signal so that the phase difference between the low-frequency clock signal and the second clock signal reaches a preset difference range. On the first hand, due to the cooperation of the phase-locked loop and the serial-parallel converter, the controller can flexibly adjust the output phase of the phase-locked loop according to the parallel clock signal output by the serial-parallel converter, so that the phase difference between the low-frequency clock signal output by the phase-locked loop and the second clock signal from the outside is minimized, and the consistency of the phase relation between the local system clock and the external system clock is maximized; in a second aspect, for a digital system constructed by the clock phase adjusting apparatus, the second digital device can more accurately lock the output phase of the phase-locked loop during the period when the first digital device sends the second clock signal for a period of time, thereby avoiding the situation that the first digital device needs to send the second clock signal all the time in the past, so that the power consumption and radiation problems caused by the transmission of the second clock signal all the time can be reduced, and the communication stability during signal transmission is enhanced.

Drawings

FIG. 1 is a schematic diagram of a conventional digital system;

FIG. 2 is a schematic structural diagram of a clock phase adjusting apparatus according to the present application;

FIG. 3 is a block diagram of a digital system of the present application;

fig. 4 is a schematic structural diagram of a signal transmission system according to the present application;

FIG. 5 is a schematic diagram of phase relationship between the low frequency clock signal and the second clock signal, wherein FIG. 5a is a phase relationship of phase difference within 0-45 °, FIG. 5b is a phase relationship of phase difference within 45-90 °, FIG. 5c is a phase relationship of phase difference within 90-135 °, FIG. 5d is a phase relationship of phase difference within 135-180 °, FIG. 5e is a phase relationship of phase difference within 180-225 °, FIG. 5f is a phase relationship of phase difference within 225-270 °, FIG. 5g is a phase relationship of phase difference within 270-315 °, and FIG. 5h is a phase relationship of phase difference within 315-360 °.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

For the purpose of clearly understanding the technical aspects of the present application, the following technical terms are explained herein.

The FPGA, as a programmable logic device, has high integration level and abundant logic resources, is very convenient to develop, and has unique advantages in digital signal processing or hardware algorithm realization due to high FPGA processing speed.

Serial-to-parallel conversion is a technology for converting between two transmission modes, namely serial transmission and parallel transmission. Parallel and serial input and output are typically implemented with the aid of shift registers, often configured as "serial input, parallel output" (SIPO) or "parallel input, serial output" (PISO). Where configured as SIPO, this configuration allows data to be converted from a serial format to a parallel format.

The phase-locked loop is a feedback control circuit, PLL for short, and is characterized in that the frequency and phase of an internal oscillation signal of the loop are controlled by using an externally input reference signal. Many electronic devices normally operate by requiring an external input signal to be synchronized with an internal oscillating signal, which can be accomplished using a phase-locked loop. Phase-locked loops are commonly used in closed-loop tracking circuits because they allow for automatic tracking of the frequency of the input signal with respect to the frequency of the output signal. In the working process of the phase-locked loop, when the frequency of the output signal is equal to that of the input signal, the phase difference between the output voltage and the input voltage is kept constant, namely the phase of the output voltage and the phase of the input voltage are locked, which is the origin of the name of the phase-locked loop. In the phase-locked loop, when the frequency of the output signal reflects the frequency of the input signal in proportion, the output voltage and the input voltage keep a fixed phase difference value, so that the phases of the output voltage and the input voltage are locked.

The technical solution of the present application will be described below by some embodiments.

The first embodiment,

Referring to fig. 2, the present application provides a clock phase adjusting apparatus 1, which mainly includes a first clock 11, a phase locked loop 12, a serial-to-parallel converter 13 and a controller 14, which are respectively described below.

The first clock 11 is used to generate a first clock signal.

The phase locked loop 12 is coupled to the first clock for receiving the first clock signal and generating a high frequency clock signal and a low frequency clock signal based on the first clock signal, where the high frequency clock signal and the low frequency clock signal are used to form the plurality of output phases of the phase locked loop 12.

A serial to parallel converter 13 is connected to the phase locked loop 12 and is further adapted to be connected to an external second clock 21, the serial to parallel converter 13 being adapted to receive a high frequency clock signal, a low frequency clock signal and the second clock signal from the second clock 21 and being adapted to generate a parallel clock signal of the second clock signal based on the high frequency clock signal and the low frequency clock signal.

The controller 14 is connected to the serial-to-parallel converter 13 and the phase locked loop 12, and is configured to receive the parallel clock signal and adjust the output phase of the phase locked loop 12 according to the parallel clock signal, so that the phase difference between the low frequency clock signal and the second clock signal reaches a preset difference range.

Further, the phase locked loop 12 comprises a first input terminal 121, a first output terminal 122, a second output terminal 123 and a control terminal 124. The first input end 121 is connected to the first clock 11, and is configured to receive a first clock signal; the first output end 122 and the second output end 123 are respectively used for outputting a high-frequency clock signal and a low-frequency clock signal corresponding to the first clock signal; the control terminal 124 is connected to the controller 14 for receiving a control signal of the controller 14, and the control signal is used for adjusting the high frequency clock signal and the low frequency clock signal to configure any output phase of the phase locked loop 12.

Further, the serial-to-parallel converter 13 includes a second input 131, a third input 132, a fourth input 133 and a third output 134. Wherein the second input 131 is configured to receive a second clock signal from the second clock 21; the third input end 132 and the fourth input end 133 are respectively connected to the first output end 122 and the second output end 123 of the phase-locked loop 12, and are respectively configured to receive a high-frequency clock signal and a low-frequency clock signal; the third output 134 is connected to the controller 14.

The serial-parallel converter 13 shift-converts the second clock signal using the low-frequency clock signal, samples the shift-converted second clock signal using the high-frequency clock signal, obtains a parallel clock signal, and outputs the parallel clock signal from the third output terminal 134.

Further, the controller 14 is configured to receive the parallel clock signal and adjust the phase of the output of the phase locked loop 12 according to the parallel clock signal. The process of adjustment can be described as: (1) the controller 14 determines the phase difference between the low frequency clock signal and the second clock signal according to the format of the received parallel clock signal; (2) the controller 14 determines that the determined phase difference is outside the difference range, and adjusts the high frequency clock signal and the low frequency clock signal through the control signal to configure the next output phase of the phase-locked loop 12; (3) the controller 14 determines that the determined phase difference is within the difference range, locks the high frequency clock signal and the low frequency clock signal by the control signal to maintain the output phase of the phase locked loop 12, and the controller 14 controls the serial-to-parallel converter 13 to stop receiving the second clock signal from the second clock 21.

In this embodiment, the high frequency clock signal and the low frequency clock signal are both frequency multiplication signals of the second clock signal, wherein the frequency multiplication value of the low frequency clock signal compared with the second clock signal is 1, and the frequency multiplication value of the high frequency clock signal compared with the second clock signal is 8, 16 or 32.

In the present embodiment, the frequency multiplication value of the high-frequency clock signal compared to the second clock signal is used to set the number of serial-to-parallel conversion bits of the serial-to-parallel converter 13 and to set the difference range preset in the controller 14. Specifically, the method comprises the following steps: (1) if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 8, the serial-parallel conversion bit number of the serial-parallel converter 13 is 8, and the difference value range preset in the controller 14 is 0-45 degrees; (2) if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 16, the serial-parallel conversion bit number of the serial-parallel converter 13 is 16, and the preset difference range in the controller 14 is 0-22.5 degrees; (3) if the frequency multiplication value of the high frequency clock signal compared with the second clock signal is 32, the serial-parallel conversion bit number of the serial-parallel converter 13 is 32, and the preset difference range in the controller is 0-11.25 °.

For a clear understanding of the structure and performance of the clock phase adjustment apparatus disclosed in the present embodiment, the principle of the clock phase adjustment apparatus will be described in detail herein according to a specific embodiment.

Assuming that the frequencies of the first clock signal and the second clock signal are 125MHz, the phase-locked loop 12 can adjust 8 phases, so that the frequency of the low-frequency clock signal generated by the phase-locked loop 12 is 125MHz, and the frequency of the high-frequency clock signal is 1GHz (125MHz multiplied by 8 phases); further, the number of serial-to-parallel conversion bits of the serial-to-parallel converter 13 is set to 8, and the difference value range preset in the controller 14 is set to 0 to 45 °, that is, the operation mode of the serial-to-parallel converter 13 is 1G/125M to 1, i.e., the serial-to-parallel conversion efficiency of 8: 1.

When the second clock signal reaches the second input terminal 131 of the serial-to-parallel converter 13 in a 125MHz and serial manner, the serial-to-parallel converter 13 performs shift conversion on the second clock signal by using the low frequency clock signal of 125MHz, and samples the shift-converted second clock signal by using the high frequency clock signal of 1GHz, thereby obtaining a parallel clock signal of 125MHz and 8-bit parallel output. Due to the phase difference existing between the low frequency clock signal and the second clock signal, the formats of the parallel clock signals are different due to the magnitude of the phase difference, and fig. 5 can be referred to specifically.

In this embodiment, since the pll 12 can adjust 8 phases, the output phase of the pll 12 is obtained by dividing 360 ° by 8 and multiplying by 0-7, i.e. 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 °. Under the condition of various output phases, the phase difference between the low-frequency clock signal and the second clock signal is respectively determined, and the possible value ranges of the phase difference are respectively 0-45 degrees, 45-90 degrees, 90-135 degrees, 135-180 degrees, 180-225 degrees, 225-270 degrees, 270-315 degrees and 315-360 degrees.

Case one, in the case where the phase difference belongs to 0-45 ° (excluding 45 °), referring to fig. 5a, the format of the parallel clock signal is b 00001111;

case two, in case the phase difference belongs to 45-90 ° (excluding 90 °), the format of the parallel clock signal is b10000111, see fig. 5b

Case three, in the case where the phase difference belongs to 90-135 ° (excluding 135 °), referring to fig. 5c, the format of the parallel clock signal is b 11000011;

case four, in the case that the phase difference belongs to 135- > 180 ° (excluding 180 °), referring to fig. 5d, the format of the parallel clock signal is b 11100001;

case five, in the case that the phase difference belongs to 180-;

case six, in the case where the phase difference belongs to 225-;

case seven, in the case that the phase difference belongs to 270-;

case eight, in the case where the phase difference belongs to 315-.

It can be seen that a value range of the phase difference corresponds to a format of the parallel clock signal, and then the controller 14 can determine the value range of the current phase difference according to the format of the parallel clock signal. In order to keep the phase consistency of the low-frequency clock signal and the second clock signal as much as possible, the effect of phase alignment is achieved. In this embodiment, it is preferable to select a case one as the determination condition of the controller 14, that is, if the controller 14 determines that the phase difference is out of the range of the difference value 0-45 °, the high frequency clock signal and the low frequency clock signal are adjusted by the control signal to configure the next output phase (e.g. 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, or 315 °) of the pll; the controller 14 determines that the phase difference is within the range of 0-45 deg., and locks the high frequency clock signal and the low frequency clock signal by the control signal to maintain the output phase (e.g., 0 deg.) of the phase locked loop 12, and the controller 14 controls the serial-to-parallel converter 13 to stop receiving the second clock signal from the second clock 21, that is, when the configuration operation of the phase locked loop 12 is completed, the low frequency clock signal may be used instead of the second clock signal.

Those skilled in the art can understand how, when the phase-locked loop 12 is set to 16 phases, i.e. when the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 16, the controller 14 determines whether the phase difference is within the range of 0-22.5 ° according to the format of the 16-bit parallel clock signal; in addition, it is also easy to understand how the phase-locked loop 12 is set to 32 phases, i.e. when the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 32, the controller 14 determines whether the phase difference is within the range of 0-11.25 ° according to the format of the 32-bit parallel clock signal. And will not be described in detail herein.

It should be noted that, in the present embodiment, the controller 14 only implements a simple logical judgment function, and the built-in judgment condition is set in advance by the user and can be implemented without creative labor, so that the logical judgment function and the control function of the controller 14 can be considered to belong to the prior art.

Example II,

Referring to fig. 3, the present application also discloses a digital system, which mainly includes a first digital device 2 and a second digital device 3, which are described below.

The first digital device 2 is provided with a second clock 21, which second clock 21 is used to generate a second clock signal.

The second digital device 3 comprises the clock phase adjusting device 1 disclosed in the embodiment, wherein the serial-to-parallel converter 13 is connected with the first digital device 2 and is used for receiving a second clock signal from the first digital device 2; the controller 14 is also connected to the first digital device 2, and is configured to control the first digital device 2 to stop sending the second clock signal to the serial-to-parallel converter when the phase difference between the low-frequency clock signal and the second clock signal reaches a preset difference range.

Further, the first digital device 2 is further provided with a control circuit 22, and the control circuit 22 is used for instructions of the controller 14 in the second digital device 3, responding to the instructions and implementing certain control logic to control whether the second clock 21 sends out the second clock signal.

Further, when the first digital device 2 or the second digital device 3 is started (e.g., power-on, power-off restart), the first digital device 2 sends the second clock signal to the second digital device 3.

For example, when the third digital device 3 is powered on, in order to ensure the system clock synchronization with the first digital device, the control circuit 22 controls the second clock 21 to send out the second clock signal, the controller 14 determines whether the phase difference corresponding to the parallel clock signal is in the range of 0-45 °, if not, the controller 12 controls the phase-locked loop 12 to generate the next output phase and continues the determination according to the new parallel clock signal, and if so, the controller 22 controls the phase-locked loop 12 to keep generating the output phase of 0 ° and stops sending out the second clock signal by the second clock 21. The second digital device 3 then obtains a low frequency clock signal which is clocked synchronously with the first digital device 2.

In another embodiment, the first digital device 2 and the second digital device 3 may be both FPGA components, and the functions of the second clock 21 and the control circuit 22 are implemented on the first FPGA through logic circuits, and the functions of the first clock 11, the phase-locked loop 12, the serial-to-parallel converter 13, and the controller 14 are implemented on the second FPGA through logic circuits.

Example III,

Referring to fig. 4, the present application further discloses a signal transmission system, which mainly includes the digital system in the second embodiment, and further includes a signal sending device 4 cooperating with the first digital device 2 and a signal receiving device 5 cooperating with the second digital device 3.

The signal transmitting apparatus is configured to transmit a signal to the signal receiving apparatus 5 after the first digital apparatus 2 responds to the control of the second digital apparatus 3 and stops transmitting the second clock signal to the serial-to-parallel converter 13.

The signal receiving apparatus 5 is configured to perform synchronization processing on the received signal by using the low frequency clock signal generated by the serial-to-parallel converter after receiving the signal transmitted by the signal transmitting apparatus.

As will be understood by those skilled in the art, after the phase adjustment operation of the clock signal is performed by using the first digital device 2 and the second digital device 3, the frequency and the phase of the low-frequency clock signal in the second digital device 3 can be kept consistent with those of the second clock signal in the first digital device 2, so as to achieve the effect of phase alignment, and the second clock signal is not transmitted any more. After receiving the signal sent by the signal sending device 4, the signal receiving device 5 performs synchronization processing under the action of the low-frequency clock signal, which is equivalent to processing in the clock domain of the second clock signal, so that the signal processing can be synchronized and stabilized, and powerful technical support is provided for the signal receiving device 5 to reliably receive the signal.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (9)

1. A clock phase adjustment apparatus, comprising:

a first clock for generating a first clock signal;

the phase-locked loop is connected with the first clock, and is used for receiving the first clock signal and generating a high-frequency clock signal and a low-frequency clock signal according to the first clock signal, wherein the high-frequency clock signal and the low-frequency clock signal are used for forming various output phases of the phase-locked loop;

the serial-parallel converter is connected with the phase-locked loop and is also used for being connected with an external second clock, and the serial-parallel converter is used for receiving the high-frequency clock signal, the low-frequency clock signal and a second clock signal from the second clock and is used for generating a parallel clock signal of the second clock signal according to the high-frequency clock signal and the low-frequency clock signal;

and the controller is connected with the serial-parallel converter and the phase-locked loop and used for receiving the parallel clock signal and adjusting the output phase of the phase-locked loop according to the parallel clock signal so as to enable the phase difference between the low-frequency clock signal and the second clock signal to reach a preset difference range.

2. The clock phase adjustment apparatus of claim 1, wherein the phase locked loop comprises a first input terminal, a first output terminal, a second output terminal, and a control terminal;

the first input end is connected with the first clock and used for receiving the first clock signal; the first output end and the second output end are respectively used for outputting a high-frequency clock signal and a low-frequency clock signal corresponding to the first clock signal; the control end is connected with the controller and used for receiving a control signal of the controller, and the control signal is used for adjusting the high-frequency clock signal and the low-frequency clock signal to configure any output phase of the phase-locked loop.

3. The clock phase adjustment apparatus of claim 2, wherein the serial-to-parallel converter comprises a second input, a third input, a fourth input, and a third output;

the second input terminal is used for receiving a second clock signal from the second clock; the third input end and the fourth input end are respectively connected with the first output end and the second output end of the phase-locked loop and are respectively used for receiving the high-frequency clock signal and the low-frequency clock signal; the third output end is connected with the controller;

and the serial-parallel converter performs shift conversion on the second clock signal by using the low-frequency clock signal, samples the shift-converted second clock signal by using the high-frequency clock signal, obtains the parallel clock signal and outputs the parallel clock signal from the third output end.

4. The clock phase adjustment apparatus of claim 3, wherein the controller is configured to receive the parallel clock signals and adjust the output phase of the phase locked loop based on the parallel clock signals, comprising:

the controller determines the phase difference between the low-frequency clock signal and the second clock signal according to the format of the received parallel clock signal;

the controller judges that the phase difference is out of the difference range, and then adjusts the high-frequency clock signal and the low-frequency clock signal through the control signal to configure the next output phase of the phase-locked loop;

if the controller judges that the phase difference is within the difference range, the high-frequency clock signal and the low-frequency clock signal are locked through the control signal so as to keep the output phase of the phase-locked loop; and the controller controls the serial-to-parallel converter to stop receiving the second clock signal from the second clock.

5. The clock phase adjustment apparatus of any one of claims 1-4, wherein the high frequency clock signal and the low frequency clock signal are both multiples of the second clock signal, the low frequency clock signal has a multiple of 1 compared to the second clock signal, and the high frequency clock signal has a multiple of 8, 16, or 32 compared to the second clock signal.

6. The clock phase adjusting apparatus of claim 5, wherein the high frequency clock signal is used to set a number of serial-to-parallel conversion bits of the serial-to-parallel converter and to set a difference range preset in the controller, compared to a multiplied value of the second clock signal;

if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 8, the serial-parallel conversion bit number of the serial-parallel converter is 8, and the difference value range preset in the controller is 0-45 degrees;

if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 16, the serial-parallel conversion bit number of the serial-parallel converter is 16, and the preset difference range in the controller is 0-22.5 degrees;

and if the frequency multiplication value of the high-frequency clock signal compared with the second clock signal is 32, the serial-parallel conversion bit number of the serial-parallel converter is 32, and the difference value range preset in the controller is 0-11.25 degrees.

7. A digital system, comprising:

the first digital equipment is provided with a second clock, and the second clock is used for generating a second clock signal;

a second digital device comprising the clock phase adjustment apparatus of any one of claims 1-6, wherein the serial-to-parallel converter is coupled to the first digital device for receiving a second clock signal from the first digital device; the controller is also connected with the first digital device and is used for controlling the first digital device to stop sending the second clock signal to the serial-parallel converter when the phase difference between the low-frequency clock signal and the second clock signal reaches a preset difference range.

8. The digital system of claim 7, wherein the first digital device sends the second clock signal to the second digital device when the first digital device or the second digital device is powered on.

9. A signal transmission system comprising the digital system of any of claims 7-8, further comprising a signal transmitting device cooperating with the first digital device and a signal receiving device cooperating with the second digital device;

the signal transmitting device is used for transmitting a signal to the signal receiving device after the first digital device responds to the control of the second digital device and stops transmitting the second clock signal to the serial-parallel converter;

and the signal receiving equipment is used for carrying out synchronous processing on the received signals by using the low-frequency clock signals generated by the serial-parallel converter after the signals sent by the signal sending equipment are received.

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