CN210073829U - Structure for packaging FOSiP of ultrahigh-density chip - Google Patents
Structure for packaging FOSiP of ultrahigh-density chip Download PDFInfo
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- CN210073829U CN210073829U CN201921063961.1U CN201921063961U CN210073829U CN 210073829 U CN210073829 U CN 210073829U CN 201921063961 U CN201921063961 U CN 201921063961U CN 210073829 U CN210073829 U CN 210073829U
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- fosip
- copper interconnection
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- 238000004806 packaging method and process Methods 0.000 title claims description 23
- 239000002184 metal Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052802 copper Inorganic materials 0.000 claims abstract description 34
- 239000010949 copper Substances 0.000 claims abstract description 34
- 238000005538 encapsulation Methods 0.000 claims abstract description 11
- 239000005416 organic matter Substances 0.000 claims abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 3
- 230000005611 electricity Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 138
- 238000000034 method Methods 0.000 description 28
- 238000012858 packaging process Methods 0.000 description 25
- 238000010586 diagram Methods 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model relates to a structure for ultra-high density chip FOSiP encapsulation, from last to setting gradually the plastic envelope layer down, accurate copper interconnection layer and rewiring layer, the plastic envelope has a plurality of chips or the device that have the metal contact in the plastic envelope layer, accurate copper interconnection layer has the interconnect structure who comprises the double flute, the cross-sectional size that is close to the plastic envelope layer along plastic envelope layer surface vertical direction is less than the cross-sectional size of keeping away from the plastic envelope layer, rewiring layer forms the metal connection structure that can interconnect with accurate copper interconnection layer electricity in its dielectric layer place one deck, metal connection structure passes the dielectric layer and extends organic matter dielectric layer part as the contact, set up the tin ball on the contact. Adopt the design scheme of the utility model, can conveniently carry out the integrated encapsulation of fan-out type to the accurate bare chip of high-end that has hyperfine pin structure, also further dwindled the encapsulation volume.
Description
Technical Field
The utility model relates to a semiconductor package technical field, concretely relates to a structure for encapsulation of ultra high density chip FOSiP.
Background
With the advent of the 5G communication and Artificial Intelligence (AI) era, the amount of data to be transmitted and processed interactively at high speed is enormous for chips applied in such related fields, which usually have huge number of pad pins (hundreds or even thousands), ultra-fine pin sizes and pitches (several microns or even smaller). On the other hand, the demands on the mobile internet and the internet of things are more and more strong, and the miniaturization and the multi-functionalization of electronic terminal products become a great trend of industrial development. How to integrate and package a plurality of different high-density chips together to form a system or subsystem with powerful function and smaller volume and power consumption becomes a great challenge in the field of advanced packaging of semiconductor chips.
At present, for multi-chip integrated packaging of such high-density chips, the industry generally adopts Through Silicon Vias (TSVs), silicon interposer (Si interposer) and other manners, so as to lead out and effectively interconnect ultra-fine pins of the chips to form a functional module or system, but the technology has higher cost, thereby greatly limiting the application range thereof. The fanout packaging technology provides a good platform for realizing multi-chip integrated packaging by adopting a mode of re-wiring a reconstituted wafer (recon wafer) and an RDL (radio data link layer), but the precision of the RDL re-wiring manufacturing method in the existing fanout packaging technology is limited, so that the extraction and interconnection of such fine pins in a high-density chip cannot be finished, or the area of a packaging body is large and the thickness is high due to the limited wiring precision, and the problems of multiple processes, low reliability and the like exist.
SUMMERY OF THE UTILITY MODEL
The purpose of the invention is as follows: the utility model aims to solve current fan-out type encapsulation and than higher in the integrated encapsulation to super high density many pins chip technical cost, the range of application is narrow, and it is limited to adopt the precision of prior art preparation rewiring layer, can't accomplish so meticulous pin draw forth and interconnect in the high density chip, thereby perhaps because the wiring precision is limited makes the great thickness of the area of packaging body higher, has the problem that the process is numerous moreover, the reliability is not high.
The technical scheme is as follows: in order to solve the above problem, the utility model adopts the following technical scheme:
the utility model provides a structure for ultra-high density chip FOSiP encapsulation, from last to setting gradually the plastic envelope layer down, accurate copper interconnection layer and at least one deck rewiring layer, accurate copper interconnection layer has the metal interconnection structure who constitutes by the stack of double flute, the cross-sectional size that is close to the plastic envelope layer along plastic envelope layer surface vertical direction is less than the cross-sectional size of keeping away from the plastic envelope layer, rewiring layer forms the metal connection structure that can with accurate copper interconnection layer electricity interconnection in its dielectric layer place one deck, metal connection structure passes the dielectric layer and extends organic matter dielectric layer part as the contact, set up the tin ball on the contact.
Further, the direction of the double-groove stacking is the stacking direction along the plastic package layer, the precision copper interconnection layer and the rewiring layer.
Furthermore, the metal connecting structure is in an I shape, and the arrangement direction is the direction along the superposition of the plastic packaging layer, the precision copper interconnection layer and the rewiring layer.
Furthermore, a plurality of bare chips with metal contacts or passive elements are plastically packaged in the plastic packaging layer.
Further, at least one dummy die among the bare chip or passive component.
A preparation method of a structure for packaging an ultra-high density chip FOSiP comprises the following steps:
1) adhering a temporary bonding glue layer on the surface of a temporary slide;
2) a bare chip or a passive element is pasted on the temporary bonding glue layer obtained in the step 1);
3) manufacturing a plastic package layer according to the orientation of the device surface with the pad pin on the bare chip or the passive element;
4) manufacturing a precision copper interconnection layer on the plastic package body;
5) manufacturing a rewiring layer on the precise copper interconnection layer;
6) placing a solder ball on the metal gasket led out from the pad of the rewiring layer to realize the electrical connection between the gasket and the solder ball;
7) separating the temporary slide from the packaging body on the temporary slide by adopting a laser or thermal stripping method;
8) and cutting to obtain the individual packaging bodies.
Further, in the step 3), if the device surface of the bare chip or the passive component is upward, a metal pad with a bump needs to be manufactured in advance above a pad pin of the bare chip or the passive component; then, carrying out plastic package on the mounted bare chip or passive element to form a plastic package layer, and thinning the plastic package layer to expose pad salient points on the surface of the bare chip or passive element; if the device surface of the bare chip or the passive element is downward, the bare chip or the passive element is subjected to plastic package after being pasted, then the temporary slide and the temporary bonding adhesive layer below are removed, and the plastic package layer is turned over, so that the bonding pad on the surface of the bare chip or the passive element can be exposed.
Further, in the step 4), the manufacturing of the precision copper interconnection layer specifically includes the following steps:
4, a) coating a dielectric layer on the plastic packaging layer by using Chemical Vapor Deposition (CVD);
4.b) coating a layer of photoresist on the dielectric layer;
4, c) carrying out photoetching and developing processes on the photoresist to form a groove, wherein the position corresponding to the groove is the position of a bump bonding pad which needs to be led out on the bare chip or the passive element or the position of the bump bonding pad which needs to be electrically interconnected with pins of other chips;
4, d) etching the dielectric layer at the position of the groove on the photoresist by using an Etch (Etch) method to form a first groove on the dielectric layer;
e) removing the photoresist by an etching method;
4, f) repeating the same process steps from 5.b to 5.e, further manufacturing a second groove with the bottom surface smaller than that of the first groove in the area of the first groove on the dielectric layer, wherein the second groove penetrates through the current dielectric layer, so that the superposed first groove and second groove jointly penetrate through the whole dielectric layer, and the position of the second groove corresponds to the position of the pin of the bare chip or passive element below the second groove, thereby exposing the pin of the bare chip or passive element below the second groove and forming a fine connecting through hole above the pin of the bare chip or passive element;
4, g) depositing a thin metal seed layer in the communicating through hole, and electroplating on the metal seed layer to form a copper interconnection structure line;
and 4, h) grinding the surface, and removing the redundant metal seed layer to enable the top of the copper interconnection structure line to be flush with the end face of the dielectric layer and simultaneously perform the function of flattening the surface.
Further, in the step 5), a rewiring layer is continuously manufactured on the precision copper interconnection layer, and the method specifically comprises the following steps;
5, a) coating a dielectric layer on the precision copper interconnection layer by using a spin coating method;
5, b) carrying out exposure and development photoetching process at the corresponding position of the dielectric layer to expose the pin bonding pads needing to be led out on the surface of the copper interconnection structure below the dielectric layer;
5, c) continuously depositing a metal seed layer on the dielectric layer, wherein the metal seed layer deposition is required to keep the mutual electrical interconnection of the bare chip or the passive element and ensure that the pin bonding pad of the bare chip or the passive element can be matched with the dielectric layer to form a groove;
5, d) coating a layer of photoresist, exposing and developing, slotting on the photoresist, and exposing the pin bonding pad to be led out and the seed layer of the wiring area;
5, e) continuing to perform a metal electroplating process, and forming an RDL rewiring layer in the photoresist slotting region;
and 5.f) removing the photoresist and the metal seed layer at the bottom by adopting a wet etching method.
Further, in the step 5.f), if a plurality of metal connection layers are required, the process steps 5.a to 5.e may be repeated, the metal pad is exposed at the uppermost part of the RDL rewiring layer structure, then the required metal rewiring layer is made by using photolithography and electroplating methods, the pad and the metal bump are led out as the metal pad, and the photoresist and the excess metal seed layer are removed by using etching.
Has the advantages that: the utility model discloses compare with the integrated packaging technology of fan-out type of current conventionality or through more complicated packaging technology structures such as keysets:
1) the fan-out integrated packaging process structure for the high-density chip with the ultra-fine pin structure is realized, the thickness of a rewiring layer manufactured by adopting the existing packaging structure and process is more than 10 mu m, generally about 15 mu m, and the thickness of the rewiring layer can be controlled to be less than 10 mu m by adopting the design of the application;
2) for the integrated packaging of the ultra-fine structure pin chip, high-cost complex structures such as Through Silicon Vias (TSV), silicon connection plates (interposer) and the like are not needed;
3) the bare chip and the passive device can be simultaneously integrated and packaged, so that the integration level is greatly improved, and the method is particularly suitable for high-density application scenes such as 5G, AI and the like;
4) the packaging method greatly simplifies the process and reduces the volume of the high-density chip integrated package.
Drawings
Fig. 1 is a schematic view of the temporary slide in step 1) of the packaging process of the present invention;
FIG. 2 is a state diagram after the packaging process step 1) of the present invention is finished;
FIG. 3 is a state diagram after the packaging process step 2) of the present invention is finished;
fig. 4 is a schematic diagram of the present invention, in the packaging process step 3), the device surface of the bare chip or the passive component is upward, and a protruding metal pad needs to be pre-fabricated above the pad pin of the bare chip or the passive component;
fig. 5 is a schematic diagram of the packaging process step 3) of the present invention, in which the device surface of the bare chip or the passive component is upward, and the mounted bare chip or passive component is subjected to plastic package to form a plastic package layer;
fig. 6 is a schematic diagram of the packaging process step 3) of the present invention, in which the device surface of the bare chip or the passive component faces upward, and the plastic package layer is thinned to expose the pad bumps on the surface of the bare chip or the passive component;
fig. 7 is a state diagram of the bare chip or passive component with the device surface facing down and attached on the temporary bonding glue layer in step 3) of the packaging process of the present invention;
fig. 8 is a schematic view of the package process of the present invention, in step 3), the device surface of the bare chip or the passive component is downward, and the bare chip or the passive component is plastic-sealed;
fig. 9 is a schematic view of the packaging process of the present invention, in step 3), the device surface of the bare chip or the passive component is facing down, the temporary carrier and the temporary bonding glue layer are removed, and the plastic package layer is turned over;
fig. 10 is a state diagram after the end of step 4.a) of the packaging process of the present invention;
FIG. 11 is a state diagram after the end of step 4.b) of the packaging process of the present invention;
FIG. 12 is a state diagram after the end of step 4.c) of the packaging process of the present invention;
FIG. 13 is a state diagram after the end of step 4.d) of the packaging process of the present invention;
FIG. 14 is a state diagram after the end of step 4.e) of the packaging process of the present invention;
fig. 15 is a state diagram after the end of step 4.f) of the packaging process of the present invention;
fig. 16 is a state diagram after the end of step 4.g) of the packaging process of the present invention;
fig. 17 is a state diagram after the end of step 4.h) of the packaging process of the present invention;
fig. 18 is a state diagram after the end of step 5.a) of the packaging process of the present invention;
FIG. 19 is a state diagram after the end of step 5.b) of the packaging process of the present invention;
FIG. 20 is a state diagram after the end of step 5.c) of the packaging process of the present invention;
FIG. 21 is a state diagram after the end of step 5.d) of the packaging process of the present invention;
FIG. 22 is a state diagram after the end of step 5.e) of the packaging process of the present invention;
fig. 23 is a state diagram after the end of step 5.f) of the packaging process of the present invention;
fig. 24 is a state diagram after the end of step 6) of the packaging process of the present invention;
fig. 25 is a state diagram after the end of step 7) of the packaging process of the present invention;
in the figure, 1-temporary slide, 2-temporary bonding glue layer, 3-bare chip with metal contact or passive element, 4-plastic package layer, 5-precision copper interconnection layer, 6-photoresist, 7-metal seed layer, 8-rewiring layer, 801-organic dielectric layer, 802-metal connection structure, 9-tin ball and 12-dielectric layer.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples.
Example 1
The utility model provides a structure for encapsulation of ultra-high density chip FOSiP, from last to setting gradually plastic-sealed layer 4 down, accurate copper interconnect layer 5 and at least one deck rewiring layer 8, accurate copper interconnect layer 5 has the metal interconnect structure who constitutes by the stack of double flute, the cross-sectional size that is close to plastic-sealed layer 4 along the vertical direction in plastic-sealed layer 4 surface is less than the cross-sectional size of keeping away from plastic-sealed layer 4, rewiring layer 8 forms the metal connection structure 802 that can electrically interconnect with accurate copper interconnect layer 5 in its dielectric layer 12 place one deck, metal connection structure 802 passes dielectric layer 12 and extends organic matter dielectric layer 801 part as the contact, set up tin ball 9 on the contact.
The stacking direction of the double grooves is the stacking direction along the plastic package layer 4, the precision copper interconnection layer 5 and the rewiring layer 6.
The metal connection structure 802 is in an i shape, and the arrangement direction is the direction along the stacking direction of the plastic package layer 4, the precision copper interconnection layer 5 and the rewiring layer 6.
The plastic packaging layer 4 is internally and plastically packaged with a plurality of bare chips or passive elements 3 with metal contacts.
At least one dummy die among the bare chips or passive elements 3.
Example 2
A preparation method of a structure for packaging an ultra-high density chip FOSiP comprises the following steps:
1) as shown in fig. 2, firstly, adhering a temporary bonding glue layer 2 on the surface of a temporary slide 1;
2) as shown in fig. 3, a bare chip or a passive element 3 is mounted on the temporary bonding glue layer 2 obtained in step 1);
3) manufacturing a plastic package layer 4 according to the orientation of the device surface with pad pins on the bare chip or the passive element;
as shown in fig. 4, if the device surface of the bare chip or passive component 3 is upward, a metal pad with a bump needs to be pre-fabricated above the pad pin of the bare chip or passive component 3; as shown in fig. 5, the mounted bare chip or passive component 3 is then subjected to plastic packaging to form a plastic packaging layer 4, as shown in fig. 6, and the plastic packaging layer 4 is thinned to expose pad bumps on the surface of the bare chip or passive component 3; as shown in fig. 7 and 8, if the device surface of the bare chip or passive component 3 is facing down, the bare chip or passive component 3 is subjected to plastic encapsulation after mounting, as shown in fig. 9, and then the temporary carrier sheet 1 and the temporary bonding adhesive layer 2 below are removed, and the plastic encapsulation layer 4 is turned over, so that the bonding pads on the surface of the bare chip or passive component 3 are exposed.
4) Manufacturing a precision copper interconnection layer 5 by the plastic package body 4;
the manufacturing method of the precise copper interconnection layer specifically comprises the following steps:
4.a) as in FIG. 10, a dielectric layer 12 is first coated on the molding layer 4 by CVD;
4.b) coating a layer of photoresist 6 on the dielectric layer 12 as in FIG. 11;
4, c) as shown in fig. 12, carrying out photoetching and developing processes on the photoresist 6 to form a groove, wherein the position corresponding to the groove is the position of a bump pad which needs to be led out on the bare chip or the passive element or the position of the bump pad which needs to be electrically interconnected with pins of other chips;
4.d) as shown in fig. 13, etching the dielectric layer 12 at the position of the groove on the photoresist 6 by using an Etch method to form a first groove on the dielectric layer 12;
e) removing the photoresist 6 by etching as shown in FIG. 14;
4, f) repeating the same process steps as 5.b to 5.e as shown in fig. 15, further manufacturing a second groove with a bottom surface smaller than that of the first groove in the first groove region on the dielectric layer 12, wherein the second groove penetrates through the current dielectric layer 12, so that the overlapped first groove and second groove jointly penetrate through the whole dielectric layer 12, and the position of the second groove corresponds to the position of the pin of the bare chip or passive element below the second groove, thereby exposing the pin of the bare chip or passive element 3 below the second groove, and forming a fine connecting through hole above the pin of the bare chip or passive element 3;
4.g) depositing a thin metal seed layer 7 in the through via holes and electroplating on the metal seed layer 7 to form copper interconnection structure lines as shown in FIG. 16;
4, h) grinding the surface to remove the excess metal seed layer 7 so that the top of the copper interconnect structure line is flush with the end face of the dielectric layer and the surface is also planarized.
5) Manufacturing a rewiring layer 6 on the precise copper interconnection layer 5;
continuously manufacturing a rewiring layer on the precise copper interconnection layer, wherein the method specifically comprises the following steps;
5.a) coating a dielectric layer 12 on the precision copper interconnect layer 5 by spin coating as shown in FIG. 17;
5, b) as shown in FIG. 18, performing a photolithography process of exposure and development at a corresponding position of the dielectric layer 12 to expose the pin pads to be led out on the surface of the copper interconnection structure below the dielectric layer 12;
5, c) as shown in FIG. 19, a metal seed layer 7 is continuously deposited on the dielectric layer 12, and the metal seed layer 7 is deposited to maintain the electrical interconnection between the bare chip or the passive element and to enable the pin pad of the bare chip or the passive element to cooperate with the dielectric layer to form a groove;
5, d) coating a layer of photoresist 6 as shown in FIG. 20, exposing and developing, slotting on the photoresist, and exposing the pin bonding pad to be led out and the seed layer of the wiring area;
5.e) continuing the metal plating process as shown in FIG. 21, forming an RDL rewiring layer 6 in the photoresist grooved area;
and 5.f) removing the photoresist 6 and the metal seed layer 7 at the bottom by adopting a wet etching method as shown in FIG. 22.
If a plurality of metal connecting layers are needed, the process steps from 5.a to 5.e can be repeated, the metal gasket is exposed at the uppermost part of the RDL rewiring layer structure, then the needed metal rewiring layer is made by using a photoetching and electroplating method, the bonding pad and the metal bump are led out to be the metal gasket, and the photoresist and the redundant metal seed layer are removed by using etching.
6) As shown in fig. 23, a solder ball 9 is placed at a metal pad led out from a pad of the rewiring layer 6, and electrical connection between the pad and the solder ball 9 is realized;
7) as shown in fig. 24, the temporary carrier 1 is separated from the package body thereon by laser or thermal peeling;
8) as shown in fig. 25, dicing is performed to obtain individual packages.
Claims (5)
1. A structure for ultra-high density chip FOSiP encapsulation which characterized in that: the precise copper interconnection layer is provided with a metal interconnection structure formed by overlapping double grooves, the size of a cross section close to the plastic package layer in the surface vertical direction of the plastic package layer is smaller than that of a cross section far away from the plastic package layer, the rewiring layer forms a metal connection structure capable of being electrically interconnected with the precise copper interconnection layer on the dielectric layer of the rewiring layer, the metal connection structure penetrates through the dielectric layer and extends out of an organic matter dielectric layer part to serve as a contact, and a solder ball is arranged on the contact.
2. The structure for the ultra-high density chip FOSiP package of claim 1, wherein: the direction of the double-groove stacking is along the stacking direction of the plastic packaging layer, the precision copper interconnection layer and the rewiring layer.
3. The structure for the ultra-high density chip FOSiP package of claim 1, wherein: the metal connecting structure is I-shaped, and the arrangement direction is the direction along the superposition of the plastic packaging layer, the precision copper interconnection layer and the rewiring layer.
4. The structure for the ultra-high density chip FOSiP package of claim 1, wherein: the plastic package layer is internally provided with a plurality of bare chips or passive elements with metal contacts in a plastic package way.
5. The structure for the ultra-high density chip FOSiP package of claim 4, wherein: at least one dummy die among the bare chips or passive components.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110323197A (en) * | 2019-07-09 | 2019-10-11 | 王新 | Structure and preparation method thereof for ultra high density chip FOSiP encapsulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110323197A (en) * | 2019-07-09 | 2019-10-11 | 王新 | Structure and preparation method thereof for ultra high density chip FOSiP encapsulation |
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