CN209881957U - Image display device and stereoscopic image processing circuit - Google Patents

Abstract

The utility model provides a stereoscopic image processing circuit. The stereoscopic image processing circuit is adapted to process a stereoscopic image signal, wherein the stereoscopic image signal includes a picture synchronization signal and a corresponding view angle switching signal. The stereoscopic image processing circuit includes a synchronization signal correction circuit coupled to the image processing circuit. The synchronizing circuit of the synchronizing signal correcting circuit receives the picture synchronizing signal processed by the image processing circuit and simultaneously receives the view angle switching signal. The synchronization circuit compares the processed picture synchronization signal with the view angle switching signal to output a view angle switching signal synchronized with the processed picture synchronization signal. The utility model also provides an image display equipment who contains above-mentioned stereoscopic image processing circuit. The utility model discloses can avoid picture synchronizing signal and visual angle switching signal asynchronous, can adjust the frequency signal between the stereoscopic image signal automatically and accurately.

Description

Image display device and stereoscopic image processing circuit

【Technical field】

The utility model relates to a stereoscopic image processing technology, in particular to an image display device and a stereoscopic image processing circuit.

【Background technique】

With the continuous improvement of display technology, in order to enhance the user's visual experience, the images viewed by the user begin to change from flat (2D) images to stereoscopic (3D) images. Compared with the traditional planar image signal, the stereoscopic image signal includes not only the frame synchronization signal corresponding to the frame number (Frame), but also the viewing angle switching signal corresponding to the left and right eyes. By allowing the left eye and the right eye to receive different viewing angles, the user will have a stereoscopic view of the picture, and the viewing angle switching signal indicates whether the picture at the time point is displayed to the left eye or the right eye.

However, when the image display device plays the stereoscopic image signal, a frame delay problem may occur, so that the frame synchronization signal and the viewing angle switching signal are not synchronized, and the stereoscopic display effect is destroyed. This is caused by the system's image path design or different image processing requirements. For example, a 3D projector may perform image processing operations such as image scale change, dynamic compensation, or image correction on a stereoscopic image signal before projecting an image. A frame delay problem may occur in the processed stereoscopic image signal. Therefore, how to avoid the delay between the picture synchronization signal and the viewing angle switching signal becomes an important issue.

【Content of invention】

The utility model provides an image display device and a three-dimensional image processing circuit, which can automatically keep the synchronization between the picture synchronization signal and the viewing angle switching signal, and provide accurate synchronization effect.

An embodiment of the present invention provides a stereoscopic image processing circuit suitable for processing stereoscopic image signals, wherein the stereoscopic image signal includes a frame synchronization signal and a viewing angle switching signal corresponding to the frame synchronization signal. The stereoscopic image processing circuit includes a synchronization signal correction circuit coupled to the image processing circuit, wherein the image processing circuit receives the frame synchronization signal and outputs a processed frame synchronization signal, and the synchronization signal correction circuit includes a synchronization circuit. The synchronization circuit is coupled to the output end of the image processing circuit to receive the processed frame synchronization signal and simultaneously receive the viewing angle switching signal. The synchronizing circuit is used for comparing the processed frame synchronizing signal with the viewing angle switching signal to output a corrected viewing angle switching signal synchronized with the processed frame synchronizing signal.

An embodiment of the utility model provides an image display device for playing stereoscopic images. The image display device includes a stereoscopic image decoding circuit, an image processing circuit, a synchronous signal correction circuit and an image playing circuit. The stereoscopic image decoding circuit is used for decoding the stereoscopic image signal, wherein the stereoscopic image signal includes a frame synchronization signal and a viewing angle switching signal corresponding to the frame synchronization signal. The image processing circuit is used for receiving the frame synchronization signal from the stereo image decoding circuit and outputting the processed frame synchronization signal. The synchronization circuit of the synchronization signal correction circuit is coupled to the output end of the image processing circuit to receive the processed frame synchronization signal. The synchronous circuit also receives the viewing angle switching signal at the same time. The synchronizing circuit is used for comparing the processed frame synchronizing signal with the viewing angle switching signal to output a corrected viewing angle switching signal synchronized with the processed frame synchronizing signal. The image playing circuit is used for receiving the processed picture synchronous signal from the image processing circuit and the corrected viewing angle switching signal from the synchronous signal correction circuit, and plays the stereoscopic image signal according to the processed picture synchronizing signal and the corrected viewing angle switching signal.

Based on the above, the image display device and the stereoscopic image processing circuit of the present utility model compare the processed picture synchronization signal with the viewing angle switching signal to output the corrected viewing angle switching signal synchronized with the processed picture synchronizing signal, so there is no need for the user to Manual adjustment can achieve the effect of automatic synchronization between signals, so that users can have good image quality and convenience when watching stereoscopic images. In addition, the present invention synchronizes the corrected viewing angle switching signal with the processed frame synchronization signal, thereby reducing the delay time between the processed frame synchronization signal and the initial frame synchronization signal. The stereoscopic image processing circuit of the present invention also has the advantages of simple structure and easy integration with the original stereoscopic image processing circuit, is applicable to various stereoscopic image sources, and can be applied to various image display devices.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with accompanying drawings.

【Description of drawings】

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a synchronization signal correction circuit according to the embodiment of FIG. 1 of the present invention.

FIG. 3 is a waveform diagram of a frame synchronization signal and a viewing angle switching signal before and after image processing according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of the frame synchronization signal before and after image processing and the viewing angle switching signal before and after correction according to an embodiment of the present invention.

FIG. 5 is a flow chart of a method for correcting a synchronization signal of a stereoscopic image signal according to an embodiment of the present invention.

【Symbol Description】

10: Image display device

20: Image output device

100: Stereo image processing circuit

102: Stereo image decoding circuit

104: Image processing circuit

106: Synchronous signal correction circuit

108: Image input interface

110: Synchronous circuit

120: multiplexer

130: delay comparison circuit

140: Phase judgment circuit

200: image playback circuit

300: synchronization signal correction method

DATA: image data

P1, P2: image path

PXS, PXS1: Pixel signal

SYN, SYN1: picture synchronization signal

STE, STE1: viewing angle switching signal

T: frame period

t: frame delay time

L, R: period

td: delay time

S510-S520: Steps of the synchronous signal correction method for the stereoscopic image signal

【Detailed ways】

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention. The image display device 10 receives image data DATA from an external image output device 20 to display a stereoscopic image. The image display device 10 may be a 3D projector, a 3D TV or other stereoscopic image players, and the image output device 20 may be an electronic device such as a smart phone or a notebook computer or a storage medium such as a CD or a hard disk. The image display device 10 at least includes a stereoscopic image processing circuit 100 and an image playing circuit 200 , wherein the stereoscopic image processing circuit 100 includes a stereoscopic image decoding circuit 102 , an image processing circuit 104 and a synchronization signal correction circuit 106 .

The stereoscopic image decoding circuit 102 is used for decoding image data DATA. It should be noted that, in this embodiment, the image format of the image data DATA is a stereoscopic image signal, including a pixel signal PXS, a frame synchronization signal SYN, and an angle switching signal STE corresponding to the frame synchronization signal SYN. After decoding the image data DATA, the stereoscopic image decoding circuit 102 can obtain the pixel signal PXS, the frame synchronization signal SYN and the viewing angle switch signal STE, and transmit the viewing angle switching signal STE to the synchronization signal correction circuit 106, as shown in the image path P1 of FIG. 1 . In another embodiment, the image format of the image data DATA is a planar image signal, and the image data DATA may form a stereoscopic image signal with another viewing angle switching signal STE. The stereoscopic image decoding circuit 102 decodes the image data DATA and outputs the pixel signal PXS and the frame synchronization signal SYN. The synchronization signal correction circuit 106 receives the viewing angle switching signal STE from the image output device 20 through the image input interface 108, as shown in the image path P2 of FIG. 1 .

The image processing circuit 104 is, for example, an image processing chip, which can provide image scale conversion (Scaling), motion estimation and motion compensation (Motion Estimation & Motion Compensation, MEMC) or keystone correction (Keystone correction), image fusion (Blending) or image deformation adjustment (Warping) Waiting for image processing functions to adjust the display screen of the stereoscopic image, the utility model does not limit its function type. The image processing circuit 104 receives the pixel signal PXS and the frame synchronization signal SYN from the stereoscopic image decoding circuit 102 and outputs the processed pixel signal PXS1 and the processed frame synchronization signal SYN1 .

The synchronization signal correction circuit 106 includes a synchronization circuit 110 . The synchronization circuit 110 is coupled to the output terminal of the image processing circuit 104 to receive the processed frame synchronization signal SYN1 and simultaneously receive the viewing angle switching signal STE from the image path P1 or the image path P2. The synchronization circuit 110 compares the processed frame synchronization signal SYN1 with the viewing angle switching signal STE to output a corrected viewing angle switching signal STE1 synchronized with the processed frame synchronizing signal SYN1 . The image playback circuit 200 receives the pixel signal PXS1 and the picture synchronization signal SYN1 from the image processing circuit 104 and receives the corrected viewing angle switching signal STE1 from the synchronization signal correction circuit 106, and switches the viewing angle according to the pixel signal PXS1, the picture synchronization signal SYN1 and the corrected viewing angle. Signal STE1 plays stereoscopic images.

FIG. 2 is a block diagram of a synchronization signal correction circuit according to the embodiment of FIG. 1 of the present invention. The synchronization signal correction circuit 106 in FIG. 2 includes a multiplexer 120 , a delay comparison circuit 130 and a phase determination circuit 140 in addition to the synchronization circuit 110 . The synchronous signal correction circuit 106 can utilize Field Programmable Gate Array (Field Programmable GateArray, FPGA) to implement the above architecture. Please refer to FIG. 2 with FIG. 1 , the synchronization signal correction circuit 106 is coupled between the stereoscopic image decoding circuit 102 and the image input interface 108 .

Specifically, the image input interface 108 is used for receiving stereoscopic image signals from the image output device 20 . The image input interface 108 is, for example, a video graphics array (Video Graphics Array, VGA) interface, a digital video interface (DigitalVisual Interface, DVI), a high-resolution multimedia interface (High-Definition MultimediaInterface, HDMI), a display port (DisplayPort, DP) interface Or other wired or wireless transmission interfaces that can receive image data.

The multiplexer 120 is coupled to the synchronization circuit 110 , the stereo image decoding circuit 102 and the image input interface 108 . The multiplexer 120 can selectively receive the viewing angle switch signal STE from the image input interface 108 or from the stereoscopic image decoding circuit 102 and provide it to the synchronization circuit 110 . In other words, when the image format of the image data DATA is a stereoscopic image signal, the viewing angle switching signal STE will be transmitted from the stereoscopic image decoding circuit 102 to the multiplexer 120 along the image path P1; The processor 120 receives the viewing angle switching signal STE from the image output device 20 through the image input interface 108, such as the image path P2. The multiplexer 120 selects the source of the viewing angle switching signal STE according to the image format of the image data DATA.

Thus, the image data DATA received by the image display device 10 of this embodiment is not limited to the stereoscopic image format, and the stereoscopic image can be displayed by additionally providing the viewing angle switching signal STE together with the image data DATA in the planar image format.

In particular, in another embodiment, the synchronization signal correction circuit 106 may not include the multiplexer 120 , and is not limited to be disposed between the image input interface 108 and the stereoscopic image decoding circuit 102 . The synchronous signal correction circuit 106 can be arranged in other positions, but still receives the processed picture synchronous signal SYN1 from the image processing circuit 104 and receives the viewing angle switching signal STE from the stereoscopic image decoding circuit 102 or the image input interface 108 to correct the viewing angle switching signal STE , so as to output the corrected viewing angle switching signal STE1 synchronized with the frame synchronization signal SYN1. In addition, the viewing angle switching signal STE received by the synchronization circuit 110 may be the viewing angle switching signal corresponding to the picture synchronization signal SYN1 processed by the image processing circuit 104 or the viewing angle switching signal corresponding to the picture synchronization signal SYN not processed by the image processing circuit 104. Angle switching signal STE. The decoded image data DATA is input to the image processing circuit 104 for some image processing steps, and then the output pixel signal PXS1 and the frame synchronization signal SYN1 will be delayed, but the image processing circuit 104 will not substantially cause the viewing angle switching signal STE to be delayed. Therefore, in another embodiment, the synchronization signal correction circuit 106 may also receive the viewing angle switching signal STE from the output terminal of the image processing circuit 104 .

Fig. 3 is a waveform diagram of a picture synchronization signal and a viewing angle switching signal before and after image processing according to an embodiment of the present invention, and Fig. 4 is a picture synchronization signal before and after image processing and correction according to an embodiment of the present invention Waveform diagrams of front and rear viewing angle switching signals. Please refer to Figure 3 and Figure 4 together, the frame period of the picture synchronization signal SYN is T, and the viewing angle switching signal STE is at a low level (level) in the period L, such as logic "0", indicating that the picture corresponding to the left eye; the viewing angle The switching signal STE is at a high level in the period R, such as a logic "1", indicating the picture corresponding to the right eye. After being processed by the image processing circuit 104 , the frame synchronization signal SYN and the frame synchronization signal SYN1 will generate a frame delay time t. The synchronization circuit 110 receives the view switching signal STE from the multiplexer 120 and receives the processed frame synchronization signal SYN1 from the output terminal of the image processing circuit 104 . The synchronization circuit 110 will compare the frame delay time t between the picture synchronization signal SYN1 and the angle of view switching signal STE, that is, the synchronization circuit 110 obtains the frame delay time t by comparing the picture synchronization signal SYN1 and the angle of view switching signal STE, and the angle of view The switching signal STE is delayed or advanced by a frame delay time t to output the corrected viewing angle switching signal STE1 synchronized with the processed picture synchronizing signal SYN1. In this way, the period of the corrected viewing angle switch signal STE1 is synchronized with the period of the processed frame synchronization signal SYN1 .

The delay comparison circuit 130 is coupled to the input terminal and the output terminal of the image processing circuit 104 to receive the frame synchronization signal SYN and the processed frame synchronization signal SYN1 respectively. The delay comparison circuit 130 compares the delay time between the frame synchronization signal SYN1 and the unprocessed frame synchronization signal SYN. The phase judging circuit 140 is coupled to the output terminal of the synchronizing circuit 130 for judging and changing the level or phase of the corrected viewing angle switching signal STE1 output by the synchronizing circuit 110 according to the delay time. Specifically, although the corrected viewing angle switching signal STE1 output by the synchronization circuit 110 is synchronized with the period of the processed picture synchronization signal SYN1, the logic levels corresponding to the period L and period R may be opposite, causing the left and right eyes to Receive the opposite picture. The delay time is obtained by comparing the phase difference between the picture synchronization signal SYN1 and the picture synchronization signal SYN by the delay comparison circuit 130, for example, the time td in FIG. 3 plus the frame delay time (Framedelay time) of N frame periods T , where N is an integer. According to the delay time, it is judged whether the level of the corrected viewing angle switching signal STE1 corresponds to the correct cycle R or cycle L. If the level of the corrected viewing angle switching signal STE1 is wrong, the phase judging circuit 140 can change the corrected viewing angle switching The level or phase of the signal STE1, so that the corrected viewing angle switching signal STE1 output by the synchronous signal correction circuit 106 is still at a low level in the period L, and is at a high level in the period R, and is consistent with the processed picture Synchronization signal SYN1 maintains synchronization, as shown in FIG. 4 .

FIG. 5 is a flow chart of a method for correcting a synchronization signal of a stereoscopic image signal according to an embodiment of the present invention. The synchronization signal correction method in FIG. 5 is applicable to the embodiments in FIGS. 1 to 4 . The steps of the synchronous signal correction method are described below with reference to the symbols of the above-mentioned embodiments.

In step S510 , the image processing circuit 104 receives the frame synchronization signal SYN and outputs the processed frame synchronization signal SYN1 . In step S520, the synchronization circuit 110 compares the frame synchronization signal SYN1 processed by the image processing circuit 104 with the viewing angle switching signal STE, and outputs a corrected viewing angle switching signal STE1 synchronized with the processed frame synchronizing signal SYN1. In addition, the operation method of the embodiment of the present invention can obtain sufficient teachings, suggestions and implementation instructions from the description of the embodiment in FIG. 1 to FIG. 4 , so details are not repeated here.

In summary, the image display device, the stereoscopic image processing circuit and its synchronous signal correction method of the present invention can automatically synchronize the image-processed picture synchronous signal and the corrected visual angle switching signal by adjusting the viewing angle switching signal, and because It is not to adjust the processed picture synchronization signal, so it can also avoid increasing the delay time of the picture. The utility model can eliminate the need for the user to manually adjust the setting action of the stereoscopic image, improve the convenience of using the image display device, and use the image synchronization signal after image processing and the corrected viewing angle switching signal to accurately synchronize the signal . Finally, the structure of the utility model is simple, so it can be easily combined on the main boards of various image display devices, and can also be implemented by a field programmable gate array, which has the advantage of low cost.

Although the utility model has been disclosed as above with the embodiments, it is not intended to limit the utility model, and any skilled person in the art can make some changes and modifications without departing from the spirit and scope of the utility model , so the scope of protection of the present utility model should be defined by the appended claims as the criterion.

Claims (8)

1. A stereoscopic image processing circuit adapted to process a stereoscopic image signal, wherein the stereoscopic image signal includes a picture synchronization signal and a view angle switching signal corresponding to the picture synchronization signal, the stereoscopic image processing circuit comprising a synchronization signal correction circuit, wherein:

the synchronization signal correction circuit is coupled to an image processing circuit, wherein the image processing circuit receives the frame synchronization signal and outputs the processed frame synchronization signal, and the synchronization signal correction circuit includes a synchronization circuit, wherein:

the synchronization circuit is coupled to the output terminal of the image processing circuit to receive the processed frame synchronization signal and simultaneously receive the view switching signal, and the synchronization circuit is configured to compare the processed frame synchronization signal with the view switching signal to output the corrected view switching signal synchronized with the processed frame synchronization signal.

2. The stereoscopic image processing circuit according to claim 1, wherein the synchronization signal correction circuit further comprises:

and the phase judgment circuit is coupled with the output end of the synchronous circuit and used for judging and changing the phase or the level of the corrected visual angle switching signal output by the synchronous circuit.

3. The stereoscopic image processing circuit according to claim 2, wherein the synchronization signal correction circuit further comprises:

a delay comparison circuit coupled to the input terminal and the output terminal of the image processing circuit for comparing the delay time between the processed frame synchronization signal and the unprocessed frame synchronization signal,

wherein the phase judging circuit judges and changes a phase or a level of the corrected view angle switching signal output by the synchronizing circuit according to the delay time.

4. The stereoscopic image processing circuit according to claim 1, wherein the synchronization circuit compares a frame delay time between the processed picture synchronization signal and the view angle switching signal, and delays or advances the view angle switching signal by the frame delay time to output the corrected view angle switching signal in synchronization with the processed picture synchronization signal.

5. The stereoscopic image processing circuit according to claim 1, wherein the synchronization signal correction circuit is implemented as a field programmable gate array.

6. The stereoscopic image processing circuit of claim 1, wherein the synchronization signal correction circuit is coupled between a stereoscopic image decoding circuit and an image input interface, the image input interface is configured to receive the stereoscopic image signal from an image output device, the stereoscopic image decoding circuit is configured to decode the stereoscopic image signal to output the frame synchronization signal to the image processing circuit, wherein the synchronization signal correction circuit further comprises:

a multiplexer, coupled to the synchronization circuit, the stereoscopic image decoding circuit and the image input interface, for selectively receiving the view switching signal from the image input interface or from the stereoscopic image decoding circuit and providing the view switching signal to the synchronization circuit.

7. The stereoscopic image processing circuit according to claim 1, wherein the view switching signal received by the synchronization circuit is the view switching signal corresponding to the frame synchronization signal processed by the image processing circuit or the view switching signal corresponding to the frame synchronization signal not processed by the image processing circuit.

8. An image display device for playing a stereoscopic image, the image display device comprising a stereoscopic image decoding circuit, an image processing circuit, a synchronization signal correction circuit, and an image playing circuit, wherein:

the stereoscopic image decoding circuit is used for decoding a stereoscopic image signal, wherein the stereoscopic image signal comprises a picture synchronization signal and a view switching signal corresponding to the picture synchronization signal;

the image processing circuit is used for receiving the picture synchronization signal from the stereo image decoding circuit and outputting the processed picture synchronization signal;

the synchronization signal correction circuit includes a synchronization circuit, wherein:

the synchronization circuit is coupled to an output terminal of the image processing circuit to receive the processed frame synchronization signal and simultaneously receive the view switching signal, and the synchronization circuit is configured to compare the processed frame synchronization signal with the view switching signal to output the corrected view switching signal synchronized with the processed frame synchronization signal; and

the image playing circuit is used for receiving the processed picture synchronization signal from the image processing circuit and the corrected visual angle switching signal from the synchronization signal correction circuit, and playing the stereoscopic image according to the processed picture synchronization signal and the corrected visual angle switching signal.