CN107277295B - Video synchronization processing device and method - Google Patents

Abstract

The present invention provides a video synchronization processing device and method, the device includes: a first extraction module, used to extract the decoded frame header signal of the decoded video, and synchronously send the video data in the decoded video and the decoded frame header signal to Clock synchronization processing module; Clock frequency recovery module, used to obtain the reference clock frequency from the reference video; Clock synchronization processing module, used to synchronously output video data consistent with the reference clock frequency and decode the frame header signal to the synchronization output module; the second The extraction module is used to extract the reference frame header signal of the reference video; the synchronous output module is used to determine the initial output time of the received video data according to the received decoded frame header signal and the reference frame header signal, and output according to the initial output time the video data. In this way, the video data of each decoded video is double-synchronized in the clock domain and the data domain, which can keep the broadcast TV picture stable and improve people's viewing effect.

Description

Video synchronization processing device and method

technical field

The present invention relates to the technical field of broadcasting and television, in particular to a video synchronization processing device and method.

Background technique

In the broadcasting system of radio and television, some of the multi-channel videos input by the front end of the system come from satellite signals, some from rebroadcast signals, and some from recording and broadcasting signals, etc. Digital Interface, digital component serial interface) output. In order to switch between multiple channels of decoded video (decoded video is called decoded video), the output end of the SDI interface is connected to an SDI switcher, which controls the output of the decoded video.

There may be asynchronous problems in the clock domain or data domain of each channel of decoded video. When the SDI switcher switches between the out-of-sync decoded videos, it will cause the broadcasted TV picture to be unstable, such as jumping and flickering Or scrolling, etc., thereby affecting people's viewing effect.

Contents of the invention

In view of this, the purpose of the present invention is to provide a video synchronization processing device and method, so that the video data of each decoded video is double-synchronized in the clock domain and the data domain, so as to keep the broadcasted TV picture stable and improve people's awareness. Watch the effect.

In the first aspect, the embodiment of the present invention provides a video synchronization processing device, the device includes a first extraction module, a clock frequency recovery module, a clock synchronization processing module, a second extraction module and a synchronization output module;

The first extracting module is used to extract the decoded frame header signal of the decoded video when receiving the decoded video provided by the video source, and synchronously send the video data in the decoded video and the decoded frame header signal to The clock synchronization processing module; wherein, the decoded frame header signal is used to indicate the frame header position of each video frame of the decoded video;

The clock frequency recovery module is configured to obtain a reference clock frequency from the reference video when receiving a reference video provided by a reference source, and send the reference clock frequency to the clock synchronization processing module, and send the reference clock frequency to the clock synchronization processing module. sending the reference video to the second extraction module;

The clock synchronization processing module is used to receive the video data, the decoded frame header signal and the reference clock frequency, and synchronously output the video data and the decoded frame header signal consistent with the reference clock frequency to the synchronous output module;

The second extraction module is used to extract the reference frame header signal of the reference video when receiving the reference video, and send the reference frame header signal to the synchronization output module; wherein, the reference frame The header signal is used to indicate the frame header position of each video frame of the reference video;

The synchronous output module is used to receive the video data, the decoded frame header signal and the reference frame header signal, and determine the initial output of the video data according to the decoded frame header signal and the reference frame header signal time, and output the video data according to the start output time.

With reference to the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the first extraction module is specifically configured to:

Acquire a synchronous signal of the decoded video, the synchronous signal includes a horizontal synchronous signal, a vertical synchronous signal and a field synchronous signal; extract a decoded frame header signal of the decoded video according to the synchronous signal.

With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a second possible implementation manner of the first aspect, wherein the first extraction module includes:

A first extracting unit, configured to extract a decoded frame header signal of the decoded video according to a change position of the field synchronization signal when the decoded video is an interlaced scan video;

The second extraction unit is configured to extract the decoded frame header signal of the decoded video according to the change position of the vertical synchronization signal and the horizontal synchronization signal when the decoded video is a progressive scan video.

In combination with the first aspect, the embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein the clock synchronization processing module includes a writing unit, a storage unit, and a read output unit;

The writing unit is used to synchronously write the received video data and the decoded frame header signal into the storage unit;

The storage unit is used to store the received video data and the decoded frame header signal;

The read output unit is used for synchronously reading the video data and the decoded frame header signal stored in the storage unit according to the received reference clock frequency, and combining the read video data and the The decoded frame header signal is synchronously sent to the synchronous output module.

With reference to the third possible implementation manner of the first aspect, the embodiment of the present invention provides a fourth possible implementation manner of the first aspect, wherein the writing unit is further configured to , repeatedly write the current video frame of the video data into the storage area corresponding to the last video frame before the storage unit overflows;

The read output unit is further configured to repeatedly read the last video frame stored before the storage unit underflows when the storage unit underflows.

With reference to the first aspect, the embodiment of the present invention provides a fifth possible implementation manner of the first aspect, wherein the synchronization output module is specifically used for:

Synchronously read the received video data, the decoded frame header signal and the reference frame header signal; when the decoded frame header signal is read, stop reading the decoded video and continue to read the reference frame header signal, and determine the time when the reference frame header signal is read later as the start output time; output the video data according to the start output time.

With reference to the first aspect, the embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein the device further includes a delay adjustment module;

The delay adjustment module is used to adjust the relative delay between the decoded frame header signal and the reference frame header signal, and send the relative delay to the synchronization output module;

The synchronous output module is further configured to receive the relative delay, determine the start output time according to the relative delay, and output the video data according to the start output time.

In the second aspect, the embodiment of the present invention also provides a video synchronization processing method, the method is applied to the video synchronization processing device as described in the first aspect; the method includes:

When the first extraction module receives the decoded video provided by the video source, it extracts the decoded frame header signal of the decoded video, and synchronously sends the video data in the decoded video and the decoded frame header signal to the A clock synchronization processing module; wherein, the decoded frame header signal is used to indicate the frame header position of each video frame of the decoded video;

When the clock frequency recovery module receives the reference video provided by the reference source, it obtains the reference clock frequency from the reference video, sends the reference clock frequency to the clock synchronization processing module, and sends the reference video sent to the second extraction module;

The clock synchronization processing module receives the video data, the decoded frame header signal and the reference clock frequency, and synchronously outputs the video data and the decoded frame header signal consistent with the reference clock frequency to the synchronization output module;

When the second extraction module receives the reference video, it extracts the reference frame header signal of the reference video, and sends the reference frame header signal to the synchronization output module; wherein, the reference frame header signal Used to indicate the frame header position of each video frame of the reference video;

The synchronous output module receives the video data, the decoded frame header signal and the reference frame header signal, and determines the start output time of the video data according to the decoded frame header signal and the reference frame header signal, And output the video data according to the start output time.

With reference to the second aspect, the embodiment of the present invention provides a first possible implementation manner of the second aspect, wherein when the first extraction module receives the decoded video provided by the video source, extracts the decoded video Decode frame header signals, including:

When the first extracting module receives the decoded video provided by the video source, it acquires a synchronous signal of the decoded video, the synchronous signal includes a horizontal synchronous signal, a vertical synchronous signal and a field synchronous signal;

Extracting a decoded frame header signal of the decoded video according to the synchronization signal.

With reference to the second aspect, the embodiment of the present invention provides a second possible implementation manner of the second aspect, wherein the determination of the initial output of the video data according to the decoded frame header signal and the reference frame header signal time, including:

Synchronously read the received video data, the decoded frame header signal and the reference frame header signal; when the decoded frame header signal is read, stop reading the decoded video and continue to read the reference frame header signal, and determine the time when the reference frame header signal is read later as the start output time.

Embodiments of the present invention bring the following beneficial effects:

In the embodiment of the present invention, the video synchronization processing device includes a first extraction module, a clock frequency recovery module, a clock synchronization processing module, a second extraction module and a synchronization output module; the first extraction module is used to receive the decoded video provided by the video source , extract the decoded frame header signal of the decoded video, and send the video data in the decoded video and the decoded frame header signal to the clock synchronization processing module synchronously; wherein, the decoded frame header signal is used to indicate each video frame of the decoded video The frame header position; the clock frequency recovery module is used to obtain the reference clock frequency from the reference video when receiving the reference video provided by the reference source, and send the reference clock frequency to the clock synchronization processing module, and the reference video Sent to the second extraction module; the clock synchronization processing module is used to receive video data, decode the frame header signal and the reference clock frequency, and synchronously output the video data consistent with the reference clock frequency and decode the frame header signal to the synchronous output module; the second The extraction module is used to extract the reference frame header signal of the reference video when receiving the reference video, and send the reference frame header signal to the synchronous output module; wherein the reference frame header signal is used to indicate each video frame of the reference video Frame header position; the synchronous output module is used to receive video data, decode frame header signals and reference frame header signals, determine the start output time of the video data according to the decoded frame header signals and the reference frame header signals, and determine the start output time of the video data according to the start The video data is output at the output time. The clock synchronization processing module can synchronize the decoded video with the reference video in the clock domain according to the reference clock frequency, and then the synchronization output module can synchronize the decoded video with the reference video in the data domain according to the decoded frame header signal and the reference frame header signal, thereby realizing Double synchronization of decoded video and reference video in clock domain and data domain. Since each channel of decoded video is synchronized with the reference video, by using the video synchronization processing device and method provided by the embodiment of the present invention, the output video data of each channel is double-synchronized in the clock domain and the data domain, thus maintaining the broadcast TV The picture is stable, which improves people's viewing effect.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the specific implementation or description of the prior art. Obviously, the accompanying drawings in the following description The drawings show some implementations of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work.

FIG. 1 is a first structural schematic diagram of a video synchronization processing device provided by an embodiment of the present invention;

2 is a schematic diagram of unit composition of a clock synchronization processing module in a video synchronization processing device provided by an embodiment of the present invention;

3 is a schematic diagram of a processing flow of a video synchronization processing device provided by an embodiment of the present invention;

FIG. 4 is a second structural schematic diagram of a video synchronization processing device provided by an embodiment of the present invention;

FIG. 5 is a schematic flowchart of a video synchronization processing method provided by an embodiment of the present invention.

icon:

10-first extraction module; 20-clock frequency recovery module; 30-clock synchronization processing module; 31-write unit; 32-storage unit; 33-read output unit; 40-second extraction module; 50-synchronous output module; 60-delay adjustment module.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. the embodiment. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Considering that when the SDI switcher switches between asynchronous decoded videos, the broadcasted TV picture will be unstable and affect people's viewing effect, a video synchronization processing device and method provided by the embodiment of the present invention , can double-synchronize the output video data in the clock domain and data domain, keep the broadcast TV picture stable, and improve people's viewing effect.

To facilitate the understanding of this embodiment, a video synchronization processing device disclosed in this embodiment of the present invention is first introduced in detail.

Embodiment one:

Figure 1 is a schematic diagram of the first structure of a video synchronization processing device provided by an embodiment of the present invention. As shown in Figure 1, the device includes a first extraction module 10, a clock frequency recovery module 20, a clock synchronization processing module 30, a second extraction Module 40 and Synchronous Output Module 50.

The first extraction module 10 is used to extract the decoded frame header signal of the decoded video when receiving the decoded video provided by the video source, and synchronously send the video data in the decoded video and the decoded frame header signal to the clock synchronization processing module 30; Wherein, the decoded frame header signal is used to indicate the frame header position of each video frame of the decoded video.

Clock frequency recovery module 20 is used for when receiving the reference video that reference source provides, obtains reference clock frequency from this reference video, and this reference clock frequency is sent to clock synchronization processing module 30, and this reference video is sent to the second Two extraction modules 40 .

The clock synchronization processing module 30 is used to receive video data, decode frame header signals and a reference clock frequency, and synchronously output video data and decoded frame header signals consistent with the reference clock frequency to the synchronization output module 50 .

The second extraction module 40 is used to extract the reference frame header signal of the reference video when receiving the reference video, and send the reference frame header signal to the synchronous output module 50; wherein, the reference frame header signal is used to indicate the reference frame header signal of the reference video The frame header position of each video frame.

Synchronous output module 50 is used for receiving video data, decoded frame header signal and reference frame header signal, determines the initial output time of this video data according to this decoded frame header signal and this reference frame header signal, and outputs according to this initial output time the video data.

In the embodiment of the present invention, the video synchronization processing device includes a first extraction module, a clock frequency recovery module, a clock synchronization processing module, a second extraction module and a synchronization output module, and the clock synchronization processing module can compare the decoded video and the reference video according to the reference clock frequency. Synchronized in the clock domain, and then the synchronous output module can synchronize the decoded video and the reference video in the data domain according to the decoded frame header signal and the reference frame header signal, thus realizing the double synchronization of the decoded video and the reference video in the clock domain and the data domain Synchronize. Since each channel of decoded video is synchronized with the reference video, by using the video synchronization processing device provided by the embodiment of the present invention, the output video data of each channel is double-synchronized in the clock domain and the data domain, thus maintaining the stability of the broadcast TV picture , improving people's viewing effect.

The above video synchronization processing device can be realized by relying on FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chip. For this device, the input source is divided into two parts, one is the video source and the other is the reference source. Among them, the video source can be but not limited to the video data output by the decoder chip, the front-end video input source outputs the decoded video after decoding through the decoder chip, and the decoded video is a digital video; the reference source is an external analog video source, and the output reference video, the reference video For analog video, this reference video is used to provide a reference for the synchronization of each decoded video. The device processes these two input sources synchronously, and the processing process of the device on the decoded video and the reference video will be described in detail below.

(1) the first extraction module 10 extracts the decoding frame header signal of the decoded video and includes: when the first extraction module 10 receives the decoded video, obtains the synchronous signal of the decoded video, the synchronous signal includes a horizontal synchronous signal, a vertical synchronous signal and A field synchronization signal, based on which a decoded frame header signal of the decoded video is extracted, that is, a TOF (Top Of Frame, frame header) signal.

Specifically, for a complete decoded video, its Hsync signal (horizontal synchronization signal), Vsync signal (vertical synchronization signal) and Fsync signal (field synchronization signal) can be obtained, and the Hsync signal is used to indicate that in each video frame of the decoded video The end or starting point of each row of data, the Vsync signal is used to indicate that each row of data in each video frame of the decoded video is in the field blanking interval or the normal interval (effective data row), and the Fsync signal is used to indicate each row of data in each video frame of the decoded video In odd or even field. The TOF signal of the decoded video can be extracted according to the Hsync signal, the Vsync signal and the Fsync signal of the decoded video.

Considering that the scanning mode of video is divided into interlaced scanning and progressive scanning, the first extraction module 10 includes: a first extraction unit, which is used to extract the decoded video of the decoded video according to the change position of the field synchronization signal when the decoded video is an interlaced video. The frame header signal; the second extracting unit is used to extract the decoded frame header signal of the decoded video according to the change position of the vertical synchronization signal and the horizontal synchronization signal when the decoded video is a progressive scan video.

Specifically, for interlaced scanning video, since each video frame includes two fields-odd field and even field, the Fsync signal is low level and high level (or vice versa) in the odd field and even field respectively, so it can be based on the Fsync signal Level changes to determine the frame header position, thereby extracting the TOF signal. For example, if each video frame of the decoded video scans the odd field first, and then scans the even field, the Fsync signal in the odd field is low level, and the Fsync signal in the even field is high level, then when the Fsync signal changes from high level to When it is low level, it means that the even field scanning of the current video frame ends, and the odd field of the next video frame starts to be scanned, that is, the frame head position of the corresponding video frame can be determined at this time, thereby extracting the TOF signal.

For progressive scan video, the Fsync signal remains unchanged, and the TOF signal cannot be extracted according to the Fsync signal at this time. Considering that each video frame of progressive scan video includes three parts: field blanking interval, forward interval and vertical blanking interval, the number of lines in the vertical blanking interval after the regular interval in the same video system is fixed, and the Vsync signal The vertical blanking interval and the forward interval are respectively high level and low level (or vice versa), so the end position of the forward interval can be determined by the level change of the Vsync signal, and the next video can be found by determining the number of lines according to the Hsync signal The frame header position of the frame, thereby extracting the TOF signal. For example, if each video frame of the decoded video includes 750 lines, the 1st-25th row is the vertical blanking interval, the 26th-745th row is the normal interval, the 746th-750th row is the vertical blanking interval, and the Vsync signal is high in the vertical blanking interval Level, if it is low level in the forward interval, when it is detected that the Vsync signal changes from low level to high level, it can be determined that it is scanning from the forward interval to the vertical blanking interval (such as lines 745-746 ), and then determine the position after 5 lines as the frame header position of the next video frame according to the Hsync signal, thereby extracting the TOF signal.

(2) The processing of the reference video by the clock frequency recovery module 20 includes: when the clock frequency recovery module 20 receives the reference video provided by the reference source, restore the analog video source clock of the reference video, and use the analog video source clock as the decoded video The processing clock of the reference video is to obtain the reference clock frequency of the reference video, and use the reference clock frequency as the clock frequency after the decoded video is synchronized, so as to realize the synchronization of the decoded video and the reference video in the clock domain.

(3) The clock synchronization processing module 30 is used to synchronize the decoded video and the reference video in the clock domain. FIG. 2 is a schematic diagram of the unit composition of the clock synchronization processing module in the video synchronization processing device provided by the embodiment of the present invention. As shown in FIG. Writing unit 31 is used for synchronously writing the received video data and decoded frame header signal into storage unit 32; Storage unit 32 is used for storing received video data and decoded frame header signal; Read output unit 33 is used for according to the reference received Clock frequency, synchronously read the video data and decoded frame header signal stored in the storage unit 32 , and synchronously send the read video data and decoded frame header signal to the synchronous output module 50 .

Considering that when the clock frequency of the decoded video itself is not consistent with the reference clock frequency, the writing rate of the writing unit 31 is not consistent with the output rate of the reading output unit 33, so the storage unit 32 is used to cache video data. The clock synchronization processing module 30 may, but is not limited to, use DDR to cache data. The full name of DDR is DDR SDRAM (Double Data Rate SDRAM, double rate SDRAM), where SDRAM is Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory.

Further, considering that when the write rate is greater than the output rate, it will cause DDR storage overflow, the write unit 31 is also used to repeatedly write the current video frame of the video data into the storage unit 32 when the storage overflow occurs in the storage unit 32 The storage area corresponding to the last video frame before overflow. Considering that when the write rate is less than the output rate, it will cause DDR storage underflow, and the read output unit 33 is also used to repeatedly read the last video frame stored before the storage unit 32 underflows when the storage unit 32 underflows . In this way, it is ensured that the video data output from the DDR is a complete frame, and at the same time, the TOF signal is also output to the synchronization output module 50 together with the clock-synchronized video data.

(4) The second extraction module 40 is used to extract the reference frame header signal of the reference video, ie the TOF signal. Specifically, the reference video itself also carries synchronization signals: Hsync signal, Vsync signal and Fsync signal. Since the synchronization signal of the reference video is an analog video synchronization signal, it is necessary to use an analog-to-digital conversion chip to convert the Hsync signal, Vsync signal and Fsync signal of the reference video converted to the digital domain for use by the second extraction module 40 . The process of extracting the TOF signal of the reference video by the second extracting module 40 is the same as the process of extracting the TOF signal of the decoded video by the first extracting module 10 , and will not be repeated here.

(5) The synchronous output module 50 is specifically used for: synchronously reading received video data, decoded frame header signal and reference frame header signal; when reading the decoded frame header signal, stop reading the decoded video, and continue to read the reference frame header signal, and determine the time when the reference frame header signal is read later as the start output time; output the video data according to the start output time. The output interface of the synchronous output module 50 may be an SDI interface. In this way, the decoded video is consistent with the reference video in the data domain.

Fig. 3 is a schematic diagram of the processing flow of the video synchronization processing device provided by the embodiment of the present invention. As shown in Fig. 3, the processing flow of the device includes the following steps:

Step S301, the first extraction module extracts the TOF signal of the decoded video.

In step S302, the clock frequency recovery module acquires a reference clock frequency from a reference video.

Step S303, the second extraction module extracts the TOF signal of the reference video.

It should be noted that step S301 and step S302 or step S303 can be executed synchronously, and the execution sequence of step S302 and step S303 is not limited. In FIG. 3 , step S302 is executed first, and then step S303 is executed as an example for illustration.

Step S304, the clock synchronization processing module performs clock domain synchronization on the received decoded video and the reference video, and outputs it to the synchronization output module.

Step S305, the synchronization output module performs data domain synchronization of the decoded video and the reference video, and outputs video data synchronized with the reference video.

For the specific execution process of the above steps, reference may be made to the foregoing content, and details are not repeated here.

Considering that the video data output by the above-mentioned video synchronization processing device will be processed later, and the influence of the external environment, the actual video data and the reference video cannot be completely synchronized in the data domain, as shown in Figure 4. 1, the device also includes a delay adjustment module 60, the delay adjustment module 60 is used to adjust the relative delay between the decoded frame header signal and the reference frame header signal, and send the relative delay to the synchronization output module 50 . The synchronous output module 50 is also specifically configured to receive the relative delay, determine the start output time according to the relative delay, and output the video data according to the start output time.

Specifically, the user can adjust the above-mentioned relative delay through the delay adjustment module 60. The basic unit of adjustment is a reference clock cycle, which is equal to the adjustment of a video frame, and the accuracy is very high. Wherein, the reference clock cycle corresponds to the reference clock frequency . This further ensures the synchronization of the video data and the reference video in the data domain.

Considering that the above-mentioned relative delay is not fixed when the reference source is abnormal or changed, when the relative delay changes are detected multiple times, a resynchronization method can be used to maintain the real-time synchronization between the decoded video and the reference video.

It can be seen from the above that the video synchronization processing device provided by the embodiment of the present invention can double-synchronize the video data of the decoded video and the reference video in the clock domain and the data domain, while ensuring that the synchronization accuracy and real-time performance meet the requirements.

Embodiment two:

This implementation provides a video synchronization processing method, which is applied to the video synchronization processing device in Embodiment 1. Fig. 5 is a schematic flowchart of a video synchronization processing method provided by an embodiment of the present invention. As shown in Fig. 5, the method includes the following steps:

Step S501, when the first extraction module receives the decoded video provided by the video source, extract the decoded frame header signal of the decoded video, and synchronously send the video data in the decoded video and the decoded frame header signal to the clock synchronization processing module ; Wherein, the decoded frame header signal is used to indicate the frame header position of each video frame of the decoded video.

Step S502, when the clock frequency recovery module receives the reference video provided by the reference source, obtain the reference clock frequency from the reference video, and send the reference clock frequency to the clock synchronization processing module, and send the reference video to the second Extract the module.

Step S503, the clock synchronization processing module receives the video data, the decoded frame header signal and the reference clock frequency, and synchronously outputs the video data and the decoded frame header signal consistent with the reference clock frequency to the synchronization output module.

Step S504, when the second extraction module receives the reference video, extract the reference frame header signal of the reference video, and send the reference frame header signal to the synchronous output module; wherein, the reference frame header signal is used to indicate each of the reference video The frame header position of the video frame.

Step S505, the synchronous output module receives the video data, the decoded frame header signal and the reference frame header signal, determines the start output time of the video data according to the decoded frame header signal and the reference frame header signal, and outputs according to the start output time the video data.

The process of the first extracting module extracting the decoded frame header signal of the decoded video is specifically: when the first extracting module receives the decoded video provided by the video source, it obtains the synchronous signal of the decoded video, and the synchronous signal includes a horizontal synchronous signal and a vertical synchronous signal and field synchronous signal; extract the decoded frame header signal of the decoded video according to the synchronous signal.

The process of determining the start output time of video data according to the decoded frame header signal and the reference frame header signal is specifically: synchronously read the received video data, decoded frame header signal and reference frame header signal; when the decoded frame header signal is read , stop reading the decoded video, continue to read the reference frame header signal, and determine the time when the reference frame header signal is read later as the start output time.

In the embodiment of the present invention, when the first extraction module receives the decoded video provided by the video source, it extracts the decoded frame header signal of the decoded video, and synchronously sends the video data in the decoded video and the decoded frame header signal to the clock A synchronization processing module; wherein, the decoded frame header signal is used to indicate the frame header position of each video frame of the decoded video. When the clock frequency recovery module receives the reference video provided by the reference source, it obtains the reference clock frequency from the reference video, sends the reference clock frequency to the clock synchronization processing module, and sends the reference video to the second extraction module. The clock synchronization processing module receives video data, decoded frame header signal and reference clock frequency, and synchronously outputs video data and decoded frame header signal consistent with the reference clock frequency to the synchronization output module. When the second extracting module receives the reference video, it extracts the reference frame header signal of the reference video, and sends the reference frame header signal to the synchronous output module; wherein, the reference frame header signal is used to indicate each video frame of the reference video frame header position. The synchronous output module receives video data, decoded frame header signal and reference frame header signal, determines the start output time of the video data according to the decoded frame header signal and the reference frame header signal, and outputs the video data according to the start output time . The clock synchronization processing module can synchronize the decoded video with the reference video in the clock domain according to the reference clock frequency, and then the synchronization output module can synchronize the decoded video with the reference video in the data domain according to the decoded frame header signal and the reference frame header signal, thereby realizing Double synchronization of decoded video and reference video in clock domain and data domain. Since each channel of decoded video is synchronized with the reference video, the video synchronization processing method provided by the embodiment of the present invention is applied, and the output video data of each channel is double-synchronized in the clock domain and the data domain, thus maintaining the stability of the broadcast TV picture , improving people's viewing effect.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the method described above can refer to the corresponding process in the foregoing device embodiment, which will not be repeated here.

The video synchronization processing method provided in the embodiment of the present invention has the same technical features as the video synchronization processing device provided in the above embodiment, so it can also solve the same technical problem and achieve the same technical effect.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or part of code that includes one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for description purposes only, and should not be understood as indicating or implying relative importance.

The computer program product for performing the video synchronization processing method provided by the embodiment of the present invention includes a computer-readable storage medium storing processor-executable non-volatile program code, and the instructions included in the program code can be used to execute the preceding method For the method described in the embodiment, the specific implementation may refer to the method embodiment, and details are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .

Finally, it should be noted that: the above-described embodiments are only specific implementations of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting them, and the scope of protection of the present invention is not limited thereto, although referring to the foregoing The embodiment has described the present invention in detail, and those skilled in the art should understand that any person familiar with the technical field can still modify the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention Changes can be easily thought of, or equivalent replacements are made to some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of the present invention within the scope of protection. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. a kind of audio video synchronization processing unit, which is characterized in that described device includes the first extraction module, clock frequency recovery mould Block, clock synchronization process module, the second extraction module and synchronous output module；

First extraction module is used to extract the decoding of the decoding video when receiving the decoding video of video source offer Header signal, and synchronize to be sent to the clock synchronous by video data and the decoding header signal in the decoding video Processing module；Wherein, the decoding header signal is used to indicate the frame header position of each video frame of the decoding video；

The clock frequency recovery module is used to obtain from the reference video when receiving the reference video of reference source offer It takes reference clock frequency, and the reference clock frequency is sent to the clock synchronization process module, and by the reference Video is sent to second extraction module；

The clock synchronization process module is for receiving the video data, the decoding header signal and reference clock frequency Rate, and synchronism output and the consistent video data of the reference clock frequency and header signal is decoded to the synchronism output mould Block；

Second extraction module is used for when receiving the reference video, extracts the reference frame head letter of the reference video Number, and the synchronous output module is sent to reference to header signal by described；Wherein, described to be used to indicate institute with reference to header signal State the frame header position of each video frame of reference video；

The synchronous output module for receive the video data, the decoding header signal and it is described refer to header signal, According to the decoding header signal and the starting output time for determining the video data with reference to header signal, and according to institute State the starting output time output video data.

2. the apparatus according to claim 1, which is characterized in that first extraction module is specifically used for:

The synchronization signal of the decoding video is obtained, the synchronization signal includes horizontal synchronizing signal, vertical synchronizing signal and field Synchronization signal；The decoding header signal of the decoding video is extracted according to the synchronization signal.

3. the apparatus of claim 2, which is characterized in that first extraction module includes:

First extraction unit is used for when the decoding video is interlaced scanning video, according to the variation of the field sync signal Extract the decoding header signal of the decoding video in position；

Second extraction unit is used for when the decoding video is progressive scanned video, according to the change of the vertical synchronizing signal Change position and the horizontal synchronizing signal extracts the decoding header signal of the decoding video.

4. the apparatus according to claim 1, which is characterized in that the clock synchronization process module includes writing unit, deposits Storage unit and reading output unit；

Said write unit is used to for the received video data and the decoding header signal to be synchronously written the storage single Member；

The storage unit is for storing the received video data and the decoding header signal；

The reading output unit is synchronous to read what the storage unit stored for the reference clock frequency based on the received The video data and the decoding header signal, and by the video data of reading it is synchronous with the decoding header signal hair It send to the synchronous output module.

5. device according to claim 4, which is characterized in that said write unit is also used to occur when the storage unit The last one video when overflow, before the current video frame of the video data to be repeatedly written to the storage unit overflow The corresponding storage region of frame；

The reading output unit is also used to when storage underflow occurs in the storage unit, and repetition is read under the storage unit The last one video frame stored before overflowing.

6. the apparatus according to claim 1, which is characterized in that the synchronous output module is specifically used for:

It is synchronous to read the received video data, the decoding header signal and described with reference to header signal；When reading When stating decoding header signal, stop reading the decoding video, continue to read it is described with reference to header signal, and will after read The time with reference to header signal is determined as the starting output time；The time output video is exported according to the starting Data.

7. the apparatus according to claim 1, which is characterized in that described device further includes delay adjustment module；

The delay adjustment module is used to adjust the decoding header signal and the relative time delay with reference between header signal, And the relative time delay is sent to the synchronous output module；

The synchronous output module is specifically also used to receive the relative time delay, determines that the starting is defeated according to the relative time delay Time out, and the time output video data is exported according to the starting.

8. a kind of audio video synchronization processing method, which is characterized in that the method is applied in such as any one of claims 1 to 7 institute In the audio video synchronization processing unit stated；The described method includes:

When first extraction module receives the decoding video of video source offer, the decoding frame head of the decoding video is extracted Signal, and by video data and the decoding header signal in the decoding video synchronize be sent to the clock synchronization process Module；Wherein, the decoding header signal is used to indicate the frame header position of each video frame of the decoding video；

When the clock frequency recovery module receives the reference video of reference source offer, ginseng is obtained from the reference video It examines clock frequency, and the reference clock frequency is sent to the clock synchronization process module, and by the reference video It is sent to second extraction module；

The clock synchronization process module receives the video data, the decoding header signal and the reference clock frequency, And synchronism output and the consistent video data of the reference clock frequency and header signal is decoded to the synchronous output module；

When second extraction module receives the reference video, the reference header signal of the reference video is extracted, and The synchronous output module is sent to reference to header signal by described；Wherein, described to be used to indicate the ginseng with reference to header signal Examine the frame header position of each video frame of video；

The synchronous output module receives the video data, the decoding header signal and described with reference to header signal, according to The decoding header signal and the starting output time that the video data is determined with reference to header signal, and according to described Begin the output time output video data.

9. according to the method described in claim 8, it is characterized in that, described mention when first extraction module receives video source When the decoding video of confession, the decoding header signal of the decoding video is extracted, comprising:

When first extraction module receives the decoding video of video source offer, the synchronous letter of the decoding video is obtained Number, the synchronization signal includes horizontal synchronizing signal, vertical synchronizing signal and field sync signal；

The decoding header signal of the decoding video is extracted according to the synchronization signal.

10. according to the method described in claim 8, it is characterized in that, described according to the decoding header signal and the reference Header signal determines the starting output time of the video data, comprising:

It is synchronous to read the received video data, the decoding header signal and described with reference to header signal；When reading When stating decoding header signal, stop reading the decoding video, continue to read it is described with reference to header signal, and will after read The time with reference to header signal is determined as the starting output time.