CN209593406U - A Novel Operational Amplifier Circuit Suitable for 12-bit Pipeline ADC - Google Patents

Abstract

The utility model discloses a novel operational amplifier circuit suitable for 12-bit pipeline ADC (Analog-to-Digital Converter, analog-to-digital converter) circuit, comprising a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, and a PMOS tube M4 , NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupling capacitor Cin1, coupling capacitor Cin2, load capacitor CL1, load capacitor CL2, current source Ib, input voltage Vin+, input voltage Vin‑, common mode voltage Vcm , output voltage Vo+, output voltage Vo‑, first switch s1, second switch s2, third switch s3, fourth switch s4, fifth switch s5, sixth switch s6, seventh switch s7, eighth switch s8, The ninth switch s9, the tenth switch s10, the eleventh switch s11 and the twelfth switch s12. The charging state and working state of the circuit are controlled by the switch, which improves the work efficiency, adopts two mutually coupled circuit structures, reduces power consumption, saves chip area, and improves the common-mode rejection ability and power supply rejection ability, which contributes to noise reduction. improved.

Description

A Novel Operational Amplifier Circuit Suitable for 12-bit Pipeline ADC

technical field

The utility model relates to a novel operation amplifier circuit suitable for 12-bit assembly line ADC (Analog-to-Digital Converter, analog-to-digital converter). It belongs to the field of analog integrated circuit design and integrated system.

Background technique

Pipeline ADC can provide a high sampling rate between 6-bit and 12-bit resolution, so driven by the market, it is widely used in mobile communication systems, portable equipment and test equipment and other fields. The main trend of pipeline ADC design is to reduce power consumption and chip area. As an important component module of pipeline ADC, the operational amplifier is required to have low noise, low power consumption and other performances while maintaining linearity and other characteristics. The performance of the amplifier determines the performance of the pipeline ADC to a certain extent, so the design of the operational amplifier is extremely important.

Contents of the invention

The purpose of the utility model is to design the operational amplifier circuit in the pipeline ADC, reduce the power consumption of the pipeline ADC while ensuring the stable performance of the pipeline ADC, reduce the chip area, and reduce the noise. Therefore, a fully symmetrical new operational amplifier circuit operating through switch control is provided.

Above-mentioned purpose of the present utility model is mainly realized by following scheme:

A basic framework of a 12-bit pipeline ADC as shown in Figure 1, is characterized in that: comprise pipeline stage circuit (101), first stage pipeline internal circuit (102), delay and calibration circuit (103), novel operational amplifier circuit ( 104), where:

Pipeline-level circuit (101): It is composed of five pipelined ADC circuits cascaded. The first-stage 3.5-bit pipelined ADC circuit adopts a circuit structure without sampling and holding SHA_Less. Compared with a circuit structure with sampling and holding SHA, it achieves the same While improving the performance, the power consumption is reduced by about 20%, and the influence of non-linear factors such as noise introduced by the latter due to its own structure is eliminated. The second, third, and fourth-stage 1.5-bit circuits adopt an op-amp sharing structure, which can reduce power consumption while increasing speed. Finally, a 3-bit flash ADC circuit is cascaded, and the output of each stage is connected to the input of the next stage; the internal circuit (102) of the first stage pipeline: it is the frame diagram of the SHA_Less circuit, and the input signal vin1 is directly Access the sub-level ADC circuit and the addition circuit, the sub-level ADC circuit converts the input analog signal into a digital signal Dout and access the following delay and calibration circuit (103), while the output of the sub-level ADC circuit is also connected to the sub-level ADC circuit The input of the first-stage DAC circuit, the sub-level DAC circuit converts the connected digital signal Dout into an analog signal vdac again, and then subtracts it from the previous input signal vin1, and the obtained margin is amplified by the amplifier to obtain vout, and finally connected to the In the circuit of the next stage, vin2 continues to perform the same work as the input of the next stage;

Delay and calibration circuit (103): the error code output by the previous stage is calibrated by a digital error correction algorithm, and finally the number of digits obtained after calibration is the 12-bit accuracy of the entire pipeline ADC;

A new operational amplifier circuit (104): amplifies the remainder after subtracting the input signal vin1 from the analog quantity vdac, and the obtained output voltage vout is sent to the next pipeline stage as the input vin2 of the next stage.

The new operational amplifier circuit (104) mentioned above adopts a mutually coupled capacitor structure, which can reduce the capacitor size, thereby reducing the chip area, and utilizes the characteristics of the gradual decay of the capacitor to reduce the nonlinear distortion of the operational amplifier circuit, thereby To achieve the effect of increasing power, it can also provide a certain common mode rejection capability.

The above-mentioned novel operational amplifier circuit (104) adopts a mutually coupled resistive load structure, which makes the output impedance of the amplifier in the differential mode much higher than the output impedance in the common mode while ensuring the symmetry of the circuit. High common mode rejection ratio CMRR and power supply rejection ratio PSRR, so as to achieve the effect of reducing noise.

The new operational amplifier circuit (104) mentioned above is shown in Figure 2, including PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8 , coupling capacitor Cin1, coupling capacitor Cin2, load capacitor CL1, load capacitor CL2, current source Ib, input voltage Vin+, input voltage Vin-, common mode voltage Vcm, output voltage Vo+, output voltage Vo-, first switch s1, second The second switch s2, the third switch s3, the fourth switch s4, the fifth switch s5, the sixth switch s6, the seventh switch s7, the eighth switch s8, the ninth switch s9, the tenth switch s10, the eleventh switch s11 and The twelfth switch s12.

The above-mentioned novel operational amplifier circuit (104) includes two clock phases respectively controlling two working states, clock phase Φ1 and clock phase Φ2, wherein the clock phase Φ1 controls the closing of switches s1 to s6, and the closing of switches s7 to s12 Open; the clock phase Φ2 controls the switch s1 to switch s6 to open, and the switch s7 to switch s12 to close.

Among them, when the clock phase Φ1, as shown in Figure 3, includes PMOS transistor M1, PMOS transistor M2, two coupling capacitors Cin1 and Cin2, two load capacitors CL1 and CL2, common mode voltage Vcm, wherein, the gate of PMOS transistor M1 The pole is connected to the gate of the PMOS transistor M2, the drain and one end of the current source Ib, the source is connected to VDD, and the drain is respectively connected to the upper plates of the two coupling capacitors Cin1 and Cin2, and the two coupling capacitors Cin1 and Cin2 The lower plates are connected to the ground, the source of the PMOS transistor M2 is connected to VDD, the upper plates of the two load capacitors CL1 and CL2 are respectively connected to the common mode voltage Vcm, the lower plate is connected to the ground, and the other end of the current source is connected to the ground; the clock When phase Φ2, as shown in Figure 4, including PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupling capacitor Cin1, coupling capacitor Cin2, load capacitor CL1, load capacitor CL2 , input voltage Vin+, input voltage Vin-, output voltage Vo+, output voltage Vo-, wherein, the gate of the PMOS transistor M3 is connected to Vin+, the source is connected to the upper plate of the coupling capacitor Cin2, and the drain is respectively connected to the load capacitor CL1 The upper plate of the upper plate, the output voltage Vo-, the drain and gate of the NMOS transistor M7, the drain of the NMOS transistor M5 and the gate of the NMOS transistor M6 are connected, the gate of the PMOS transistor M4 is connected to the output voltage Vin-, and the source Connected to the upper plate of the coupling capacitor Cin1, the drain is respectively connected to the upper plate of the load capacitor CL2, the output voltage Vo+, the drain and gate of the NMOS transistor M8, the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5 , the lower plate of the coupling capacitor Cin1 is connected to the sources of the NMOS transistor M7 and the NMOS transistor M5 respectively, and the lower plate of the coupling capacitor Cin2 is connected to the sources of the NMOS transistor M6 and the NMOS transistor M8 respectively.

Compared with the prior art, the technical solution of the utility model has the following beneficial effects:

This utility model is mainly researched from the aspects of increasing the working efficiency of the operational amplifier, reducing the chip area, and reducing noise. Aiming at the working efficiency, the working structure of the switch control circuit is adopted. The operational amplifier can be charged first when it is not working. The power supply of the operational amplifier improves the working speed. At the same time, the attenuation characteristics of the capacitor are used to reduce the distortion caused by the nonlinearity of the operational amplifier, thereby improving the working efficiency. The mutual coupling capacitor structure adopted can reduce the chip area. The mutual coupling resistive load structure can greatly increase the output impedance while increasing the common mode rejection ratio and power supply rejection ratio, thereby reducing noise.

Description of drawings

Fig. 1 is the frame diagram of a kind of 12 pipeline ADCs proposed by the utility model;

Fig. 2 is a kind of novel operational amplifier circuit (104) structure schematic diagram that is applicable to 12 pipeline ADCs of the utility model;

Fig. 3 is a kind of structural representation of the novel operation amplifier circuit (104) that is applicable to 12 pipeline ADCs of the utility model when clock phase Φ1;

Fig. 4 is a kind of structural representation of the novel operational amplifier circuit (104) that is applicable to 12 pipelined ADCs of the utility model when clock phase Φ 2;

Detailed ways

In order to further introduce the specific content of the utility model, the structural characteristics of the circuit, and the working states of different clock phases of the circuit, the utility model will be described in detail in conjunction with the accompanying drawings.

The utility model provides a frame diagram of a 12-bit pipeline ADC, as shown in Figure 1, including a pipeline level circuit (101), a first-level pipeline internal circuit (102), a delay and calibration circuit (103), a new type of operation Amplifying circuit (104), here in order to realize reducing chip area, reduce power consumption, improve work efficiency, reduce noise etc. object, proposed a kind of novel operational amplifier circuit (104), as shown in Figure 2, comprise PMOS transistor M1, PMOS Tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupling capacitor Cin1, coupling capacitor Cin2, load capacitor CL1, load capacitor CL2, current source Ib, input voltage Vin+ , input voltage Vin-, common mode voltage Vcm, output voltage Vo+, output voltage Vo-, first switch s1, second switch s2, third switch s3, fourth switch s4, fifth switch s5, sixth switch s6, The seventh switch s7, the eighth switch s8, the ninth switch s9, the tenth switch s10, the eleventh switch s11 and the twelfth switch s12.

As shown in FIG. 2 , the novel operational amplifier circuit ( 104 ) adopts a circuit structure of mutual coupling capacitors and a circuit structure of mutually coupled resistors as loads. Among them, the capacitive structure of mutual coupling can reduce the size of the capacitor, thereby reducing the chip area, using the characteristics of the gradual decay of the capacitor, reducing the nonlinear distortion of the op amp circuit, thereby achieving the effect of increasing the power, and also providing a certain common Mode suppression ability; the mutually coupled resistive load structure ensures the symmetry of the circuit while making the output impedance of the amplifier in the differential mode much higher than that in the common mode mode, which greatly increases the common mode rejection capability and power supply Inhibition ability, so as to achieve the effect of reducing noise.

The new operational amplifier circuit (104) has two states, charging state and working state, wherein, the charging state corresponds to the clock phase Φ1, and the clock phase Φ1 controls the closing of the switch s1 to the switch s6, and the opening of the switch s7 to the switch s12, as shown in Fig. 3 As shown, it includes PMOS transistor M1, PMOS transistor M2, two coupling capacitors Cin1 and Cin2, two load capacitors CL1 and CL2, and common mode voltage Vcm, wherein the gate of PMOS transistor M1 and the gate and drain of PMOS transistor M2 The pole and one end of the current source Ib are connected, the source is connected to VDD, the drain is respectively connected to the upper plates of the two coupling capacitors Cin1 and Cin2, the lower plates of the two coupling capacitors Cin1 and Cin2 are connected to the ground, and the PMOS transistor M2 The source of the current source is connected to VDD, the upper plates of the two load capacitors CL1 and CL2 are respectively connected to the common mode voltage Vcm, the lower plate is connected to the ground, and the other end of the current source is connected to the ground; the working state corresponds to the clock phase Φ2, and the clock phase Φ2 controls Switches s1 to s6 are disconnected, switches s7 to s12 are closed, as shown in Figure 4, including PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M8, coupling capacitor Cin1, Coupling capacitor Cin2, load capacitor CL1, load capacitor CL2, input voltage Vin+, input voltage Vin-, output voltage Vo+, output voltage Vo-, wherein, the gate of the PMOS transistor M3 is connected to Vin+, and the source is connected to the top of the coupling capacitor Cin2 The plates are connected, the drains are respectively connected to the upper plate of the load capacitor CL1, the output voltage Vo-, the drain and gate of the NMOS transistor M7, the drain of the NMOS transistor M5 and the gate of the NMOS transistor M6, and the PMOS transistor M4 The gate is connected to the output voltage Vin-, the source is connected to the upper plate of the coupling capacitor Cin1, the drain is respectively connected to the upper plate of the load capacitor CL2, the output voltage Vo+, the drain and gate of the NMOS transistor M8, and the NMOS transistor M6 The drain of the coupling capacitor Cin1 is connected to the gate of the NMOS transistor M5, the lower plate of the coupling capacitor Cin1 is connected to the source of the NMOS transistor M7 and the NMOS transistor M5 respectively, and the lower plate of the coupling capacitor Cin2 is connected to the NMOS transistor M6 and the source of the NMOS transistor M8 respectively. source connected. In summary, the above is a specific embodiment of the utility model, and the principle of the utility model has been described in the above description. The protection scope of the present utility model is not limited thereto. Any simple structural changes made by any designer in the professional field within the disclosure scope of the present utility model all belong to this utility model. Therefore, the protection scope of the present utility model should be determined by the scope of claims.

Claims (5)

1. a kind of novel operational amplification circuit (104) suitable for 12 pipeline ADCs, it is characterised in that: including PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor Cin2, load capacitance CL1, load capacitance CL2, current source Ib, input voltage vin+, input voltage vin-, Common-mode voltage Vcm, output voltage Vo+, output voltage Vo-, first switch s1, second switch s2, third switch s3, the 4th switch S4, the 5th switch s5, the 6th switch s6, the 7th switch s7, the 8th switch s8, the 9th switch s9, the tenth switch s10, the 11st Switch s11 and the 12nd switch s12.

2. novel operational amplification circuit (104) according to claim 1, it is characterised in that: the condenser network being mutually coupled Structure includes PMOS tube M1, coupled capacitor Cin1, coupled capacitor Cin2, first switch s1, second switch s2, the 5th switch s5, 6th switch s6, wherein the both ends of first switch s1 and second switch s2 are connected in the drain electrode and coupled capacitor of PMOS tube M1 respectively The both ends of Cin1, the top crown of coupled capacitor Cin2, the 5th switch s5 and the 6th switch s6 be connected in respectively and coupled capacitor Cin1, the bottom crown of coupled capacitor Cin2.

3. novel operational amplification circuit (104) according to claim 1, it is characterised in that: the resistance being mutually coupled is born The circuit structure of load includes PMOS tube M3, and PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, the 7th opens Close s7, the 8th switch s8, the 9th switch s9, the tenth switch s10, wherein PMOS tube M3, PMOS tube M4 as Differential Input pipe, The source electrode of PMOS tube M3 is connected in one end of the 7th switch s7, and grid is connected with Vin+, drain electrode respectively with the drain electrode of NMOS tube M7 and Grid, the drain electrode of NMOS tube M5 and the grid of NMOS tube M6 are connected, and the source electrode of PMOS tube M4 is connected in one end of the 8th switch s8, Grid is connected with output voltage Vin-, the drain and gate of drain electrode difference NMOS tube M8, the drain electrode and NMOS tube of NMOS tube M6 The grid of M5 is connected;The source electrode of PMOS tube M5 is connected in one end of the 9th switch s9, and the source electrode of PMOS tube M7 is connected in the 9th switch s9 The other end, the source electrode of PMOS tube M6 is connected in one end of the tenth switch s10, and the source electrode of PMOS tube M8 is connected in the tenth switch s10's The other end.

4. novel operational amplification circuit (104) according to claim 1, it is characterised in that: at 1 corresponding circuits of clock phase Φ In charged state, clock phase Φ 1 controls first switch s1 and is closed to the 6th switch s6, the 7th switch s7 to the 12nd switch s12 It disconnects, including PMOS tube M1, PMOS tube M2, two coupled capacitor Cin1 and Cin2, two load capacitances CL1 and CL2, common mode electricity Press Vcm, wherein one end of the grid of PMOS tube M1 and the grid of PMOS tube M2, drain electrode and current source Ib are connected, and source electrode connects VDD, drain electrode are connected in respectively on the top crown of two coupled capacitors Cin1 and Cin2, the lower pole of two coupled capacitors Cin1 and Cin2 Plate all connects ground, and the source electrode of PMOS tube M2 is connected with VDD, the top crown of two load capacitances CL1 and CL2 respectively with common-mode voltage Vcm is connected, and even, the other end of current source is even for bottom crown.

5. novel operational amplification circuit (104) according to claim 1, it is characterised in that: at 2 corresponding circuits of clock phase Φ In magnifying state, clock phase Φ 2 control switch s1 to switch s6 is disconnected, switch s7 to switch s12 closure, including PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor Cin2, load electricity Hold CL1, load capacitance CL2, input voltage vin+, input voltage vin-, output voltage Vo+, output voltage Vo-, wherein PMOS The grid of pipe M3 is connected with Vin+, and source electrode is connected with the top crown of coupled capacitor Cin2, drains upper with load capacitance CL1 respectively Pole plate, output voltage Vo-, the drain and gate of NMOS tube M7, the drain electrode of NMOS tube M5 and the grid of NMOS tube M6 are connected, The grid of PMOS tube M4 is connected with output voltage Vin-, and source electrode is connected with the top crown of coupled capacitor Cin1, drain electrode respectively with it is negative Carry the top crown of capacitor CL2, output voltage Vo+, the drain and gate of NMOS tube M8, the drain electrode of NMOS tube M6 and NMOS tube M5 Grid be connected, respectively with NMOS tube M7, the source electrode of NMOS tube M5 is connected the bottom crown of coupled capacitor Cin1, coupled capacitor Respectively with NMOS tube M6, the source electrode of NMOS tube M8 is connected the bottom crown of Cin2.