CN209543343U - Big data operation acceleration system - Google Patents

Abstract

The utility model embodiment provides a kind of big data operation acceleration system, including more than two operation chips and more than two storage units, wherein the operation chip includes at least one first data-interface and more than two second data-interfaces；The storage unit includes more than two third data-interfaces；Second data-interface of the operation chip is connect with the third data-interface of the storage unit, is used for transmission data or control instruction；At least one first data-interface of the operation chip is connected, and is used for transmission control instruction.Accelerate the processing speed of data.

Description

Big Data Operation Acceleration System

technical field

The embodiment of the utility model relates to the field of integrated circuits, in particular to a big data operation acceleration system.

Background technique

Application Specific Integrated Circuits (ASIC) refers to integrated circuits designed and manufactured in response to specific user requirements and the needs of specific electronic systems. The characteristic of ASIC is that it is oriented to the needs of specific users. Compared with general-purpose integrated circuits, ASIC has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and reduced cost when mass-produced.

With the development of science and technology, more and more fields, such as artificial intelligence, security computing, etc., involve specific calculations with large amounts of calculations. For specific calculations, ASIC chips can take advantage of their specific features such as fast calculations and low power consumption. At the same time, in order to improve the data processing speed and processing capacity for these fields with a large amount of computation, it is usually necessary to control N computing chips to work at the same time. With the continuous improvement of data accuracy, artificial intelligence, security computing and other fields need to calculate more and more large data. In order to store data, it is generally necessary to configure multiple storage units for ASIC chips. For example, an ASIC chip needs to be configured with four pieces of 2G memory. ; In this way, when N computing chips work at the same time, 4N pieces of 2NG memory are needed. However, when multiple computing chips work at the same time, the data storage capacity will not exceed 2 G, which causes waste of storage units and increases system cost.

Utility model content

The embodiment of the utility model provides a big data operation acceleration system, in which two or more ASIC operation chips are respectively connected to two or more storage units through a bus, and the operation chips perform data exchange through the storage units, which not only reduces storage The number of units also reduces the connection lines between ASIC computing chips, simplifies the system structure, and each ASIC computing chip is connected to multiple storage units, which will not cause conflicts in the use of bus methods, and does not need to be used for each The ASIC computing chip sets the Cache.

In order to achieve the above object, according to the first aspect of this embodiment, a big data computing acceleration system is provided, including more than 2 computing chips and more than 2 storage units; the computing chip includes at least one first data interface (130) and More than two second data interfaces (150, 151, 152, 153), the storage unit includes more than two second data interfaces (250, 251, 252, 253); each second data interface of the computing chip (150, 151, 152, 153) are connected to each second data interface (250, 251, 252, 253) of the storage unit in one-to-one correspondence through the bus, and are used to transmit data or control instructions; the two or more Each at least one first data interface (130) of the computing chip is connected through a bus for transmitting control instructions.

The embodiment of the utility model achieves the technical effect of saving the number of memory units by connecting multiple computing chips in the big data computing acceleration system to each memory unit, reduces the system cost and reduces the connection lines between ASIC computing chips , which simplifies the system structure, and each ASIC computing chip is connected to multiple storage units separately, which will not cause conflicts due to the way of using the bus, and there is no need to set a Cache for each ASIC computing chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are merely exemplary embodiments, and those skilled in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is a schematic structural diagram of the big data operation acceleration system provided by the first embodiment of the present invention;

Fig. 2a is a schematic structural diagram of the computing chip provided by the first embodiment of the present invention;

Fig. 2b is a schematic diagram of the signal flow of the computing chip provided by the first embodiment of the present invention;

Fig. 3a is a schematic structural diagram of the computing chip provided by the second embodiment of the present invention;

Fig. 3b is a schematic diagram of the signal flow of the computing chip provided by the second embodiment of the present invention;

Fig. 4a is a schematic structural diagram of the storage unit provided by the third embodiment of the present invention;

Fig. 4b is a schematic diagram of the signal flow of the storage unit provided by the third embodiment of the present invention;

5 is a schematic diagram of the connection structure of the big data operation acceleration system provided by the fourth embodiment of the present invention;

Fig. 6 is a schematic diagram of the data structure provided by the fifth embodiment of the present invention.

Detailed ways

The exemplary implementations of this embodiment will be described in detail below based on the accompanying drawings. It should be understood that these implementations are given only to enable those skilled in the art to better understand and realize the present utility model, rather than to limit the present invention in any way. Scope of utility model. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In addition, it should be noted that the directions of up, down, left, and right in the drawings are only examples of specific implementations, and those skilled in the art can adjust the components shown in the drawings according to actual needs. A part or all of them can be applied by changing the direction without affecting the function of each component or the system as a whole. This technical solution with changed direction still belongs to the protection scope of the present utility model.

A multi-core chip is a multi-processing system embodied on a single large-scale integrated semiconductor chip. Typically, two or more chip cores may be embodied on a multi-core chip, interconnected by a bus (which may also be formed on the same multi-core chip). There can be anywhere from two chip cores to many chip cores embodied on the same multi-core chip, the upper limit in the number of chip cores being limited only by manufacturing capabilities and performance constraints. Multi-core chips can have applications that include execution in multimedia and signal processing algorithms such as video encoding/decoding, 2D/3D graphics, audio and speech processing, image processing, telephony, speech recognition and sound synthesis, encryption processing specialized arithmetic and/or logical operations.

Although only an ASIC is mentioned in the background art, the specific wiring implementation in the embodiment can be applied to a multi-core chip such as a CPU, GPU, or FPGA. In this embodiment, the multiple cores may be the same core or different cores.

For the convenience of explanation, the big data operation acceleration system with 4 computing chips and 4 storage units in Fig. 1 will be used as an example to illustrate, and those skilled in the art know that 4 computing chips and 4 storage units are selected here As an example, it is just an exemplary description, the number of computing chips may be N, where N is a positive integer greater than or equal to 2, for example, N may be 6, 10, 12 and so on. The number of storage units may be M, where M is a positive integer greater than or equal to 2, for example, M may be 6, 9, 12 and so on. In an embodiment, N and M may or may not be equal. In this embodiment, the multiple computing chips may be the same computing chip, or may be different computing chips.

FIG. 1 is a schematic structural diagram of a big data operation acceleration system provided by the first embodiment of the present invention. In the embodiment shown in FIG. 1 , the big data operation acceleration system includes four operation chips and four storage units as an example for description. Please refer to Figure 1, the big data computing acceleration system includes 4 computing chips (10, 11, 12, 13) and 4 storage units (20, 21, 22, 23); Optionally, the computing chip and the storage unit may be connected through a bus or through a data line. The computing chips exchange data through the storage unit, and the computing chips do not directly exchange data; the computing chips send control instructions.

A dedicated storage area and a shared storage area are set in each storage unit; the dedicated storage area is used to store a temporary calculation result of an operation chip, and the temporary operation result is an intermediate calculation result that the one operation chip continues to use, and Intermediate calculation results that are not used by other computing chips. The shared storage area is used to store data operation results of the operation chip, and the data operation results are used by other operation chips, or need to be fed back and transmitted to the outside. Of course, for the convenience of management, the storage units may not be divided. Here the storage unit may be Double Data Rate (DDR), Serial Double Data Rate (SDDR), DDR2, DDR3, DDR4, Graphics Double Data Rate (GDDR) ) 5. GDDR6, Hybrid Memory Cube (HMC), High Band Memory (HBM) and other high-speed external memory. Here, the storage unit preferably selects a DDR series memory, and the DDR memory is a double-rate synchronous dynamic random access memory. DDR uses a synchronous circuit, so that the main steps of specified address, data transmission and output are executed independently, and are fully synchronized with the CPU; DDR uses a delay locked loop (Delay Locked Loop, DL) to provide a data filtering signal technology, when The memory controller can use this data filter signal to pinpoint data when data is valid, output every 16th, and resynchronize data from different memory modules. The frequency of DDR memory can be expressed in two ways: operating frequency and equivalent frequency. The operating frequency is the actual operating frequency of the memory particles. However, since DDR memory can transmit data at both rising and falling edges of the pulse, the equivalent frequency of transmitting data is twice the operating frequency. DDR2 memory is a new generation memory technology standard developed by the Joint Electron Device Engineering Council (JEDEC). DDR2 memory can read/write data at 4 times the speed of the external bus per clock, and can internally control the bus. Runs at 4x speed. DDR3, DDR4, GDDR5, GDDR6, HMC, and HBM memory are all existing technologies, so I won’t introduce them in detail here.

The four ASIC computing chips are respectively connected to the four storage units through the bus, and the computing chips exchange data through the storage units, which not only reduces the number of storage units, but also reduces the connection lines between the ASIC computing chips, The system structure is simplified, and each ASIC computing chip is connected to multiple storage units, which will not cause conflicts in the way of using the bus, and there is no need to set a Cache for each ASIC computing chip.

Fig. 2a is a schematic structural diagram of the computing chip provided by the first embodiment of the present invention. In FIG. 2a , the computing chip has 4 cores as an example for illustration. Those skilled in the art know that the selection of 4 cores as an example here is only an exemplary illustration. The number of cores in the computing chip can be Q, where Q is a positive integer greater than or equal to 2, such as 6, 10, 12, etc. Wait. In this embodiment, the computing chip cores may be cores with the same function, or cores with different functions.

The computing chip (10) with 4 cores includes 4 cores (110, 111, 112, 113), a routing unit (120), a data exchange control unit (130) and 4 serdes interfaces (150, 151, 152 , 153). A data exchange control unit and 4 serdes interfaces are respectively connected to the routing unit through the bus, and the routing unit is connected to each core core. The data exchange control unit can be implemented using a variety of protocols, for example, Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (Serial Peripheral Interface, SPI), high-speed serial computer expansion bus standard (peripheral component interconnectexpress, PCIE), serializer/deserializer (SERializer/DESerializer, SERDES), Universal Serial Bus (Universal Serial Bus, USB), etc., in this embodiment, the data exchange control unit is a UART control unit (130). The Universal Asynchronous Receiver Transmitter is usually called UART, which is an asynchronous transceiver that converts the data to be transmitted between serial communication and parallel communication. UART is usually integrated on the connection of various communication interfaces. But here we just take the UART protocol as an example, and other protocols can also be used. The UART control unit (130) can receive external data or control instructions, send control instructions to other chips, receive control instructions from other chips, and feed back operation results or intermediate data to the outside.

Serdes is a mainstream time division multiplexing (Time Division Multiplexing, TDM), point-to-point (Point to Point, P2P) serial communication technology. That is, at the sending end, multiple low-speed parallel signals are converted into high-speed serial signals, passed through the transmission medium (optical cable or copper wire), and finally the high-speed serial signals are re-converted into low-speed parallel signals at the receiving end. This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of required transmission channels and device pins, increases the transmission speed of signals, and thus greatly reduces communication costs. Of course, other communication interfaces may also be used here instead of the serdes interface, for example: Synchronous Serial Interface (Synchronous Serial Interface, SSI), UATR. Data and control instructions are transmitted between the chip and the storage unit through the serdes interface and the transmission line.

The main function of the kernel core is to execute external or internal control instructions, perform data calculation, and data storage control.

The routing unit is used to send data or control instructions to the core cores (110, 111, 112, 113), and accept data or control instructions sent by the core cores (110, 111, 112, 113), so as to realize communication between the core cores. Accept internal or external control commands to write data to the storage unit, read data or send control commands to the memory unit through the serdes interface; if the internal or external control commands are used to control the control commands of other chips, the routing unit sends the control commands to The UART control unit (130) is sent to other chips by the UART control unit (130); if it is necessary to send data to other chips, the routing unit transmits data to the storage unit through the serdes interface, and other chips obtain data through the storage unit; When other chips receive data, the routing unit obtains data from the storage unit through the serdes interface. The routing unit receives external control instructions through the UART control unit (130), and sends control instructions to each core core (110, 111, 112, 113); receives external data through the UART control unit (130), and transfers the external data according to the external data address Send to the kernel core (110, 111, 112, 113) or storage unit. The internal data or internal control instructions refer to data or control instructions generated by the chip itself, and the external data or external control instructions refer to data or control instructions generated outside the chip, such as data or control instructions sent by an external host or an external network. instruction.

Fig. 2b is a schematic diagram of the signal flow of the computing chip provided by the first embodiment of the present invention. In FIG. 2b , it is illustrated by taking the computing chip with 4 cores as an example. Please refer to Fig. 2 b, the UART interface (130) is used to obtain chip external data or control instruction, routing unit (120) sends data or control instruction to core core according to data or control instruction address, or routing unit (120) passes The serdes interface sends to the storage unit connected to the serdes interface. If the destination address of the external control command points to other chips, the routing unit sends the control command to the UART control unit (130), and the UART control unit (130) sends it to other chips. The UART interface (130) sends the calculation result to the outside according to the external control command or the internal control command. The calculation result can be obtained from the core core of the calculation chip, or can be obtained through the serdes interface to obtain the storage unit connected to the serdes interface. The external mentioned here may refer to an external host, an external network, or an external platform. The external host can initialize and configure the parameters of the storage unit through the UART control unit, and uniformly address multiple storage particles.

The kernel core can send a control instruction to acquire or write data to the routing unit, and the control instruction carries a data address, and the routing unit reads or writes data to the storage unit through the serdes interface according to the address. The core core can also send data or control instructions to other core cores through the routing unit according to the address, and obtain data or control instructions from other core cores through the routing unit. The kernel core performs calculations based on the acquired data, and stores the calculation results in the storage unit. A dedicated storage area and a shared storage area are set in each storage unit; the dedicated storage area is used to store a temporary calculation result of an operation chip, and the temporary operation result is an intermediate calculation result that the one operation chip continues to use, and The intermediate calculation results that will not be used by other computing chips; the shared storage area is used to store the data computing results of the computing chips, and the data computing results are used by other computing chips, or need to be fed back and transmitted to the outside. If the control instruction generated by the core is used to control the operation of other chips, the routing unit sends the control instruction to the UART control unit (130), and the UART control unit (130) sends it to other chips. If the control instruction generated by the kernel core is used to control the storage unit, the routing unit sends the control instruction to the storage unit through the serdes interface.

Fig. 3a is a schematic structural diagram of the computing chip provided by the second embodiment of the present invention. In FIG. 3 a , the computing chip has 4 cores as an example for illustration. According to Fig. 3a, it can be seen that the computing chip with 4 cores includes 4 core cores (110, 111, 112, 113), a routing unit (120), a UART control unit (130) and 4 serdes interfaces (150, 151, 152, 153). Each serdes interface is connected to one core core, four core cores are connected to the routing unit, and the UART control unit (130) is connected to the core core (110).

Fig. 3b is a schematic diagram of the signal flow of the computing chip provided by the second embodiment of the present invention. In FIG. 3b , it is illustrated by taking the computing chip with 4 cores as an example. Please refer to Fig. 3b, the UART control unit (130) is used to obtain chip external data or control instructions, and transmit the external data or control instructions to the core core (110) connected to the UART control unit. The core core (110) transmits external data or control instructions to the routing unit (120), and the routing unit sends the data or control instructions to the core cores (111, 112, 113) corresponding to the data address according to the data or control instruction address. If the destination address of the data or control instruction is the core core of the computing chip, the routing unit sends the data or control instruction to the core core (110, 111, 112, 113). If the destination address of the data or control instruction is a storage unit, the kernel core (111, 112, 113) sends it to the corresponding storage unit through the serdes interface (151, 152, 153). The kernel core (110) can also directly send data or control instructions to the corresponding storage unit through the serdes interface (150) connected to itself. In this case, the routing unit stores the serdes interfaces corresponding to all storage unit addresses. If the destination address of the data or control instruction is another computing chip, the data is sent to the corresponding storage unit by the kernel core (111, 112, 113) through the serdes interface (151, 152, 153); the control instruction is sent to the corresponding storage unit through the UART control unit. Other computing chips. When the kernel core feeds back the operation result or intermediate data to the outside according to the external control instruction or internal control instruction, the kernel core obtains the operation result or intermediate data from the storage unit through the serdes interface, and sends the operation result or intermediate data to the routing unit, and the routing unit will The operation result or intermediate data is sent to the core (110) connected to the UART control unit, and finally the operation result or intermediate data is sent to the outside through the UART control unit. If the operation result or intermediate data is obtained by the serdes interface corresponding to the core core connected to the UART control unit, then the operation result or intermediate data is directly sent to the outside through the UART control unit. The external mentioned here may refer to an external host, an external network, or an external platform. The external host can initialize and configure storage unit parameters through the UART control unit, and uniformly address multiple storage units.

The core core can send control instructions to the routing unit, and the routing unit sends control instructions to other core cores, other chips or storage units according to the address of the control instruction. After receiving the control instructions, other core cores, other chips or storage units perform corresponding operations. When the kernel core sends control instructions or data to other kernel cores, it is directly forwarded through the routing unit. The kernel core sends control commands to other chips through the UART control unit. When the kernel core sends a control instruction to the storage unit, the routing unit queries the corresponding serdes interface of the address according to the address, sends the control instruction to the kernel core corresponding to the serdes interface, and then the kernel core sends it to the corresponding serdes interface, and the serdes interface sends the instruction to the storage unit Send control commands. When the core core sends data to other chips or storage units, the routing unit queries the serdes interface corresponding to the address according to the address, sends the control command to the core core corresponding to the serdes interface, and then the core core sends it to the corresponding serdes interface, and the serdes interface sends the control command to the corresponding serdes interface. The storage unit sends data. Other chips are acquiring data through memory cells. When the kernel core obtains data from the memory unit, it reads the data address in the control instruction, and the routing unit queries the serdes interface corresponding to the address according to the address, sends the control instruction to the kernel core corresponding to the serdes interface, and then the kernel core sends it to the corresponding The serdes interface, the serdes interface sends a read control command to the storage unit, and the command carries a destination address and a source address. After the serdes interface acquires data from the storage unit, it sends the data to the kernel core corresponding to the serdes interface. The kernel core sends the data packet including the source address and the destination address to the routing unit, and the routing unit sends the data packet to the corresponding data packet according to the destination address. The kernel core. If the kernel core finds that the destination address is its own address, the kernel core obtains the data for processing. And the core core can also send data or commands to other core cores through the routing unit, and obtain data or commands from other core cores through the routing unit. The kernel core performs calculations based on the acquired data, and stores the calculation results in the storage unit. A dedicated storage area and a shared storage area are set in each storage unit; the dedicated storage area is used to store a temporary calculation result of an operation chip, and the temporary operation result is an intermediate calculation result that the one operation chip continues to use, and The intermediate calculation results that will not be used by other computing chips; the shared storage area is used to store the computing data results of the computing chips, which are used by other computing chips or need to be fed back and transmitted to the outside.

Fig. 4a is a schematic structural diagram of the storage unit provided by the third embodiment of the present invention. In FIG. 4 a , it is described as an example that the storage unit corresponds to the computing chip with 4 cores, that is, in FIG. 4 a , the storage unit corresponds to the computing chip shown in the first embodiment. See also Fig. 4 a, storage unit (20) comprises C storage memory, illustrate with C=4 as example here, certainly wherein C is the positive integer greater than or equal to 2, for example can be 6,10,12 etc.; Storage (240 , 241, 242, 243) include a storage controller (220, 221, 222, 223) and storage particles (210, 211, 212, 213); the storage controller is used to write or read data to the storage particles according to instructions, and store Granules are used to store data. The storage unit (20) further includes a routing unit (230) and four serdes interfaces (250, 251, 252, 253). The four serdes interfaces are respectively connected to the routing unit through the bus, and the routing unit is connected to each memory.

Fig. 4b is a schematic diagram of the signal flow of the storage unit provided by the third embodiment of the present invention. In FIG. 4b , it is described as an example that the storage unit corresponds to the computing chip with 4 cores, that is, in FIG. 4b , the storage unit corresponds to the computing chip shown in the first embodiment. Please refer to Fig. 4b, the storage unit (20) receives the control command through the serdes interface (250, 251, 252, 253), and sends the control command to the routing unit (230), and the routing unit sends the control command according to the address in the control command For the corresponding storage (240, 241, 242, 243), the storage controller (220, 221, 222, 223) performs related operations according to the control instruction. For example, perform unified addressing on multiple storage particles according to the initial configuration memory parameters; or reset and reset the storage particles according to the reset instruction; write instructions or read instructions and other operations. The data acquisition instruction sent by the computing chip is accepted through the serdes interface (250, 251, 252, 253). The instruction carries the address of the data to be obtained. The routing unit sends the data acquisition instruction to the memory according to the address. The data is obtained from the granule, and the data is sent to the computing chip that requires the data through the serdes interface according to the source address. The write data instruction and data sent by the computing chip are accepted through the serdes interface (250, 251, 252, 253). The instruction carries the address of the data to be written, and the routing unit sends the write data instruction and data to the memory according to the address, and the storage control The device writes data into the storage particles according to the write data instruction. Write data instruction and data can be transmitted synchronously or asynchronously. A dedicated storage area and a shared storage area are set in each storage unit; the dedicated storage area is used to store a temporary calculation result of an operation chip, and the temporary operation result is an intermediate calculation result that the one operation chip continues to use, and The intermediate calculation results that will not be used by other computing chips; the shared storage area is used to store the computing data results of the computing chips, which are used by other computing chips or need to be fed back and transmitted to the outside.

Fig. 5 is a schematic diagram of the connection structure of the big data operation acceleration system provided by the fourth embodiment of the present invention. In FIG. 5 , the big data computing acceleration system has 4 computing chips and 4 storage units as an example for illustration. Please refer to FIG. 5 , the big data computing acceleration system includes 4 computing chips (10, 11, 12, 13) and 4 storage units (20, 21, 22, 23). The structure of the computing chip can be the chip structure disclosed in the first embodiment and the second embodiment. Of course, the computing chip can also be an equivalently improved chip structure made by those skilled in the art for the first and second embodiments. These equivalently improved The chip structure is also within the protection scope of this embodiment. The structure of the storage unit can be the storage unit structure disclosed in the third embodiment. Of course, the storage unit can also be the storage unit structure equivalently improved by those skilled in the art for the third embodiment. These equivalently improved storage unit structures are also described in this paper. The scope of protection of the embodiment. In the big data operation acceleration system, the UART control unit (130) of the operation chip (10) is connected to an external host, and the UART control unit (130) of each chip (10, 11, 12, 13) is connected through a bus. Each serdes interface (150, 151, 152, 153) of the chip (10, 11, 12, 13) is connected to a serdes interface (250, 251, 252, 253) of a storage unit (20, 21, 22, 23), Furthermore, each computing chip is connected to all storage units through a bus, and the computing chips perform data exchange through the storage units, and data is not directly exchanged between computing chips. The internal and external signal flows of the computing chip and the storage unit have been described in detail in the first, second and third embodiments, and will not be described again here.

Optionally, in the embodiment shown in FIG. 5, the UART control unit (130) in any computing chip can be connected to an external host, and the UART control units (130) in other computing chips are connected sequentially. The computing chip connected with the external host can receive the control instruction of the external host through the UART control unit (130), and send the control instruction to other computing chips.

For example, the UART control unit (130) in the computing chip 10 can be connected with an external host, the UART control unit (130) in the computing chip 11 is connected with the UART control unit (130) in the computing chip 10, and the UART in the computing chip 12 The control unit (130) is connected with the UART control unit (130) in the operation chip 11, and the UART control units (130) in the operation chips 1 and 3 are connected with the UART control unit (130) in the operation chip 12.

Optionally, the UART control unit (130) in each computing chip 12 can also be connected to an external host respectively.

The system is applied to the field of artificial intelligence. The UART control unit (130) of the computing chip (10) stores the image data or video data sent by the external host to the storage unit (20, 153) through the serdes interface (150, 151, 152, 153). 21, 22, 23), the arithmetic chip (10, 11, 12, 13) generates the mathematical model of the neural network, and the mathematical model can also be stored in the storage unit by the external host through the serdes interface (150, 151, 152, 153) (20, 21, 22, 23), read by each computing chip (10, 11, 12, 13). Running the first-layer mathematical model of the neural network on the computing chip (10), the computing chip (10) reads data from the storage unit (20, 21, 22, 23) through the serdes interface to perform calculations, and stores the calculation results through the serdes interface to at least one of the storage units (20, 21, 22, 23). The computing chip (10) sends a control instruction to the computing chip (20) through the UART control unit (130), and starts the computing chip (20) to perform computing. Run the second-layer mathematical model of the neural network on the computing chip (20), the computing chip (20) reads data from the storage unit (20, 21, 22, 23) through the serdes interface to perform calculations, and stores the calculation results through the serdes interface to at least one of the storage units (20, 21, 22, 23). Each chip executes one layer of the neural network, obtains data from the storage unit (20, 21, 22, 23) through the serdes interface for calculation, and only calculates the calculation result at the last layer of the neural network. The computing chip (10) obtains computing results from the storage units (20, 21, 22, 23) through the serdes interface, and feeds back to the external host through the UART control unit (130).

The system is applied to the field of encrypted digital currency, and the UART control unit (130) of the computing chip (10) stores block information sent by an external host into at least one storage unit (20, 21, 22, 23). The external host sends control instructions to the four computing chips (10, 11, 12, 13) through the computing chips (10, 11, 12, 13) and the UART control unit (130) to perform data computing, and the four computing chips (10, 11, 12, 13) Start the computing operation. Of course, an external host can also send control instructions to a computing chip (10) UART control unit (130) to perform data calculations, and the computing chip (10) sends control commands to other 3 computing chips (11, 12, 13) in turn to perform data calculations , 4 computing chips (10, 11, 12, 13) start computing operations. It is also possible for an external host to send a control command to a computing chip (10) UART control unit (130) to perform data calculation, and the first computing chip (10) sends a control command to the second computing chip (11) to perform data computing, and the second computing chip (11) send control instruction to the 3rd operation chip (12) and carry out data operation, the 3rd operation chip (12) sends control instruction to the 4th operation chip (13) and carry out data operation, 4 operation chips (10,11,12 , 13) Start the computing operation. The 4 computing chips (10, 11, 12, 13) read the block information data from the storage unit through the serdes interface, and the 4 computing chips (10, 11, 12, 13) perform the workload proof calculation at the same time, and the computing chips ( 10) Obtain the operation result from the storage unit (20, 21, 22, 23), and feed it back to the external host through the UART control unit (130).

In the above-mentioned embodiment, the numbers of the operation chip and the storage unit are equal, and at this moment, the number of the second data interface of the storage unit and the number of the second data interface of the operation chip are both the number of the storage unit .

However, those skilled in the art know that the numbers of the computing chips and the storage units may also be unequal. At this time, the number of the second data interfaces of the storage units is the number of computing chips, and the number of the second data interfaces of the computing chips is equal to that of the computing chips. The number of data interfaces is the number of storage units. For example, there are 4 computing chips and 5 storage units. At this time, 5 second data interfaces are set on the computing chips, and 4 second data interfaces are set on the storage units.

The bus can adopt a centralized arbitration bus structure or a ring topology bus structure. The bus technology is a common technology in this field, so it will not be introduced in detail here.

Fig. 6 is a schematic diagram of the data structure provided by the fifth embodiment of the present invention. The data mentioned here refers to various types of data such as command data, numerical data, and character data. The data format specifically includes valid bit valid, destination address dst id, source address src id and data data. The kernel can judge whether the data packet is a command or a value through the effective bit valid. Here, it can be assumed that 0 represents a value and 1 represents a command. The kernel will judge the destination address, source address and data type according to the data structure. From the point of view of instruction execution time sequence, a traditional six-stage pipeline structure is adopted in this embodiment, which are instruction fetch, decoding, execution, memory access, alignment, and write-back stages. From the point of view of the instruction set architecture, a reduced instruction set architecture can be adopted. According to the general design method of simplifying the instruction set architecture, the instruction set of the utility model can be divided into register-register type instructions, register-immediate data instructions, jump instructions, memory access instructions, control instructions and inter-core communication instructions according to functions.

Using the description provided herein, an embodiment can be implemented as a machine, process or article of manufacture by using standard programming and/or engineering techniques to produce programmed software, firmware, hardware, or any combination thereof.

Any generated program(s) (with computer-readable program code) may be embodied on one or more computer-usable media, such as a resident storage device, a smart card or other removable storage device, or a transmission device, Computer program products and articles of manufacture are thus made according to the embodiments. As such, the terms "article of manufacture" and "computer program product" as used herein are intended to cover a computer program that exists either permanently or temporarily on any computer-usable, non-transitory medium.

As noted above, memory/storage devices include, but are not limited to, magnetic disks, optical disks, removable storage devices (such as smart cards, Subscriber Identification Modules (SIMs), Wireless Identification Modules (WIMs)), semiconductor Memory (such as Random Access Memory (Random Access Memory, RAM), Read Only Memory (Read Only Memory, ROM), Programmable Read Only Memory (Programmable Read Only Memory, PROM)) and the like. Transmission media includes, but is not limited to, transmission via wireless communications networks, the Internet, intranets, telephone/modem based network communications, hardwired/cable communications networks, satellite communications, and other fixed or mobile network systems/communication links.

Although specific example embodiments have been disclosed, those skilled in the art will appreciate that changes can be made to the specific example embodiments without departing from the spirit and scope of the invention.

Above, with reference to the accompanying drawings, the present utility model has been described based on the embodiment, but the present utility model is not limited to the above-mentioned embodiment, and the parts of each embodiment and each modified example may be appropriately combined or replaced according to the layout requirements, etc. included in the scope of the present utility model. In addition, based on the knowledge of those skilled in the art, the combination and processing order of each embodiment may be appropriately reorganized, or modifications such as various design changes may be added to each embodiment, and embodiments with such modifications may also be included in the present application. new range.

Although the utility model has described various concepts in detail, those skilled in the art can understand that various modifications and substitutions to those concepts can be realized under the spirit of the overall teaching disclosed in the utility model. Those skilled in the art can implement the invention set forth in the claims without undue experimentation using ordinary techniques. It is to be understood that the specific concepts disclosed are illustrative only and are not intended to limit the scope of the present invention, which is to be determined by the appended claims and their full scope of equivalents.

Claims (33)

1. A big data computing acceleration system, characterized in that it comprises more than two computing chips and more than two storage units, wherein, The computing chip includes at least one first data interface and more than two second data interfaces; The storage unit includes more than two third data interfaces; The second data interface of the computing chip is connected to the third data interface of the storage unit for transmitting data or control instructions; The at least one first data interface of the computing chip is connected to transmit control instructions. 2. The system according to claim 1, wherein the second data interface and the third data interface are serdes interfaces, and the first data interface is a UART interface of a Universal Asynchronous Receiver Transmitter UART control unit. 3. The system according to claim 1 or 2, wherein the number of the computing chips is equal to the number of the storage units, and the number of the third data interfaces of the storage units is the same as the number of the third data interfaces of the computing chips. The number of the second data interface is the number of the storage units. 4. The system according to claim 1, wherein the number of the computing chips is not equal to the number of the storage units, the number of the third data interfaces of the storage units is the number of the computing chips, The number of the second data interfaces of the computing chip is the number of the storage units. 5. The system according to claim 1 or 2, wherein the computing chip further comprises at least two cores and a routing unit; the at least one first data interface and more than two second data interfaces are respectively connected to the routing unit, and the routing unit is connected to the at least two cores. 6. The system according to claim 5, wherein the routing unit is configured to send data or control instructions to the core, and receive data or control instructions sent by the core. 7. The system according to claim 5, wherein the routing unit is configured to write data to the storage unit, read data, or send data to the memory unit through the third data interface according to the received control instruction. Control instruction. 8. The system according to claim 5, wherein the routing unit sends a control command to an external chip through the at least one first data interface. 9. The system according to claim 5, wherein the computing chips send or receive data through the second data interface and the storage unit. 10. The system according to claim 5, wherein the routing unit receives external data or control instructions through the at least one first data interface, and sends the received external data or control instructions to the core or storage unit. 11. The system according to claim 1 or 2, wherein the computing chip further comprises at least two cores and a routing unit; each second data interface is connected to a core, and the at least two cores are connected to the The routing unit is connected, and the at least one first data interface is connected to a core. 12. The system according to claim 11, wherein the at least one first data interface is used to obtain chip external data or control instructions, and transmit the external data or control instructions to the at least one first data interface. A kernel connected to a data interface; or, the at least one first data interface is used to obtain operation results or intermediate data from the kernel connected to the at least one first data interface to feed back to the outside; or, the at least one first data The interface is used to send control commands to external chips. 13. The system according to claim 11, wherein the core is used to transmit data or control instructions to the routing unit; or, send data or control instructions to the storage unit through the two or more second data interfaces ; Or, obtain data from the storage unit through the two or more second data interfaces. 14. The system according to claim 11, wherein the routing unit is configured to send the data or control instruction to the core corresponding to the data address according to the address of the data or control instruction. 15. The system according to claim 1 or 2, wherein the storage unit further comprises two or more storage devices and a routing unit; the two or more third data interfaces are respectively connected to the routing unit, and the routing unit The unit is also connected to the two or more memories. 16. The system according to claim 15, wherein the memory comprises a storage controller and a storage particle, wherein the storage controller is used to write or read data to the storage particle according to an instruction, and the storage particle Used to store data. 17. The system according to claim 15, wherein the routing unit receives control commands through the two or more third data interfaces, and sends the control commands to corresponding Memory (240, 241, 242, 243). 18. The system according to claim 15, wherein the routing unit is configured to send the acquired data to the computing chip through the two or more third data interfaces. 19. The system according to claim 15, wherein a dedicated storage area and a shared storage area are set in the storage unit. 20. The system according to claim 15, wherein the at least one first data interface is used to initialize and configure the two or more storage units according to received external instructions, and for the two or more storage units The storage particles are uniformly addressed. 21. The system according to claim 16 or 20, wherein the storage particle is a hybrid memory cube (HMC) memory. 22. The system according to claim 1, wherein the two or more computing chips perform one or more of encryption operations and convolution calculations. 23. The system according to claim 1, wherein the two or more computing chips respectively perform independent computing, and each computing chip calculates a result separately. 24. The system according to claim 1, wherein the two or more computing chips perform cooperative operations, and each computing chip performs calculations based on calculation results of other two or more computing chips. 25. A big data computing acceleration system, characterized in that it includes more than two computing chips and more than two storage units; the computing chip includes N cores, wherein said N is a positive integer greater than or equal to 2; Each of the two or more computing chips is connected to all the storage units in the two or more storage units. 26. The system according to claim 25, wherein the two or more computing chips exchange data through the storage unit. 27. The system according to claim 25, wherein the two or more computing chips perform one or more of encryption operations and convolution calculations. 28. The system according to claim 25, wherein the two or more computing chips perform independent computing, and each computing chip calculates a result separately. 29. The system according to claim 25, wherein the two or more computing chips perform cooperative operations, and each computing chip performs computing based on the calculation results of the other two or more computing chips. 30. A big data computing acceleration system, characterized in that it includes more than two computing chips and more than two storage units; the computing chips include at least one first data interface and two or more second data interfaces, and the storage The unit includes more than two data interfaces; each second data interface of the operation chip is connected with each third data interface of the storage unit; and each first data interface of the two or more operation chips is connected. 31. The system according to claim 30, wherein the two or more computing chips perform one or more of encryption operations and convolution calculations. 32. The system according to claim 30, wherein the two or more computing chips respectively perform independent computing, and each computing chip calculates a result separately. 33. The system according to claim 30, wherein the two or more computing chips perform cooperative operations, and each computing chip performs computing based on the calculation results of the other two or more computing chips.