CN209149287U - Big data computing acceleration system - Google Patents

Abstract

The embodiment of the present invention provides a big data computing acceleration system, including more than two computing chips, the computing chip includes N cores, N data channels and at least one storage unit, the data channel includes a sending interface and a receiving interface, the core and the data The channels correspond one-to-one; more than two computing chips are connected to transmit data through the sending interface and the receiving interface; at least one storage unit is used for distributed storage of data. In this system, the external memory of the chip is cancelled, and the storage unit is arranged inside the ASIC chip, which reduces the time for the ASIC chip to read data from the outside, and speeds up the operation speed of the chip. Multiple ASIC chips share storage units, which not only reduces the number of storage units, but also reduces the connection lines between the ASIC computing chips, simplifies the system structure, and reduces the cost of the ASIC chips. At the same time, the serdes interface technology is used for data transmission between multiple computing chips, which improves the rate of data transmission between multiple ASIC chips.

Description

Big data computing acceleration system

technical field

The present disclosure relates to the field of integrated circuits, and in particular, to a big data computing acceleration system.

Background technique

ASIC (Application Specific Integrated Circuits) is an application specific integrated circuit, which refers to an integrated circuit designed and manufactured in response to the requirements of specific users and the needs of specific electronic systems. ASIC is characterized by the needs of specific users. Compared with general integrated circuits, ASIC has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and reduced cost in mass production.

With the development of science and technology, more and more fields, such as artificial intelligence, security computing, etc., involve specific calculations with a large amount of computing. For specific operations, ASIC chips can play a role in fast operation and low power consumption. At the same time, in order to improve the processing speed and processing capability of data, it is usually necessary to control N computing chips to work at the same time for these fields with large amount of computation. With the continuous improvement of data accuracy, artificial intelligence, security computing and other fields need to operate on increasingly large data. For example, the size of photos is generally 3-7MB, but with the increase in the accuracy of digital cameras and video cameras, photos The size of the video can reach 10MB or more, and the 30-minute video may reach more than 1 GB of data. In the fields of artificial intelligence and security computing, fast computing speed and small delay are required. Therefore, how to improve computing speed and response time has always been the goal required by chip design. Since the memory matched with the ASIC chip is generally 64MB or 128MB, when the data to be processed is more than 512MB, the ASIC chip needs to use the memory to access data many times, and move the data into or out of the memory from the external storage space for many times, reducing the cost of processing speed. At the same time, with the continuous improvement of data accuracy, artificial intelligence, security computing and other fields need to operate on increasingly large data. In order to store data, it is generally necessary to configure multiple storage units for ASIC chips. For example, an ASIC chip needs to be configured with 4 storage units. 2G memory; 4N blocks of 2NG memory are required when N computing chips work at the same time. However, when multiple computing chips work at the same time, the amount of data storage will not exceed 2 G, which results in a waste of storage units and increases the system cost.

In the design of processing a large amount of related data, there are two difficulties in the prior art: 1. It is the requirement of greatly improving the performance. 2. If it is a distributed system, then the problem of data correlation should also be solved, that is, the data processed in one subsystem needs to be presented to all other subsystems for confirmation and reprocessing. Generally, there are two ways to reduce the time consumed by data processing. One is to speed up the clock for processing data logic; the other is to increase the number of concurrent blocks for processing data.

Under process constraints, the increase in clock rate is limited. Increasing the number of concurrency is a more effective way to improve performance. However, after increasing the number of concurrency, the requirements for data bandwidth are generally increased accordingly. In a general system, if the data bandwidth depends on the bandwidth provided by DDR, the bandwidth improvement of DDR is not linear. Suppose the initial system contains a set of DDR, providing 1x bandwidth. If we need to get 2x bandwidth improvement, we can achieve two sets of DDR, but if we need to get more than 16x bandwidth improvement, it is impossible to simply instantiate 16 sets of DDR in one system because of physical size constraints.

If multiple ASIC chips are required to work together, the data cannot be directly distributed in multiple disconnected systems for processing, because these data are all related, and each piece of data completed in one processing unit must be processed in other Confirmation and reprocessing are performed in the unit, so if the data transmission rate between multiple ASIC chips is increased, the problem of multi-system interconnection must also be solved.

Utility model content

The purpose of the embodiments of the present invention is to provide a way of using a high-speed interface to connect distributed storage, so as to realize concurrent processing of a large amount of related data by multiple homogeneous systems. The embodiment of the present invention provides a big data operation acceleration system, in which the chip external memory is eliminated, and the storage unit is arranged inside the ASIC chip, which reduces the time for the ASIC chip to read data from the outside, and speeds up the chip operation speed. Multiple ASIC chips share storage units, which not only reduces the number of storage units, but also reduces the connection lines between the ASIC computing chips, simplifies the system structure, and reduces the cost of the ASIC chips. At the same time, the serdes interface technology is used for data transmission between multiple computing chips, which improves the rate of data transmission between multiple ASIC chips.

To achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

The first big data computing acceleration system provided according to an embodiment of the present invention includes more than two computing chips, and the computing chips include N core cores, N data lanes (lanes) and storage units, and the data lanes ( lane) includes a sending interface (tx) and a receiving interface (rx), the core core and the data channel (lane) are in one-to-one correspondence, and the core core sends and receives data or control instructions through the data channel (lane); the operation The chip is connected through the sending interface (tx) and the receiving interface (rx), so that data or control instructions are transmitted; the storage units of the two or more computing chips are used for distributed storage of data, and the computing chip core core can be stored from The storage unit of this computing chip obtains data, and it can also obtain data from storage units of other computing chips; wherein N is a positive integer greater than or equal to 4.

Optionally, the sending interface (tx) and the receiving interface (rx) of the computing chip are serdes interfaces, and the computing chips communicate through the serdes interfaces.

Optionally, the data channel (lane) further includes a receiving address judging unit and a sending address judging unit; one end of the receiving address judging unit is connected to the receiving interface (rx), and the other end of the receiving address judging unit is connected to the kernel core; One end of the unit is connected to the sending interface (tx), the other end of the sending address judging unit is connected to the kernel core; the receiving address judging unit and the sending address judging unit are connected to each other.

Optionally, the receiving interface (rx) receives the data frame sent by the running chip on the adjacent side, sends the data frame to the receiving address judgment unit, and the receiving address judgment unit sends the data frame to the kernel core, and at the same time sends all the data frames to the core core. The data frame is sent to the sending address judging unit; the sending address judging unit receives the data frame, sends the data frame to the sending interface (tx), and the sending interface sends the data frame to the other adjacent running chip.

Optionally, the kernel core generates a data frame, sends the data frame to the sending address judgment unit, the sending address judgment unit sends the data frame to the sending interface (tx), and the sending interface (tx) sends the data frame Give the running chip on the adjacent side.

Optionally, the receiving address judging unit and the sending address judging unit are connected to each other through a first-in-first-out memory.

Optionally, the storage unit includes multiple memories, and the multiple memories are connected to at least one storage control unit; the at least one storage control unit is used to control data reading or storage of the multiple memories.

Optionally, the memory includes at least two storage subunits and a storage control subunit; the storage control subunit is connected to each of the at least one storage control unit through an interface, and the storage control subunit is used to control all the storage control subunits. data reading or storage of the at least two storage subunits.

Optionally, the storage subunit is an SRAM memory.

Optionally, the two or more computing chips are connected in a ring shape.

Optionally, the two or more computing chips are not connected to external storage units.

Optionally, the computing chip further includes a first data interface (130) connected to an external host for receiving external data or control instructions.

Optionally, the computing chip stores external data in at least one storage unit of the two or more computing chips.

Optionally, the first data interface is a UART control unit.

Optionally, the N core cores are connected to each of the at least one storage control unit; and data is read and written from the plurality of memories according to operation commands of the N core cores.

Optionally, the kernel core sends the generated data to the at least one storage control unit, the at least one storage control unit sends the data to the storage control subunit, and the storage control subunit stores the data in the storage subunit. in the unit.

Optionally, the computing chip core core obtains a data acquisition command sent by other computing chips, and the computing chip core core determines whether the data is stored in the storage unit of the computing chip through the data address, and if so, sends the command to the at least one storage control unit. a data read command; the at least one storage control unit sends a data read command to the corresponding storage control subunit, the storage control subunit acquires data from the storage subunit, and the storage control subunit sends the acquired data to at least one storage control unit, at least one storage control unit sends the acquired data to the kernel core, the kernel core sends the acquired data to a sending address judgment unit, and the sending address judgment unit sends the acquired data to a sending interface (tx), The sending interface sends the acquired data to an adjacent running chip.

Optionally, the computing chip is used to perform one or more of encryption operations and convolution calculations.

Optionally, the computing chips respectively perform independent operations, and each computing unit computes results respectively.

Optionally, the computing chips are used for performing cooperative operations, and each computing chip performs operations according to the calculation results of other computing chips.

Optionally, the at least one first data interface (130) receives an external command to initialize and configure the storage units of the two or more computing chips, and uniformly edit the storage subunits in the storage units of the two or more computing chips. site.

Optionally, the computing chip can transmit the calculation result to the outside through the at least one first data interface (130).

Optionally, the kernel core is used for data calculation and data storage control.

According to the second kind of big data operation acceleration system provided by the embodiment of the present invention, it includes more than two operation chips, and the two or more operation chips are connected in a ring; the operation chip includes a data transmission interface (tx), a data reception interface (rx) and the at least one storage unit, the data sending interface (tx) and the receiving interface (rx) are serdes interfaces, and data communication is performed between the computing chips through the serdes interfaces; each core core of the computing chip can Obtain data from the storage unit of the computing chip where it is located, and can also obtain data from the storage units of other computing chips.

According to the third kind of big data operation acceleration system provided by the embodiment of the present invention, it includes more than two operation chips, and the two or more operation chips are connected to form a ring; the operation chip includes a data transmission interface (tx), a data receiving interface The interface (rx) and the at least one storage unit, the data transmission interface (tx) and the receiving interface (rx) are serdes interfaces, and data communication is performed between the computing chips through the serdes interface; the two or more computing chips The at least one storage unit is used to store data in a distributed manner, and the computing chip does not connect an external memory unit.

The fourth big data computing acceleration system provided according to the embodiment of the present invention includes more than two computing chips, and the computing chips include N core cores, N data lanes and at least one storage unit. The channel (lane) includes a sending interface (tx) and a receiving interface (rx), the core core and the data channel (lane) are in one-to-one correspondence, and the core core sends and receives data through the data channel (lane); the two The above computing chip is connected to transmit data through the sending interface (tx) and the receiving interface (rx); the at least one storage unit is used for distributed storage of data; wherein N is a positive integer greater than or equal to 4.

In the embodiment of the present invention, multiple chips are set in the big data operation acceleration system, the multiple chips include multiple core cores, each core core performs calculation and storage control functions, and at least one core is connected to each core core inside the chip. Storage unit, so that each core can have a large-capacity memory by reading the data in the storage unit connected by itself and the storage unit connected by other computing chip cores, reducing the data from the external storage space. At the same time, since multiple cores can operate independently or cooperatively, the processing speed of data is also accelerated. Multiple ASIC chips share storage units, which not only reduces the number of storage units, but also reduces the connection lines between the ASIC computing chips, simplifies the system structure, and reduces the cost of the ASIC chips.

Description of drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are just some exemplary embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative effort.

1 illustrates a schematic diagram of the structure of a big data computing acceleration system with M ASIC chips according to the first embodiment;

FIG. 2 illustrates a schematic structural diagram of an arithmetic chip with 4 cores;

Fig. 3 illustrates the structural schematic diagram of the data channel lane;

Figure 4a illustrates a schematic diagram of the structure of the first embodiment of the memory cell

4b illustrates a schematic structural diagram of a second embodiment of a memory cell;

5 illustrates a schematic diagram of the data transmission process of the big data computing acceleration system;

6 illustrates a schematic diagram of a signal flow diagram of an arithmetic chip with four cores according to the first embodiment;

FIG. 7 illustrates a schematic diagram of a data structure according to an embodiment of the present invention.

Detailed ways

In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, numerous details are provided to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawings.

Hereinafter, the exemplary embodiments of the present invention will be described in detail based on the accompanying drawings. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and realize the present invention, but not to limit the present invention in any way. scope of utility models. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In addition, it should be noted that the directions of up, down, left, and right in the drawings are only examples of specific embodiments, and those skilled in the art can modify the components shown in the drawings according to actual needs. Some or all of the components are changed in direction to be applied without affecting the functions of each component or the system as a whole.

A multicore chip is a multiprocessing system embodied on a single LSI semiconductor chip. Typically, two or more chip cores may be embodied on a multi-core chip, interconnected by a bus (which may also be formed on the same multi-core chip). There can be from two chip cores to many chip cores embodied on the same multi-core chip die, the upper limit in the number of chip cores being limited only by manufacturing capability and performance constraints. Multi-core chips may have applications including execution in multimedia and signal processing algorithms such as video encoding/decoding, 2D/3D graphics, audio and speech processing, image processing, telephony, speech recognition and voice synthesis, encryption processing Specialized arithmetic and/or logic operations.

Although only ASIC application-specific integrated circuits are mentioned in the background art, the specific wiring implementation in the embodiments can be applied to CPUs, GPUs, FPGAs, etc. with multi-core chips. In this embodiment, the multiple cores may be the same core or different cores.

FIG. 1 is a schematic diagram illustrating the structure of a big data operation acceleration system with M ASIC chips according to the first embodiment. As shown in FIG. 1 , the big data computing acceleration system includes M ASIC computing chips, where M is a positive integer greater than or equal to 2, such as 6, 10, 12, and so on. The computing chip includes multiple cores (core0, core1, core2, core3), 4 data channels (lane0, lane1, lane2 lane3), and the data channel (lane) includes a sending interface (tx) and a receiving interface (rx) ), the core core and the data channel (lane) are in one-to-one correspondence, for example, the core core0 of the computing chip 10 has a data channel (lane0), and the data channel (lane0) has a sending interface (lane0 tx) and a receiving interface (lane0 rx), The data channel sending interface (lane0 tx) is used by the core core0 to send data or control commands to the outside of the computing chip 10, and the data channel receiving interface (lane0 rx) is used to send the external data or control commands of the computing chip 10 to the core core0 . In this way, the M computing chips are connected through the sending interface (tx) and the receiving interface (rx), so as to transmit data or control instructions. M computing chips form a closed loop. A storage unit is set in each operation chip, the four core cores in the operation chip are all connected to the storage unit, and the storage units of the M operation chips are used for distributed storage of data, and the operation chip core core can be stored from this operation chip. The storage unit of the chip obtains data, and it can also obtain data from the storage unit of other computing chips. The four core cores in the computing chip are all connected to the storage unit, and the purpose of data interaction among the four core cores in the computing chip is also realized through the storage unit. However, those skilled in the art know that four cores are selected here as an example, which is only an exemplary illustration. The number of cores may be N, where N is a positive integer greater than or equal to 4, such as 6, 10, 12, and so on. In this embodiment, the multiple cores may be the same core or different cores.

Optionally, in the system provided by this embodiment, two or more computing chips may not be connected to external storage units. The chip has a storage unit, which can be used to store data, and the chip does not need to be connected with an external storage unit, which can reduce the time for the chip to read data from the outside and speed up the operation of the chip.

The transmitting interface (lane tx) and the receiving interface (lane rx) of the data channel (lane) are serdes interfaces, and the computing chips communicate through the serdes interfaces. serdes is the abbreviation of English SERializer (serializer)/DESerializer (deserializer). It is a mainstream time division multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, the multi-channel low-speed parallel signals are converted into high-speed serial signals at the sending end, pass through the transmission medium (optical cable or copper wire), and finally the high-speed serial signals at the receiving end are re-converted into low-speed parallel signals. This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing communication costs. Of course, other communication interfaces can also be used to replace the serdes interface, such as: SSI, UATR. Data and control commands are transmitted between chips through the serdes interface.

FIG. 2 illustrates a first embodiment of a schematic structural diagram of an arithmetic chip with 4 cores. However, those skilled in the art know that four cores are selected as an example here, which is only an exemplary illustration. The number of cores of the computing chip can be N, where N is a positive integer greater than or equal to 2, for example, it can be 6, 10, 12, etc. Wait. In this embodiment, the core of the computing chip may be a core with the same function, or may be a core with different functions.

The 4-core computing chip (1) includes 4 cores (core0, core1, core2, core3), 4 data channels (lane0, lane1, lane2 lane3), at least one storage unit, and a data exchange control unit, specifically The data exchange control unit is a UART control unit, and each data channel (lane) includes a transmit interface (lane tx) and a receive interface (lane rx).

The core core0 of the computing chip (1) is connected to the sending interface (lane0 tx) and the receiving interface (lane0 rx) of the data channel, and the data channel sending interface (lane0 tx) is used for the core core0 to send to the computing chip connected to the computing chip 1 For data or control instructions, the data channel receiving interface (lane0 rx) is used to send the data or control instructions transmitted by the operation chip connected to the operation chip (1) to the core core0. Similarly, the core core1 of the computing chip 1 is connected to the sending interface (lane1 tx) and the receiving interface (lane1 rx) of the data channel; the core core2 of the computing chip 1 is connected to the sending interface (lane2 tx) and the receiving interface (lane2) of the data channel. rx), the core core3 of the computing chip 1 is connected to the transmitting interface (lane3tx) and the receiving interface (lane3rx) of the data channel. The sending interface (lane tx) and the receiving interface (lane rx) of the data channel (lane) are serdes interfaces.

A data exchange control unit is connected to the storage unit and the four core cores (core0, core1, core2, core3) through a bus, and the bus is not delineated in FIG. 2 . The data exchange control unit can be implemented using various protocols, such as UART, SPI, PCIE, SERDES, USB, etc. In this embodiment, the data exchange control unit is a UART (Universal Asynchronous Receiver/Transmitter) control unit. A universal asynchronous transceiver is usually called UART, which is an asynchronous transceiver that converts the data to be transmitted between serial communication and parallel communication. UART is usually integrated in the connection of various communication interfaces. But here is only the UART protocol as an example, and other protocols can also be used. The UART control unit accepts external data, and sends the external data to the core core (core0, core1, core2, core3) or the storage unit according to the external data address. The UART control unit can also accept external control commands and send control commands to the core core (core0, core1, core2, core3) or storage units; it can also be used for computing chips to send internal or external control commands to other computing chips, and from other chips Accept control commands, and feedback operation results or intermediate data to the outside. The internal data or internal control instructions refer to the data or control instructions generated by the chip itself, and the external data or external control instructions refer to the data or control instructions generated outside the chip, such as data or control instructions sent by an external host or an external network. instruction.

The main function of the kernel core (core0, core1, core2, core3) is to execute external or internal control instructions, perform data calculation, and data storage control and other functions. The core cores (core0, core1, core2, core3) in the computing chip are all connected to the storage unit, and data is read or written to the storage unit of the computing chip, and multiple storage units in the computing chip are realized through the storage unit. The data of the core cores can be exchanged; a control command can also be sent to the storage unit of the computing chip. The core core (core0, core1, core2, core3) writes data, reads data or sends control instructions to the storage units of other computing chips through the serdes interface according to the instructions; core core (core0, core1, core2) , core3) can also send data, read data, or send control instructions to the core cores of other computing chips through the serdes interface according to the instructions.

FIG. 3 illustrates a first embodiment of a schematic structural diagram of a data channel lane. The data channel (lane) includes a receiving interface, a sending interface, a receiving address judging unit, a sending address judging unit and a plurality of registers; one end of the receiving address judging unit is connected to the receiving interface, and the other end of the receiving address judging unit is connected to the kernel core through the register. One end of the sending address judging unit is connected to the sending interface (tx), and the other end of the sending address judging unit is connected to the kernel core through the register; the receiving address judging unit and the sending address judging unit are connected to each other through the register; the receiving address judging unit and the sending address judging unit Interconnection is also possible through first-in, first-out memory, where FIFO (first-in, first-out) is a method of processing requests for program work issued from a queue or stack, allowing the oldest requests to be processed by the most recent ones. Process first. The receiving interface receives the data frame or control command sent by the running chip on the adjacent side connected to the receiving interface, sends the data frame or control command to the receiving address judgment unit, and the receiving address judgment unit sends the data frame or control command to the kernel core, and at the same time send the data frame or control command to the sending address judgment unit; the sending address judgment unit receives the data frame or control command, sends the data frame or control command to the sending interface (tx), and sends The interface sends the data frame or control instruction to the running chip on the other side adjacent to the sending interface. The kernel core generates a data frame or control command, sends the data frame or control command to the sending address judgment unit, the sending address judgment unit sends the data frame or control command to the sending interface, and the sending interface sends the data frame or control command The command is sent to the receiving interface of the running chip on the adjacent side. The role of the register is to temporarily store data frames or control instructions.

Figure 4a illustrates a first embodiment of a schematic structural diagram of a memory cell. Each computing chip contains N core cores, which require concurrent random access to data. If the magnitude of N reaches 64 or more, the memory bandwidth of the computing chip needs to reach a very high order of magnitude, even if the GDDR (Graphics Double Data Rate, discrete graphics card) is also difficult to achieve such a high bandwidth. Therefore, in the embodiment of the present invention, a SRAM (Static Random-Access Memory, static random access memory) array and a large MUX (multiplexer, data selector) routing are used to provide high bandwidth. The system as shown in Figure 4a consists of two levels of memory control units to alleviate the congestion problem at the time of implementation. The storage unit (40) may include a plurality of memories, for example, may include 8 memories (410...417), the 8 memories (410...417) are connected to the storage control unit (420); the storage control The unit is used to control data reading or storage of the plurality of memories. The memories (410...417) include at least two storage subunits and one storage control subunit; the storage control subunit is connected to the storage control unit through an interface, and the storage control subunit is used to control the at least two storage subunits. Data reading or storage of a storage subunit. The storage subunit is an SRAM memory.

Figure 4b illustrates a second embodiment of a schematic structural diagram of a memory cell. In FIG. 4b, a plurality of storage control units (420, 421, 422, 423) may be set in the storage unit, each core core and each of the plurality of storage control units (420, 421, 422, 423) are connected, and read and write data from the plurality of memories according to the operation commands of the N core cores. Each memory control unit is connected to each memory (410...417). The structure of the memory is exactly the same as in Fig. 4a, and will not be described again here.

The kernel core sends the generated data to at least one storage control unit, and the at least one storage control unit sends the data to the storage control subunit, and the storage control subunit stores the data in the storage subunit. The computing chip core core obtains a data acquisition command sent by other computing chips, and the computing chip core core determines whether the data is stored in the storage unit of the computing chip through the data address, and if so, sends a data read command to the at least one storage control unit At least one storage control unit sends the data read command to the corresponding storage control subunit, the storage control subunit obtains data from the storage subunit, and the storage control subunit sends the obtained data to at least one storage control unit, at least one The storage control unit sends the obtained data to the kernel core, the kernel core sends the obtained data to the sending address judgment unit, the sending address judgment unit sends the obtained data to the sending interface (tx), and the sending interface sends the obtained data The data is sent to the adjacent computing chip.

The computing chip is used to perform one or more of encryption operations and convolution calculations. An exemplary detailed description follows.

The big data computing acceleration system can be applied to the field of artificial intelligence. The UART control unit of the computing chip stores the picture data or video data sent by the external host into the storage unit through the core core, and the computing chip generates the mathematical model of the neural network. The model can also be stored to the storage unit by the external host through the UART control unit, and read by each computing chip. Run the first-layer mathematical model of the neural network on the computing chip. The core core of the computing chip reads data from the storage unit of the computing chip and/or the storage unit of other computing chips to perform operations, and stores the operation results to other computing devices through the serdes interface. At least one storage unit in the storage units of the operation chip, or stored in the storage unit of the operation chip. The operation chip (1) sends a control instruction to the next operation chip (2) through the UART control unit or the serdes interface, and starts the next operation chip (2) to perform operation. The second-layer mathematical model of the neural network is run on the next computing chip (2), and the core core of the next computing chip reads data from the storage unit of this computing chip and/or the storage unit of other computing chips to perform operations, and calculates the result of the operation. It is stored to at least one storage unit in the storage units of other computing chips through the serdes interface, or is stored to the storage unit of this computing chip. Each chip executes a layer in the neural network, obtains data from the storage unit of other computing chips or the storage unit of this computing chip through the serdes interface, and calculates the operation result only at the last layer of the neural network. The operation chip obtains the operation result from the local storage unit or the storage unit of other operation chips, and feeds it back to the external host through the UART control unit.

The big data operation acceleration system can be applied to the "digital certificate" field. The UART control unit of the operation chip (1) stores the block information sent by the external host in at least one storage unit among the multiple storage units of the multiple operation chips. The host sends control commands to the M arithmetic chips to perform data operations through the arithmetic chip (1... The instruction performs data operation, and the operation chip (1) sends control instructions to the other M-1 operation chips to perform data operation in turn, and the M operation chips start the operation operation. The external host can also send control instructions to one operation chip (1) UART control unit. The instruction performs data operation, the first operation chip (1) sends a control instruction to the second operation chip (2) to perform data operation, the second operation chip (2) sends a control instruction to the third operation chip (3) to perform data operation, and the first operation chip (2) sends a control instruction to the third operation chip (3) to perform data operation. Three arithmetic chips (3) send control instructions to the fourth arithmetic chip (4) to perform data operations, and M arithmetic chips start arithmetic operations. M arithmetic chips pass through the serdes interface from the storage unit of other arithmetic chips or the storage unit of this arithmetic chip The data is acquired to perform operations, the M arithmetic chips simultaneously perform the workload proof operation, and the arithmetic chip (1) acquires the operation result from the storage unit, and feeds it back to the external host through the UART control unit.

FIG. 5 illustrates a first embodiment of a schematic diagram of a data transmission process of the big data computing acceleration system. The computing chips are used for performing cooperative operations, and each computing chip performs operations according to the calculation results of other computing chips. For example, a total of N computing chips are included in the system, and each computing chip completes 1/n work. After each computing chip completes the data it is responsible for, because of the data correlation, the result of its calculation must be transmitted to all other computers. chip. The computing chip n-1 is the source computing chip of the data frame, and the data is sent to the computing chip 0 through the lane0 tx; in the computing chip 0, the data frame will be divided into two channels, and the first channel is sent to the core core of the computing chip 0 , the outer channel is forwarded to the lane0 tx channel of the computing chip 0, so the data frame will be sent to the computing chip 1.

Source ID mechanism: Each data frame carries the computing chip ID of the source of the data frame. Whenever the data frame is sent to a new computing chip, the computing chip will detect the computing chip ID in the data frame. When it is found that the ID of the computing chip is equal to the ID of the next computing chip connected to the computing chip, then the data frame will not be forwarded again, which means that the life cycle of the data frame is terminated here, and neither Take up bandwidth. The operation chip will detect the operation chip ID in the data frame, either in the core core or in the receiving address judgment unit.

FIG. 6 illustrates a schematic diagram of a signal flow of an arithmetic chip with four cores according to the first embodiment.

The computing chip further includes a first data interface (130) connected to an external host for receiving external data or control instructions. The computing chip stores external data in at least one storage unit of the two or more computing chips. The first data interface may be a UART control unit.

The UART control unit (130) is used for acquiring external data or control instructions of the chip, and transmitting the external data or control instructions to the core core (110) connected to the UART control unit. The kernel core (110) transmits the external data to the storage unit (120) of the chip according to the data address for storage, or the kernel core (110) sends the data to other chip kernel cores corresponding to the data address through the signal channel lane according to the data address, Other chip cores store data in local storage units. The core core ( 110 ) is executed by the core core of the operation chip according to the address of the external control instruction or sent to the core core of other chips corresponding to the address of the control instruction through the signal channel lane for execution. If the core core of the computing chip needs to obtain data, the core core can obtain data from a local storage unit, or obtain data from storage units of other computing chips. When acquiring data from the storage units of other computing chips, the kernel core (110) broadcasts the acquired data control instruction to the connected computing chip through the serdes interface (150) connected to itself; the connected computing chip will acquire the data The control instructions are divided into two paths, one is sent to the core core, and the other is forwarded to the next chip. If the connected computing chip determines that the data is stored in the local storage unit, the core core reads the data from the storage unit and sends it to the computing unit that issues the data acquisition control instruction through the serdes interface. Of course, the control commands between the computing chips can also be sent through the UART control unit. When the core core feeds back the operation result or intermediate data to the outside according to the external control instruction or internal control instruction, the core core obtains the operation result or intermediate data from the storage unit of this operation chip or from the storage unit of other operation chips through the serdes interface, and transfers the operation result or intermediate data to the operation chip. The result or the intermediate data is sent to the outside through the first data interface (130), and when the first data interface is the UART control unit, the operation result or the intermediate data is sent to the outside through the UART control unit. The external mentioned here may refer to an external host, an external network, or an external platform.

The at least one first data interface (130) receives an external instruction to initialize and configure the storage units of the two or more computing chips, and uniformly addresses the storage subunits in the storage units of the two or more computing chips. If the first data interface (130) is a UART control unit, the external host can initialize and configure parameters of the storage unit through the UART control unit, and perform unified addressing of multiple storage units.

Of course, the kernel core performs calculations based on the acquired data, and stores the calculation results in the storage unit. Each storage unit is provided with a dedicated storage area and a shared storage area; the dedicated storage area is used to store a temporary operation result of an operation chip, and the temporary operation result is an intermediate calculation result that the one operation chip continues to use, and Intermediate calculation results not used by other computing chips; the shared storage area is used to store the computing data results of the computing chips, and the computing data results are used by other computing chips or need to be fed back and transmitted to the outside.

In the embodiment of the present invention, a plurality of core cores are set in the chip, each core core performs operation and storage control functions, and at least one storage unit is connected to each core core inside the chip, so that each core is connected by reading its own The storage unit connected to other cores allows each core to have large-capacity memory, reducing the number of times data is moved into or out of memory from external storage space, and speeding up data processing; at the same time, since multiple cores can They operate independently or cooperatively, which also speeds up data processing.

FIG. 7 illustrates a schematic diagram of a data structure according to an embodiment of the present invention. The data referred to here are various data such as command data, numerical data, and character data. The data format specifically includes valid bits valid, destination address dst id, source address src id, and data data. The kernel can judge whether the data packet is a command or a value through the valid bit, where 0 can be assumed to represent a value, and 1 can be a command. The kernel will determine the destination address, source address and data type according to the data structure. For example, in Figure 1, the kernel 50 sends a data read command to the kernel 10, the valid bit is 1, the destination address is the address of the kernel 10, the source address is the address of the kernel 50, and the data data is the read data command and data type. Or data address, etc. When the core 10 sends data to the core 10, the valid bit is 0, the destination address is the address of the core 50, the source address is the address of the core 0, and the data data is the read data. In terms of the instruction running sequence, the present embodiment adopts a traditional six-stage pipeline structure, which are respectively instruction fetching, decoding, execution, memory fetching, alignment and write-back stages. From the perspective of instruction set architecture, a reduced instruction set architecture can be adopted. According to the general design method of the simplified instruction set architecture, the instruction set of the utility model can be divided into register-register type instruction, register-immediate number instruction, jump instruction, memory access instruction, control instruction and inter-core communication instruction according to functions.

As an example, the system provided in this embodiment can perform data processing related to digital vouchers, and the digital vouchers can be obtained through data processing.

Using the descriptions provided herein, embodiments can be implemented into a machine, process, or article of manufacture using standard programming and/or engineering techniques to produce programmed software, firmware, hardware, or any combination thereof.

Any generated program(s) (with computer-readable program code) may be embodied on one or more computer-usable media, such as resident storage devices, smart cards or other removable storage devices, or transfer devices, Computer program products and articles of manufacture are thereby made according to the embodiments. As such, the terms "article of manufacture" and "computer program product" as used herein are intended to encompass a computer program that exists permanently or temporarily on any computer-usable non-transitory medium.

As noted above, memory/storage devices include, but are not limited to, magnetic disks, optical disks, removable storage devices (such as smart cards, subscriber identity modules (SIM), wireless identity modules (WIM)), semiconductor memory (such as random access memory ( RAM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), etc. Transmission media include, but are not limited to, transmission via wireless communication networks, the Internet, intranets, telephone/modem based network communications, hardwired/cable communication networks, satellite communications, and other fixed or mobile network systems/communication links.

Although specific example embodiments have been disclosed, it will be understood by those skilled in the art that changes can be made in the specific example embodiments without departing from the spirit and scope of the invention.

The present invention has been described above based on the embodiments with reference to the accompanying drawings. However, the present invention is not limited to the above-mentioned embodiments. Parts of each embodiment and each modification are appropriately combined or replaced according to layout requirements. Included in the scope of the present invention. In addition, based on the knowledge of those skilled in the art, the combination and processing order of each embodiment may be appropriately reorganized, or various modifications such as various design changes may be added to each embodiment, and embodiments to which such modifications are applied may also be included in the present application. new range.

While this disclosure has described various concepts in detail, those skilled in the art will appreciate that various modifications and substitutions to those concepts can be implemented within the spirit of the overall teachings of this disclosure. Those skilled in the art, using ordinary skill, can implement the invention as set forth in the claims without undue experimentation. It is to be understood that the specific concepts disclosed are illustrative only and are not intended to limit the scope of the invention, which is to be determined by the appended claims along with their full scope of equivalents.

Claims (26)

1. a kind of big data operation acceleration system, which is characterized in that including 2 or more operation chips, the operation chip includes N A kernel core, N number of data channel (lane) and at least one storage unit, the data channel (lane) includes transmission interface (tx) it is corresponded with receiving interface (rx), the kernel core and data channel (lane), the kernel core passes through data (lane) sends and receives data in channel；Described 2 or more operation chips are by the transmission interface (tx) and described connect Mouth (rx) is attached transmission data；At least one described storage unit is used for distributed storage data, each of operation chip Kernel core can obtain data from the storage unit of place operation chip, can also obtain from the storage unit of other operation chips Access evidence；Wherein N is the positive integer more than or equal to 4.

2. system according to claim 1, which is characterized in that the transmission interface (tx) of the operation chip and described Receiving interface (rx) is serdes interface, is communicated between the operation chip by serdes interface.

3. system according to claim 1 or 2, which is characterized in that the data channel (lane) further comprises receiving Address judging unit sends address judging unit；It receives address judging unit one end to be connected to receiving interface (rx), receives address The judging unit other end is connected to kernel core；It sends address judging unit one end to be connected to transmission interface (tx), sends address The judging unit other end is connected to kernel core；It receives address judging unit and sends address judging unit and be connected with each other.

4. system according to claim 3, which is characterized in that receiving interface (rx) receives adjacent side operation chip and sends Data frame, by the data frame be sent to receive address judging unit, receive address judging unit the data frame is sent Kernel core is given, while the data frame being sent to and sends address judging unit；It sends address judging unit and receives the number According to frame, the data frame is sent to transmission interface (tx), the data frame is sent to the adjacent other side and run by transmission interface Chip.

5. system according to claim 3, which is characterized in that kernel core generates data frame, and the data frame is sent To address judging unit is sent, address judging unit is sent by the data frame and is sent to transmission interface (tx), transmission interface (tx) data frame is sent to the operation chip of adjacent side.

6. system according to claim 3, which is characterized in that the reception address judging unit and the judgement of transmission address are single Member is connected with each other by push-up storage.

7. system according to claim 1 or 2, which is characterized in that the storage unit includes multiple memories, described more A memory is connected at least one storage control unit；At least one described storage control unit is for controlling the multiple deposit The reading data or storage of reservoir.

8. system according to claim 7, which is characterized in that the memory includes at least two storing sub-units and deposits Storage control subelement；Storage control subelement passes through each of interface and at least one storage control unit and connect, The storage control subelement is used to control the reading data or storage of at least two storing sub-units.

9. system according to claim 8, which is characterized in that the storing sub-units are SRAM memory.

10. system according to claim 1 or 2, which is characterized in that described 2 or more operation chip connections circularize.

11. system according to claim 1 or 2, which is characterized in that described 2 or more operation chips are not connected to outside and deposit Storage unit.

12. system according to claim 1 or 2, which is characterized in that the operation chip further comprises that the first data connect Mouth (130) is connected with external host, for receiving external data or control instruction.

13. system according to claim 12, which is characterized in that the operation chip is by external data storage to described 2 At least one storage unit of a above operation chip.

14. system according to claim 12, which is characterized in that first data-interface is UART control unit.

15. system according to claim 8, which is characterized in that N number of kernel core and at least one described storage control Each of unit processed is connected；According to the operational order of N number of kernel core, number is read and write from the multiple memory According to.

16. system according to claim 15, which is characterized in that kernel core by the data of generation be sent to it is described at least One storage control unit, at least one described storage control unit sends the data to the storage control subelement, described Storage control subelement stores data into storing sub-units.

17. system according to claim 16, which is characterized in that operation chip core core obtains other operation chips hair The acquisition data command sent, operation chip core core judge whether data are stored in depositing for this operation chip by data address In storage unit, and if so, sending data read command at least one described storage control unit；It is described at least one deposit Data read command is sent to corresponding storage and controls subelement by storage control unit, and storage controls subelement from storing sub-units Data are obtained, the acquisition data are sent at least one storage control unit by storage control subelement, at least one storage The acquisition data are sent to kernel core by control unit, and the acquisition data are sent to by kernel core sends address judgement Unit sends address judging unit and is sent to the acquisition data transmission interface (tx), and transmission interface is by the acquisition data It is sent to adjacent operation chip.

18. system according to claim 1 or 2, which is characterized in that the operation chip is rolled up for executing cryptographic calculation One or more of product calculating.

19. system according to claim 18, which is characterized in that the operation chip executes independent operation respectively, often A computing unit calculates separately result.

20. system according to claim 18, which is characterized in that the operation chip is for executing collaboration operation, each Operation chip carries out operation according to the calculated result of other operation chips.

21. system according to claim 12, which is characterized in that at least one described first data-interface (130) receives The storage unit of 2 or more operation chips described in external command initial configuration, to the storage list of described 2 or more operation chips Storing sub-units in member carry out unified addressing.

22. system according to claim 12, which is characterized in that the operation chip can by it is described at least one first Data-interface (130) outward transmits calculated result.

23. system according to claim 1 or 2, which is characterized in that the kernel core is calculated for data, and data are deposited Storage control.

24. a kind of big data operation acceleration system, which is characterized in that including 2 or more operation chips, described 2 or more operations Chip connection circularizes；The operation chip includes data transmission interface (tx), data receiver interface (rx) and described at least one A storage unit, the data transmission interface (tx) and receiving interface (rx) are serdes interface, are led between the operation chip It crosses serdes interface and carries out data communication；Each kernel core of operation chip can be obtained from the storage unit of place operation chip Access evidence also can obtain data from the storage unit of other operation chips.

25. a kind of big data operation acceleration system, which is characterized in that including 2 or more operation chips, described 2 or more operations Chip signal connection circularizes；The operation chip include data transmission interface (tx), data receiver interface (rx) and it is described extremely A few storage unit, the data transmission interface (tx) and receiving interface (rx) are serdes interface, the operation chip it Between by serdes interface carry out data communication；At least one described storage unit of described 2 or more operation chips is for dividing Cloth storing data, the not external internal storage location of operation chip.

26. a kind of big data operation acceleration system, which is characterized in that including 2 or more operation chips, the operation chip includes N number of kernel core, N number of data channel (lane) and at least one storage unit, the data channel (lane) include sending to connect Mouth (tx) and receiving interface (rx), the kernel core and data channel (lane) correspond, and the kernel core passes through number Data are sent and received according to channel (lane)；Described 2 or more operation chips pass through the transmission interface (tx) and the reception Interface (rx) is attached transmission data；At least one described storage unit is used for distributed storage data；Wherein N be greater than etc. In 4 positive integer.