CN209072364U - A kind of synchronous rectification control chip and circuit - Google Patents

Abstract

A kind of synchronous rectification control chip and circuit, including the first linear Voltage stabilizing module, the second linear voltage stabilization module, the first signal judgment module and bias voltage module.Pass through the strong driving capability using NMOS tube, in the first linear Voltage stabilizing module and the second linear voltage stabilization module using NMOS tube as adjustment pipe, first control signal and second control signal are issued respectively according to the first comparing unit and the second comparing unit, control the working condition of first capacitor bias unit and the second capacitor bias unit, to the on-off of control the first NMOS tube and the second NMOS tube, the final power supply self-powered for realizing synchronous rectification control chip, solve conventional solution it is existing due to using junction field effect transistor as adjustment pipe caused by rely on complexity junction field effect transistor production technology, waste chip area, or lead to waste pcb board area due to adding auxiliary circuit in the peripheral circuit of synchronous rectification control chip, the problem of complex circuit designs.

Description

A kind of synchronous rectification control chip and circuit

Technical field

The utility model belongs to switch power technology field more particularly to a kind of synchronous rectification control chip and circuit.

Background technique

Currently, traditional synchronous rectification control chip is to obtain suitable driving voltage, two methods are generallyd use: method 1 (please referring to Fig. 1) is the linear voltage-stabilizing circuit of chip interior using junction field effect transistor conduct adjustment pipe, however, due to The production of junction field effect transistor is complicated, relies on the production of high-pressure process method, and junction field effect transistor exports electric current Ability is smaller, and needing to occupy biggish chip area can be only achieved ideal voltage supply effect；Method 2 (please referring to Fig. 8) is Increase the auxiliary circuit being made of auxiliary winding, diode and current-limiting resistance in the peripheral circuit of synchronous rectification control chip, To provide extra work voltage to synchronous rectification control chip, however, pcb board area, and electricity can be wasted by adding auxiliary circuit Road design is complicated.

Therefore, traditional synchronous rectification control chip exists due to electric as linear voltage stabilization using junction field effect transistor Complicated technology production, waste chip area are relied on caused by adjustment pipe in road or lead to wave due to adding auxiliary circuit The problem of taking pcb board area, complex circuit designs.

Summary of the invention

In view of this, the utility model embodiment provides a kind of synchronous rectification control chip and circuit, it is intended to solve to pass The synchronous rectification control chip of system is existing due to using junction field effect transistor as the adjustment pipe in linear voltage-stabilizing circuit Caused by rely on complicated technology production, waste chip area, or due to add auxiliary circuit and cause waste pcb board face The problem of product, complex circuit designs.

The first aspect of the utility model embodiment provides a kind of synchronous rectification control chip, comprising:

For pulse signal to be converted to the first linear Voltage stabilizing module of first target voltage；

It is connect with the first linear regulator module, for voltage signal to be converted to the second line of the second target voltage Property Voltage stabilizing module；

It is connect with the described first linear Voltage stabilizing module and the second linear voltage stabilization module, for judging the pulse letter Number level height after, output judges the first signal judgment module of signal；And

It is connect with the described first linear Voltage stabilizing module and the second linear voltage stabilization module, for providing bias voltage Bias voltage module；

Wherein, the described first linear Voltage stabilizing module includes:

Realize the output of pulse signal to be described for receiving the pulse signal, and by the on off operating mode of itself First NMOS tube of first target voltage；

It is connect with the grid of first NMOS tube, the first capacitor of the on off operating mode for controlling first NMOS tube Bias unit；And

It is connect with the first capacitor bias unit, for comparing the first reference voltage and sampled voltage, and according to comparing As a result and the judgement signal accordingly exports first control signal, to control the working condition of the first capacitor bias unit The first comparing unit.

The second linear voltage stabilization module includes:

Realize that by voltage signal output be second for receiving the voltage signal, and by the on off operating mode of itself Second NMOS tube of target voltage；

It is connect with the grid of second NMOS tube, the second capacitor of the on off operating mode for controlling second NMOS tube Bias unit；And

It is connect with the second capacitor bias unit, for comparing the second reference voltage and sampled voltage, and according to comparing As a result and the judgement signal accordingly exports second control signal, to control the working condition of the second capacitor bias unit The second comparing unit.

The second aspect of the utility model embodiment provides a kind of synchronous commutating control circuit, including it is above-mentioned synchronize it is whole Flow control chip, further includes:

First end connection load, the vice-side winding of the pulse signal for receiving primary side winding transmitting；With

Drain electrode is connect with the second end of the vice-side winding, and source electrode ground connection, grid connects the driving pin, is used for basis The driving signal carries out on-off, to realize the third NMOS tube for synchronizing rectification to the pulse signal；Wherein

The drain pin connects the drain electrode of the third NMOS tube, and the source electrode pin connects the third NMOS tube Source electrode, the signal pin ground connection.

The third aspect of the utility model embodiment provides a kind of synchronous commutating control circuit, including it is above-mentioned synchronize it is whole Flow control chip, further includes:

First end connection load, the vice-side winding of the pulse signal for receiving primary side winding transmitting；With

Drain electrode is connect with the second end of the vice-side winding, and source electrode ground connection, grid connects the driving pin, is used for basis The driving signal carries out on-off, to realize the third NMOS tube for synchronizing rectification to the pulse signal；Wherein

The drain pin connects the drain electrode of the third NMOS tube, and the source electrode pin connects the third NMOS tube Source electrode, the signal pin connect the drain electrode of the third NMOS tube.

The fourth aspect of the utility model embodiment provides a kind of synchronous commutating control circuit, including it is above-mentioned synchronize it is whole Flow control chip, further includes:

First end connection load, the vice-side winding of the pulse signal for receiving primary side winding transmitting；With

Drain electrode is connect with the second end of the vice-side winding, and source electrode ground connection, grid connects the driving pin, is used for basis The driving signal carries out on-off, to realize the third NMOS tube for synchronizing rectification to the pulse signal；Wherein

The drain pin connects the drain electrode of the third NMOS tube, and the source electrode pin connects the third NMOS tube Source electrode, the signal pin connect the first end of the vice-side winding.

Above-mentioned synchronous rectification control chip and circuit, first issued according to the first comparing unit and the second comparing unit The working condition of signal and second control signal control first capacitor unit and the second capacitor cell is controlled, thus control first The on-off of NMOS tube and the second NMOS tube realizes power supply self-powered.It is linear first by the strong driving capability using NMOS tube Voltage stabilizing module and the second linear voltage stabilization module are managed using NMOS tube as adjustment, instead of the junction type in traditional technical solution Field effect transistor, it is not necessary to rely on the complicated technology of production junction field effect transistor, save chip area；And without going through increasing Add peripheral auxiliary circuits to realize power supply, saves pcb board area, simplifies circuit design.

Detailed description of the invention

It, below will be to embodiment or the prior art in order to illustrate more clearly of the technical scheme in the embodiment of the utility model Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only that this is practical new Some embodiments of type for those of ordinary skill in the art without any creative labor, can be with It obtains other drawings based on these drawings.

Fig. 1 is the linear voltage-stabilizing circuit schematic diagram that traditional synchronous rectification controls chip interior；

Fig. 2 is the internal structure block diagram that the synchronous rectification that an embodiment of the present invention provides controls chip；

Fig. 3 is the circuit diagram for the first linear Voltage stabilizing module that synchronous rectification shown in Fig. 2 controls chip；

Fig. 4 is the circuit diagram for the second linear voltage stabilization module that synchronous rectification shown in Fig. 2 controls chip；

Fig. 5 is the circuit diagram that synchronous rectification shown in Fig. 2 controls chip interior；

Fig. 6 is bias voltage V2=0, power supply self-powered situation schematic diagram when V3=Vcc, signal pin HVIN are grounded；

Fig. 7 is bias voltage V2=0, and V3=Vcc, signal pin HVIN connect the power supply self-powered and power supply when direct current signal The adaptive switched situation schematic diagram of target voltage；

Fig. 8 is traditional synchronous commutating control circuit structural schematic diagram；

Fig. 9 is the synchronous commutating control circuit structure under low driving voltage situation that an embodiment of the present invention provides Schematic diagram；

Figure 10 is the synchronous commutating control circuit knot under high driving voltage situation that an embodiment of the present invention provides Structure schematic diagram；

Figure 11 is the synchronous rectification control under another high driving voltage situation that an embodiment of the present invention provides Electrical block diagram.

Specific embodiment

In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain The utility model is not used to limit the utility model.

Referring to Fig. 2, controlling the internal structure block diagram of chip for the synchronous rectification that an embodiment of the present invention provides, it is Convenient for explanation, only the parts related to this embodiment are shown, details are as follows:

A kind of synchronous rectification control chip, comprising: the first linear Voltage stabilizing module 10, the second linear voltage stabilization module 20, first Signal judgment module 30 and bias voltage module 40.

First linear Voltage stabilizing module 10 is used to pulse signal Vd being converted to first target voltage VCC1.

Second linear voltage stabilization module 20 is connect with first linear regulator module 10, for voltage signal to be converted to second Target voltage VCC2.

First signal judgment module 30 is connect with the first linear Voltage stabilizing module 10 and the second linear voltage stabilization module 20, is used for Judge the level height of pulse signal Vd, and exports and judge signal Vp.Judge signal Vp for level signal, occurrence be 0 or Person 1.

Bias voltage module 40 is connect with the first linear 10 and 20 second linear voltage stabilization module 20 of Voltage stabilizing module, for mentioning For bias voltage.In a particular application, there are three end, first end output voltage V1, second end output electricity for bias voltage module 40 Press V2, third end output voltage V3.

First linear Voltage stabilizing module 10 includes: that the first NMOS tube N1, first capacitor bias unit 11 and first are relatively more single Member 12.

First NMOS tube N1 is used for return pulse signal Vd, and by the on off operating mode of itself realization that pulse signal Vd is defeated It is out first target voltage VCC1.

First capacitor bias unit 11 is connect with the grid of the first NMOS tube N1, for controlling the on-off of the first NMOS tube N1 State.

First comparing unit 12 is connect with first capacitor bias unit 11, for comparing the first reference voltage Vref1 and adopting Sample voltage vcc _ div, and according to comparison result and judge that signal Vp accordingly exports first control signal s1, with the first electricity of control Hold the working condition of bias unit 11.The comparison result OUT1 table of first reference voltage Vref1 and sampled voltage Vcc_div Show, the occurrence of OUT1 is 0 or 1.

Second linear voltage stabilization module includes: the second NMOS tube N2, the second capacitor bias unit 21 and the second comparing unit 22。

Second NMOS tube N2 is realized by the on off operating mode of itself for receiving voltage signal and is by voltage signal output Second target voltage VCC2.

Second capacitor bias unit 21 is connect with the grid of the second NMOS tube N2, for controlling the on-off of the second NMOS tube N2 State.

Second comparing unit 22 is connect with the second capacitor bias unit 21, for comparing the second reference voltage Vref2 and adopting Sample voltage vcc _ div, and according to comparison result and judge that signal Vp accordingly exports second control signal s2, with the second electricity of control Hold the working condition of bias unit 21.The comparison result OUT2 table of second reference voltage Vref2 and sampled voltage Vcc_div Show, the occurrence of OUT2 is 0 or 1.

Synchronous rectification control chip provided by the embodiment of the utility model utilizes the strong driving capability of NMOS tube, in inside First linear Voltage stabilizing module 10 and the second linear voltage stabilization module 20 are managed using the first and second NMOS tube as adjustment, are replaced Special process device junction field effect transistor in traditional technical solution, saves chip area, and reduce to work The dependence of skill.

Synchronous rectification provided by the embodiment of the utility model controls chip, respectively according to the first comparing unit 12 and the second ratio First capacitor unit is controlled compared with the control signal (respectively first control signal s1 and second control signal s2) that unit 22 issues 11 and second capacitor cell 12 working condition, thus control the first NMOS tube N1 and the second NMOS tube N2 on-off, then by The on off operating mode of first NMOS tube N1 and the second NMOS tube N2 realize power supply self-powered；It in practical applications, can be according to different Using needs, by signal pin HVIN different connection types so that actual driving voltage Vcc is eventually equal to different mesh It marks voltage (first target voltage VCC1 or the second target voltage VCC2), that is, it is adaptive switched to realize power supply target voltage.

Above-mentioned synchronous rectification control chip further includes driving pin VG, power pin VCC, drain pin VD, source electrode pin VS and signal pin HVIN.Wherein driving pin VG is connect with external system, and external system is driven for output drive signal System.The drain electrode of drain pin VD the first NMOS tube of connection N1 is used for input pulse signal Vd.Signal pin HVIN connection second The drain electrode of NMOS tube N2 is used for input voltage signal.

In one embodiment, above-mentioned synchronous rectification control chip further include first diode D1, the second diode D2, First resistor R1 and second resistance R2.The anode of the first diode D1 connects the source electrode of first NMOS tube, cathode Connect the power pin；The anode of the second diode D2 connects the source electrode of the second NMOS tube N2, and cathode connects institute State power pin；The first end of the first resistor connects the cathode of the first diode D1, second end connection described second The first end of resistance, the second end ground connection of the second resistance；The sampling end of first comparing unit and second ratio Compared with the second end that the sampling end of unit connects the first resistor jointly.

Referring to Fig. 3, in one embodiment, first capacitor bias unit 11 include first switch 1, second switch 2, Third switch 3 and first capacitor C1.

Wherein, the first end of the first end connection first switch 1 of bias voltage module 40, the second end of first switch 1 connect The grid of the first NMOS tube N1 is connect, the second end of bias voltage module 40 connects the first end of second switch 2, second switch 2 Second end connects the first end of first capacitor C1, and the second end of first capacitor C1 connects the grid of the first NMOS tube N1, biased electrical The first end of the third end connection third switch 3 of die block 40, the first of the second end connection first capacitor C1 of third switch 3 End.

Referring to Fig. 4, in one embodiment, the second capacitor bias unit 21 include the 4th switch 4, the 5th switch 5, 6th switch 6 and the second capacitor C2.

Wherein, the first end of bias voltage module 40 connects the first end of the 4th switch 4, and the second end of the 4th switch 4 connects The grid of the second NMOS tube N2 is connect, the second end of bias voltage module 40 connects the first end of the 5th switch 5, the 5th switch 5 Second end connects the first end of the second capacitor C2, and the second end of the second capacitor C2 connects the grid of the second NMOS tube N2, biased electrical The third end of die block 40 connects the first end of the 6th switch 6, and the second end of the 6th switch 6 connects the first of the second capacitor C2 End.

Referring to Fig. 3, in one embodiment, the first comparing unit 12 include first with door S1, the first phase inverter with And first comparator COMP1.The normal phase input end of first comparator COMP1 is the sampling end of the first comparing unit 12, sampling end For input sample resistance Vcc_div, the inverting input terminal of first comparator COMP1 is the input of the first reference voltage Vref1 End, first comparator for compare the first reference voltage Vref1 and sampled voltage Vcc_div and by comparison result OUT1 export to First phase inverter；The output end of first comparator COMP1 connects the first phase inverter, the output end connection first of the first phase inverter with The first input end of door S1, the second input terminal of the output end connection first and door S1 of the first signal judgment module 30, first is anti- Phase device is used to reversely exporting OUT1 into the first input end to first and door S1 afterwards.The output end and first capacitor of first and door S1 Bias unit 11 connects, and is configured as output first control signal s1.

The output of first signal judgment module 30 judge signal Vp occurrence for the occurrence of 0 perhaps 1 OUT1 be 0 or 1, the first phase inverter reversely exports OUT1 afterwards, corresponding first exported of the first signal for being inputted to door S1 according to two input terminals Control signal s1.Wherein, the logical relation of Vp, OUT1, the signal of the first phase inverter output and s1 are as follows:

Vp	OUT1	The signal of first phase inverter output	s1
				1	1	0	0
1	0	1	1
				0	1	0	0
0	0	1	0

Referring to Fig. 4, in one embodiment, the second comparing unit 22 include second with door S2, the second phase inverter with And the second comparator COMP2.The normal phase input end of second comparator COMP2 is the sampling end of the second comparing unit 22, sampling end For input sample resistance Vcc_div, the inverting input terminal of the second comparator COMP2 is the input of the second reference voltage Vref2 End, the second comparator for compare the second reference voltage Vref2 and sampled voltage Vcc_div and by comparison result OUT2 export to Second phase inverter；The output end of second comparator COMP2 connects the second phase inverter, the output end connection second of the second phase inverter with The first input end of door S2, the second phase inverter are used to reversely exporting OUT2 into the first input end to second and door S2 afterwards.First The second input terminal of the output end connection second and door S2 of signal judgment module 30；The output end and the second capacitor of second and door S2 Bias unit 21 connects, and is configured as output second control signal s2.

The output of first signal judgment module 30 judge signal Vp occurrence for the occurrence of 0 perhaps 1 OUT2 be 0 or 1, the second phase inverter reversely exports OUT2 afterwards, corresponding second exported of the second signal for being inputted to door S2 according to two input terminals Control signal s2.Wherein, the logical relation of Vp, OUT2, the signal of the second phase inverter output and s2 are as follows:

Referring to Fig. 5, controlling the circuit diagram of chip interior for synchronous rectification.It is provided by the embodiment of the utility model same Step rectification control chip includes bias voltage module 40, the first NMOS tube N1, the second NMOS tube N2, first switch 1, second switch 2, third switch 3, the 4th switch 4, the 5th switch 5, the 6th switch 6, first capacitor C1, the second capacitor C2, first diode D1, Second diode D2, first and door S1, second are sentenced with door S2, first comparator COMP1, the second comparator COMP2, the first signal Disconnected module 30, first resistor R1 and second resistance R2.

Wherein, the drain electrode of the first NMOS tube N1 connects drain pin VD, the drain electrode connection signal pin of the second NMOS tube N2 The cathode of HVIN, the cathode of first diode D1 and the second diode D2 connect power pin VCC jointly.

The first end of bias voltage module 40 connects altogether with the first end of first switch 1 and the first end of the 4th switch 4, the The second end of one switch 1 connects the grid of the first NMOS tube N1, and the second end of the 4th switch 4 connects the grid of the second NMOS tube N2 Pole, the first end of the second end connection second switch 2 of bias voltage module 40 and the first end of the 5th switch 5, second switch 2 Second end connects the first end of first capacitor C1, and the second end of first capacitor C1 connects the grid of the first NMOS tube N1, and the 5th opens The first end of 5 the second capacitor C2 of second end connection is closed, the second end of the second capacitor C2 connects the grid of the second NMOS tube N2, partially Set voltage module 40 third end connection third switch 3 first end and the 6th switch 6 first end, the second of third switch 3 The first end of end connection first capacitor C1, the second end of the 6th switch 6 connect the first end of the second capacitor C2.

The anode of the source electrode connection first diode D1 of first NMOS tube N1, the first electricity of cathode connection of first diode D1 Hinder the first end of R1, the positive input terminal and the second comparator COMP2 of the second end connection first comparator COMP1 of first resistor R1 Positive input terminal, the second end of the first end connection first resistor R1 of second resistance R2, the second end ground connection of second resistance R2, the The negative input end of one comparator COMP1 inputs the negative input end input the of the first reference voltage Vref1, the second comparator COMP2 The output end of two reference voltage Vref2, first comparator COMP1 carry out the level signal of output anti-by the first phase inverter Input first and the first input end of door S1 backward, the output end of the second comparator COMP2 is by the level signal of output, by the Two phase inverters carry out it is reversed after, the first input end of input second and door S2, the input terminal of the first signal judgment module 30 and the The drain electrode of one NMOS tube N1 connect altogether and connect synchronous rectification control chip drain pin VD, the first signal judgment module 30 it is defeated Outlet connects with the second input terminal of door S1 and second with the second input terminal of door S2 altogether with first.

Power supply self-powered and power supply target voltage are realized the following detailed description of the synchronous rectification control chip of the utility model Adaptive switched process.

The drain electrode of drain pin VD input pulse signal Vd to the first NMOS tube N1, signal pin HVIN input voltage signal To the drain electrode of the second NMOS tube N2, the voltage signal of input can be adjusted by signal pin HVIN from external different connection types Whole, voltage signal can be 0, pulse signal Vd or DC signal.

When the drain electrode of drain pin VD input pulse signal Vd to the first NMOS tube N1, signal pin HVIN input voltage are believed When number being 0, finally obtained actual driving voltage Vcc is low driving voltage VL, and VL is equal to first target voltage VCC1, the One linear voltage stabilization module 10 keeps power supply, and the second linear voltage stabilization module 20 is not powered.As drain pin VD input pulse signal Vd The voltage signal for being input to the drain electrode of the second NMOS tube N2 to the drain electrode of the first NMOS tube N1, signal pin HVIN is pulse signal Vd or when direct current signal, finally obtained actual driving voltage Vcc is high driving voltage VH, and VH will be equal to the second target electricity VCC2 is pressed, under steady-state working condition, the first linear Voltage stabilizing module 10 is not powered, the power supply of the second linear voltage stabilization module 20.

Synchronous rectification control chip provided by the embodiment of the utility model includes two LDO (Low Dropout Regulator, low pressure difference linear voltage regulator), one is from drain pin VD input pulse signal Vd, again from power pin VCC The LDO of first target voltage VCC1 is exported, i.e., the first linear Voltage stabilizing module 10 is referred to as by the first linear Voltage stabilizing module 10 below First LDO 301；The other is exporting the second target voltage from signal pin HVIN input voltage signal, from power pin VCC LDO, i.e. the second linear voltage stabilization module 20, hereinafter referred to as the 2nd LDO 302.First LDO 301 includes the first NMOS tube N1, the The relatively list of one capacitor bias unit 11 (including first switch 1, second switch 2, third switch 3 and first capacitor C1), first Member 12 (including first and door S1, the first phase inverter and first comparator COMP1).2nd LDO 302 includes the second NMOS tube N2, the second capacitor bias unit 21 (including the 4th switch 4, the 5th switch 5, the 6th switch 6 and second capacitor C2), the second ratio Compared with unit 22 (including second and door S2, the second phase inverter and second comparator COMP2).In addition, bias voltage module 40, One signal judgment module 30, first resistor R1 and second resistance R2 are shared by the first LDO 301 and the 2nd LDO 302, partially It sets voltage module 40 and generates bias voltage V1, V2 and V3, respectively from the first end of bias voltage module 40, second end and third end Output；First signal judgment module 30 judges the height of the pulse signal Vd of drain pin VD input, when pulse signal Vd is greater than Setting certain reference voltage (such as 5V) when, the first signal judgment module 30 judge pulse signal Vd for high level, the first signal The output of judgment module 30 1, when pulse signal Vd is less than certain reference voltage (such as 5V) of setting, the first signal judgment module 30 Pulse signal Vd is judged for low level, and the first signal judgment module 30 exports 0；First resistor R1 and second resistance R2 is sampling electricity Resistance.

First LDO 301 inputs the first reference voltage Vref1 by the inverting input terminal of first comparator COMP1, and second LDO 302 inputs the second reference voltage Vref2 by the inverting input terminal of the second comparator COMP2, by being arranged different the One reference voltage Vref1 and the second reference voltage Vref2, so that different first target voltage VCC1 and the second target electricity be arranged Press VCC2.Cross normal phase input end input sample voltage vcc _ div of first comparator COMP1 and the second comparator COMP2.Work as electricity Actual driving voltage Vcc is more than target voltage (i.e. first target voltage VCC1 or the second target voltage on source capsule foot VCC When VCC2), corresponding LDO (the first LDO 301 or the 2nd LDO 302) will stop powering.For example, if the first LDO of setting 301 first target voltage VCC1 the second target voltage VCC2 less than the 2nd LDO 302, i.e. VCC1 < VCC2, have just been opened in circuit When dynamic, actual driving voltage Vcc=0, the first LDO 301 and the 2nd LDO 302 power simultaneously, when actual driving voltage After Vcc > VCC1, the first LDO 301I is automatically stopped power supply, and the 2nd LDO 302 continues to power, and finally maintains actual driving electricity Vcc is pressed to be equal to the second target voltage VCC2.

Signal pin HVIN can be connected according to different actual demands by different modes, to input different The drain electrode of voltage signal to the second NMOS tube N2 are also possible to pulse signal Vd specifically, the voltage signal of input can be 0 Or DC signal.Since the different connection types of signal pin HVIN can be different to the drain electrode of the second NMOS tube N2 input Voltage signal, finally make two LDO (the first LDO 301 and the 2nd LDO 302) realize different modes power supply self-powered with And power supply target voltage is adaptive switched.Its final effect achieved specifically: when the voltage signal of signal pin HVIN access is When 0V, finally obtained actual driving voltage Vcc is equal to target voltage VCC1, when signal pin HVIN accesses pulse voltage Vd Or access DC signal, finally obtained actual driving voltage Vcc are equal to target voltage VCC2.

The technical solution of the utility model realizes the effective self-powered of synchronous rectification control chip, even if in Width funtion Range and in the case where ringing waveform can also steady operation, without increasing auxiliary winding, diode and current-limiting resistance To obtain suitable actual driving voltage, does not need using junction field effect transistor as adjustment pipe yet, but utilize The strong driving capability of NMOS tube realizes the effective self-powered of chip.

Further, since the signal pin HVIN of synchronous rectification control chip provided by the utility model can be according to actual needs And different signals is accessed, different actual driving voltages is finally obtained, user only need to be by changing signal pin HVIN's Connection type can be obtained different actual driving voltages, without replacing synchronous rectification control chip or peripheral circuit member Part, easy to operate, flexibility is high.

In order to which the technical solution of the utility model and advantage is more clearly understood, below with bias voltage V2=0, V3= For Vcc (i.e. actual driving voltage), the impulse type linear voltage-stabilizing circuit of synchronous rectification control chip interior is carried out into one Step is described in detail.It should be appreciated that specific embodiment described herein is only used to explain the utility model, it is not used to limit The utility model.

Referring to Fig. 6, be bias voltage V2=0, power supply self-powered situation when V3=Vcc, signal pin HVIN are grounded Schematic diagram situation starts initial stage, first for purposes of illustration only, will realize that the self-powered process of power supply is divided into three phases The bootstrapping ascent stage of LDO 301 and the first LDO 301 stablize output stage.

Start the initial stage: when drain pin VD starts input pulse signal Vd, bias voltage module 40 starts to generate Bias voltage V1, V2, V3, wherein V1 is as shown in figure 8, V1 can be set in V2=0V, V3=Vcc, in practical applications, user, V2, V3 are any appropriate reference voltage value.In the starting initial stage, V1 is gradually risen, the grid voltage of the first NMOS tube N1 Vcap1 (i.e. first capacitor C1 top crown voltage) follows V1 to rise, therefore, when the first signal judgment module 30 judges pulse signal When Vd is high, it will be charged by the first NMOS tube N1 and first diode D1 to power pin VCC, voltage is gradually increasing.By Lower in incipient stage actual driving voltage, the first signal judgment module 30 can't effectively judge the height of pulse signal Vd It is low, thus at this time the first signal judgment module 30 output judge signal Vp for 0.

First LDO 301 bootstrapping ascent stage: when driving voltage Vcc actual on power pin VCC reaches certain value, First signal judgment module 30 can work normally, and the first LDO 301 enters bootstrapping ascent stage at this time.Specifically, work as arteries and veins When to rush signal Vd be low, the judgement signal Vp=0 of the first signal judgment module 30 output, first with the first control of door S1 output Signal s1=0, controls first switch 1 and second switch 2 is closed, and the bottom crown of first capacitor C1 connects V2 (V2=0V), top crown V1 is met, this state is first capacitor C1 charged state, charging voltage V1.When pulse signal Vd is got higher, the judgement of the first signal The judgement signal Vp=1 that module 30 exports, since actual driving voltage Vcc is less than first target voltage VCC1, sampling at this time Voltage vcc _ div passes through the first phase inverter less than the first reference voltage Vref1, the output OUT1=0 of first comparator COMP1 Be 1 after reversed, will it is reversed after the input of signal 1 first and door S1 first input end, therefore first with the output of door S1 at this time It is 1.At this point, first switch 1 and second switch 2 disconnect, third switch 3 is closed, and first capacitor C1 bottom crown meets V3 (V3= Vcc).At this point, first capacitor C1 top crown voltage Vcap1=V3+V1=Vcc+V1, therefore the grid voltage of the first NMOS tube N1 Vcap1 (i.e. first capacitor C1 top crown voltage) realizes bootstrapping, and the first NMOS tube N1 is sufficiently conductive, supplies for power pin VCC Electricity.

First LDO 301 stablizes output stage: as driving voltage constantly rises, as arrival first target voltage VCC1 When, Vcc_div > Vref1, therefore OUT1=1, by the first phase inverter carry out it is reversed after be 0, will it is reversed after signal input the The first input end of one and door S1, therefore first is s1=0 with the output of door S1 at this time, controls first switch 1 and second switch 2 Closure, third switch 3 disconnect, and the grid voltage Vcap1 of the first NMOS tube N1 is V1.In actual operation, usually setting V1 is small In the suitable voltage value of VL or other, to guarantee that the gate-source voltage of the first NMOS tube N1 at this time is less than conducting voltage, the first LDO 301 no longer power.Allowing comparator in actual design, there are certain hysteresis voltages, in the feelings that the first LDO 301 no longer powers Under condition, when due to synchronous rectification control chip interior power consumption actual driving voltage Vcc being gradually lower, first comparator The output OUT1=0 of COMP1, it is low to maintain actual driving voltage Vcc in cycles that the first LDO 301, which will rework, Driving voltage VL, low driving voltage VL are equal to first target voltage VCC1.

Referring to Fig. 7, being bias voltage V2=0, V3=Vcc, signal pin HVIN connect power supply confession when direct current signal Electricity and the adaptive switched situation schematic diagram of power supply target voltage.For purposes of illustration only, will realize that the self-powered process of power supply is divided into four ranks Section, i.e. starting initial stage, double LDO bootstrapping ascent stage, the 2nd LDO 302 bootstrapping ascent stage and the 2nd LDO 302 are steady Determine output stage.

Start the initial stage: when drain pin VD starts input pulse signal Vd, bias voltage module 40 starts to generate Bias voltage V1, V2, V3, wherein V1 is as shown in figure 9, V1 can be set in V2=0V, V3=Vcc, in practical applications, user, V2, V3 are any appropriate reference voltage value.In the starting initial stage, V1 is gradually risen, the grid voltage of the first NMOS tube N1 The grid voltage Vcap2 of Vcap1 and the second NMOS tube N2 follow V1 to rise, therefore, when the first signal judgment module 30 judges arteries and veins When to rush signal Vd be high, the first LDO 301 and the 2nd LDO 302 give power pin VCC by respective NMOS tube and diode Charging, driving voltage are gradually increasing.Since incipient stage actual driving voltage Vcc is lower, the first signal judgment module 30 is also It cannot effectively judge the height of pulse signal Vd, therefore the first signal judgment module 30 output at this time is 0.

Double LDO bootstrapping ascent stages: when driving voltage reaches certain value, the first signal judgment module 30 can be normal Work, at this point, the first LDO 301 and the 2nd LDO 302 enters bootstrapping ascent stage.Specifically, when pulse signal Vd is low, The judgement signal Vp=0 of first signal judgment module 30 output, so first exports s1=0 with door S1, second exports with door S2 S2=0, at this point, first switch 1, second switch 2, the 4th switch 4 and the 5th switch 5 closure, the electricity of first capacitor C1 and second The bottom crown for holding C2 connects V2 (i.e. 0V), and top crown connects V1 (Vcap1=Vcap2=V1), this state is first capacitor C1 and second The charged state of C2, charging voltage V1.When pulse signal Vd becomes high, the first signal judgment module 30 exports Vp=1, by It is less than first target voltage VCC1 and the second target voltage VCC2 in actual driving voltage Vcc, so first comparator COMP1 Output OUT1=0, the second comparator COMP2 output OUT2=0, s1=1, s2=1.At this point, first switch 1, second opening It closes the 2, the 4th switch 4 and the 5th switch 5 disconnects, third switch 3 and the 6th switch 6 closure, first capacitor C1 and the second capacitor The bottom crown of C2 connects reference voltage V3 (i.e. Vcc), the top crown voltage Vcap1=Vcap2 of first capacitor C1 and the second capacitor C2 =V3+V1=Vcc+V1, the i.e. grid voltage of the first NMOS tube N1 and the second NMOS tube N2 realize bootstrapping, the first NMOS tube N1 Can be sufficiently conductive with the second NMOS tube N2, the first LDO 301 and the 2nd LDO 302 are power pin VCC power supply.

2nd LDO 302 bootstrapping ascent stage: when actual driving voltage Vcc reaches first target voltage VCC1, The output OUT1=1 of Vcc_div > Vref1, first comparator COMP1 are 0 after being carried out reversely by the first phase inverter, therefore S1 =0, at this point, first switch 1 and second switch 2 are closed, third switch 3 is disconnected, Vcap1=V1.In practical applications, it usually sets It sets V1 and is less than the suitable voltage value of VH or other, to guarantee that the gate-source voltage of the first NMOS tube N1 at this time is less than conducting voltage, Therefore the first LDO 301 no longer powers.And due to actual driving voltage Vcc < VCC2, Vcc_div on power pin VCC at this time < Vref2, OUT2=0, therefore the power supply mode before maintenance is continued as power pin VCC power supply by the 2nd LDO 302.

2nd LDO 302 stablizes output stage: reaching the second target voltage when actual driving voltage Vcc constantly rises When VCC2, Vcc_div > Vref2, therefore OUT2=1, it is 0 after being carried out reversely by the second phase inverter, therefore S2=0, at this point, 4th switch 4 and the 5th switch 5 closure, the 6th switch 6 disconnect, Vcap2=V1, at this time the gate-source voltage of the second NMOS tube N2 Less than conducting voltage, the 2nd LDO 302 no longer powers.In actual design, allow comparator that certain hysteresis voltage is set, the In the case that two LDO 302 no longer power, make actual driving voltage Vcc since synchronous rectification controls chip interior power consumption When being gradually lower, the output OUT2=0 of the second comparator COMP2, the 2nd LDO 302 will rework, in cycles, to maintain Actual driving voltage Vcc is high driving voltage VH, and VH is equal to the second target voltage VCC2.

The linear Voltage stabilizing module of the first of the utility model and the adjustment pipe 1 of the second linear voltage stabilization module are all made of NMOS tube (i.e. the first NMOS tube N1 and the second NMOS tube N2) is realized, instead of the junction field effect transistor used in traditional technical solution The special process device such as pipe, saves chip area, reduces the dependence to technique.And since signal pin HVIN can pass through Different modes connect, to input different voltage signals to the second NMOS tube N2, finally obtain different actual drivings Voltage vcc realizes the flexibility of driving voltage selection, simplifies electricity in the case where being not necessarily to peripheral components and extra pin The design on road saves the area of pcb board.In technical solution provided by the utility model, it can change and synchronize according to actual needs The link position of the signal pin HVIN of rectification control chip, so that the drain electrode to the second NMOS tube N2 inputs different voltage letters Number (0, pulse signal Vd or DC signal)；Meanwhile drain pin VD inputs the drain electrode input pulse of the first NMOS tube N1 Signal Vd；Realize that power supply self-powered and power supply target voltage are autotomyed by the first linear Voltage stabilizing module and the second linear voltage stabilization module It changes, it is easy to operate, flexibility is high to obtain different driving voltages (low driving voltage VL or high driving voltage VH).

Referring to Fig. 9, the second aspect of the utility model embodiment provides a kind of synchronous commutating control circuit 01, including Above-mentioned synchronous rectification controls chip, further includes vice-side winding 100 and third NMOS tube N3.

The vice-side winding 100 of above-mentioned synchronous commutating control circuit 01 first end connection load 101, for receive primary side around The pulse signal Vd of group transmitting.The drain electrode of third NMOS tube N3 is connect with the second end of vice-side winding 100, source electrode ground connection, grid Connection driving pin synchronizes rectification to pulse signal Vd to realize for carrying out on-off according to driving signal.Wherein leak The drain electrode of pole pipe foot VD connection third NMOS tube N3, the source electrode of source electrode pin VS connection third NMOS tube N3, signal pin HVIN Ground connection.Since signal pin HVIN is grounded, the drain electrode of the second NMOS tube N2 of input synchronous rectification control chip interior Voltage signal is 0.

Referring to Fig. 10, the another aspect of the utility model embodiment provides another synchronous commutating control circuit, Chip is controlled including above-mentioned synchronous rectification, further includes vice-side winding 100, third NMOS tube N3.

The first end connection load 101 of vice-side winding 100, for receiving the pulse signal Vd of primary side winding transmitting.Third The drain electrode of NMOS tube N3 is connect with the second end of vice-side winding 100, source electrode ground connection, grid connection driving pin, for according to drive Dynamic signal carries out on-off, synchronizes rectification to pulse signal Vd to realize.The leakage of drain pin VD connection third NMOS tube N3 Pole, the source electrode of source electrode pin VS connection third NMOS tube N3, the drain electrode of signal pin HVIN connection third NMOS tube N3.Signal pipe The drain electrode of foot HVIN connection third NMOS tube N3, therefore its second NMOS tube N2 to synchronous rectification control chip interior at this time The voltage signal of drain electrode input is pulse signal Vd.

Figure 11 is please referred to, the another aspect of the utility model embodiment provides another synchronous commutating control circuit, Chip is controlled including above-mentioned synchronous rectification, further includes that vice-side winding 100 and the 3rd NMOS close N3.

The first end connection load 101 of vice-side winding 100, for receiving the pulse signal Vd of primary side winding transmitting.Third NMOS tube N3 drain electrode is connect with the second end of vice-side winding 100, source electrode ground connection, and grid connection driving pin HVIN is used for basis Driving signal carries out on-off, synchronizes rectification to pulse signal Vd to realize.Drain pin VD connection third NMOS tube N3's Drain electrode, the source electrode of source electrode pin VS connection third NMOS tube N3, the first end of signal pin HVIN connection vice-side winding 100.On The first end for stating vice-side winding 100 is DC signal output end, and signal pin HVIN is defeated by connection DC signal output end The voltage signal for entering the drain electrode of the second NMOS tube N2 to synchronous rectification control chip interior is DC signal.

In technical solution provided by the utility model, the signal of synchronous rectification control chip can be changed according to actual needs Different synchronous commutating control circuits 01,02 and 03 can be obtained in the link position of pin HVIN, i.e., by the 2nd NMOS The drain electrode of pipe N2 inputs different voltage signals (0, pulse signal Vd or DC signal), simultaneously to drain pin VD input The drain electrode input pulse signal Vd of first NMOS tube N1 realizes the power supply self-powered and power supply target electricity of synchronous rectification control chip Press it is adaptive switched, to obtain different driving voltages (low driving voltage VL or high driving voltage VH), without in peripheral circuit In add auxiliary circuit, the self-powered of chip can be realized and to drive external third NMOS tube N3 to synchronize simultaneously whole Stream, it is easy to operate, flexibility is high.

In a particular application, for different synchronous rectification control systems, required external or built-in MOSFET also not phase Together.For example, generalling use low-voltage driving MOSFET, low-voltage driving for the synchronous commutating control circuit of fixed 5V output MOSFET has the characteristics that conducting cut-in voltage is low, in order to promote the working efficiency of synchronous commutating control circuit, it usually needs adopt With lower driving voltage to reduce switching loss.And the output for 12V or more, it usually needs use high drive MOSFET, high drive MOSFET have the characteristics that conducting cut-in voltage is high, need to use higher driving voltage low to obtain Conducting resistance reduces conduction loss.

In technical solution provided by the utility model, synchronization can be changed according to three kinds of above-mentioned modes according to actual needs Rectification control chip signal pin HVIN link position, thus obtain different driving voltages (low driving voltage VL or High driving voltage VH), realize the flexibility of driving voltage.

To sum up, above-mentioned synchronous commutating control circuit controls chip return pulse signal Vd and electricity by synchronous rectification It after pressing signal, carries out power supply self-powered and power supply target voltage is adaptive switched, to control third NMOS tube N3, without increasing Add auxiliary winding, diode and current-limiting resistance, saves the area of pcb board, simplifies circuit, solve traditional technical side It needs to increase auxiliary winding, diode and current-limiting resistance present in case (please referring to Fig. 8) and suitably drives electricity to obtain The problem of pressing, leading to complex circuit designs.

Above-mentioned synchronous rectification control chip utilizes the strong driving capability of NMOS tube, in the first internal linear Voltage stabilizing module 10 and second linear voltage stabilization module 20 using the first and second NMOS tube as adjustment pipe, instead of traditional technical solution In special process device junction field effect transistor, save chip area, and reduce the dependence to technique.This is practical new The synchronous rectification that type embodiment provides controls chip, the control issued respectively according to the first comparing unit 12 and the second comparing unit 22 Signal (respectively first control signal s1 and second control signal s2) control first capacitor unit 11 and the second capacitor list processed The working condition of member 12, so that the on-off of control the first NMOS tube and the second NMOS tube, realizes the electricity of synchronous rectification control chip From power supply.It in practical applications, can be according to different needs of applying, by the different connection type of signal pin HVIN, most Different actual driving voltages is obtained eventually, realizes that synchronous rectification control chip power self-powered and power supply target voltage are autotomyed It changes.

It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function Can module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different functions Module is completed, i.e., the internal structure of device is divided into different functional unit or module, with complete it is described above whole or Person's partial function.The specific name of each functional module is only for convenience of distinguishing each other, the protection being not intended to limit this application Range.

The above is only the preferred embodiments of the present utility model only, is not intended to limit the utility model, all practical at this Made any modifications, equivalent replacements, and improvements etc., should be included in the guarantor of the utility model within novel spirit and principle Within the scope of shield.

Claims (10)

1. a kind of synchronous rectification controls chip characterized by comprising

For pulse signal to be converted to the first linear Voltage stabilizing module of first target voltage；

It is connect with the first linear regulator module, for voltage signal to be converted to the second linear steady of the second target voltage Die block；

It is connect with the described first linear Voltage stabilizing module and the second linear voltage stabilization module, for judging the pulse signal After level height, output judges the first signal judgment module of signal；And

It is connect with the described first linear Voltage stabilizing module and the second linear voltage stabilization module, for providing the biasing of bias voltage Voltage module；

Wherein, the described first linear Voltage stabilizing module includes:

Realize that by the output of pulse signal be described first for receiving the pulse signal, and by the on off operating mode of itself First NMOS tube of target voltage；

It is connect with the grid of first NMOS tube, the first capacitor biasing of the on off operating mode for controlling first NMOS tube Unit；And

It is connect with the first capacitor bias unit, for comparing the first reference voltage and sampled voltage, and according to comparison result And the judgement signal accordingly exports first control signal, to control the of the working condition of the first capacitor bias unit One comparing unit；

The second linear voltage stabilization module includes:

Realize that by voltage signal output be the second target for receiving the voltage signal, and by the on off operating mode of itself Second NMOS tube of voltage；

It is connect with the grid of second NMOS tube, the second capacitor biasing of the on off operating mode for controlling second NMOS tube Unit；And

It is connect with the second capacitor bias unit, for comparing the second reference voltage and sampled voltage, and according to comparison result And the judgement signal accordingly exports second control signal, to control the of the working condition of the second capacitor bias unit Two comparing units.

2. synchronous rectification as described in claim 1 controls chip, which is characterized in that the synchronous rectification control chip also wraps It includes:

Drive pin, power pin, drain pin, source electrode pin and signal pin；Wherein

The driving pin is connect with external system, for output drive signal to drive external system；

The drain pin connects the drain electrode of first NMOS tube, for inputting the pulse signal；

The signal pin connects the drain electrode of second NMOS tube, for inputting the voltage signal.

3. synchronous rectification as claimed in claim 2 controls chip, which is characterized in that the synchronous rectification control chip also wraps It includes:

First diode, the second diode, first resistor and second resistance；

The anode of the first diode connects the source electrode of first NMOS tube, and cathode connects the power pin；Described The anode of two diodes connects the source electrode of second NMOS tube, and cathode connects the power pin；The of the first resistor One end connects the cathode of the first diode, and second end connects the first end of the second resistance, and the of the second resistance Two ends ground connection；The sampling end of the sampling end of first comparing unit and second comparing unit connects described first jointly The second end of resistance.

4. synchronous rectification as claimed in claim 3 controls chip, which is characterized in that the first capacitor bias unit includes:

First switch, second switch, third switch and first capacitor；

The first end of the bias voltage module connects the first end of the first switch, the second end connection of the first switch The grid of first NMOS tube, the second end of the bias voltage module connect the first end of the second switch, and described The second end of two switches connects the first end of the first capacitor, and the second end of the first capacitor connects first NMOS tube Grid, the third end of the bias voltage module connects the first end of third switch, the second end of the third switch Connect the first end of the first capacitor.

5. synchronous rectification as claimed in claim 3 controls chip, which is characterized in that the second capacitor bias unit includes:

4th switch, the 5th switch, the 6th switch and the second capacitor；

The first end of the bias voltage module connects the first end of the 4th switch, the second end connection of the 4th switch The grid of second NMOS tube, the second end of the bias voltage module connect the first end of the 5th switch, and described the The second end of five switches connects the first end of second capacitor, and the second end of second capacitor connects second NMOS tube Grid, the third end of the bias voltage module connect it is described 6th switch first end, it is described 6th switch second end Connect the first end of second capacitor.

6. synchronous rectification as claimed in claim 3 controls chip, which is characterized in that first comparing unit includes:

First with door, the first phase inverter and first comparator；

The normal phase input end of the first comparator is the sampling end of first comparing unit, and inverting input terminal is described first Reference voltage input；The output end of the first comparator connects first phase inverter, the output of first phase inverter The first input end of end connection described first and door, the output end of the first signal judgment module connect described first and door Second input terminal；Described first connect with the output end of door with the first capacitor bias unit, is configured as exporting described One control signal.

7. synchronous rectification as claimed in claim 3 controls chip, which is characterized in that second comparing unit includes:

Second with door, the second phase inverter and the second comparator；

The normal phase input end of second comparator is the sampling end of second comparing unit, and inverting input terminal is described second Reference voltage input；The output end of second comparator connects second phase inverter, the output of second phase inverter The first input end of end connection described second and door, the output end of the first signal judgment module connect described second and door Second input terminal；Described second connect with the output end of door with the second capacitor bias unit, is configured as exporting described Two control signals.

8. a kind of synchronous commutating control circuit, which is characterized in that including the described in any item synchronous rectifications of such as claim 2 to 7 Control chip, further includes:

First end connection load, the vice-side winding of the pulse signal for receiving primary side winding transmitting；With

Drain electrode is connect with the second end of the vice-side winding, and source electrode ground connection, grid connects the driving pin, for according to Driving signal carries out on-off, to realize the third NMOS tube for synchronizing rectification to the pulse signal；Wherein

The drain pin connects the drain electrode of the third NMOS tube, and the source electrode pin connects the source of the third NMOS tube Pole, the signal pin ground connection.

9. a kind of synchronous commutating control circuit, which is characterized in that including the described in any item synchronous rectifications of such as claim 2 to 7 Control chip, further includes:

First end connection load, the vice-side winding of the pulse signal for receiving primary side winding transmitting；With

Drain electrode is connect with the second end of the vice-side winding, and source electrode ground connection, grid connects the driving pin, for according to Driving signal carries out on-off, to realize the third NMOS tube for synchronizing rectification to the pulse signal；Wherein

The drain pin connects the drain electrode of the third NMOS tube, and the source electrode pin connects the source of the third NMOS tube Pole, the signal pin connect the drain electrode of the third NMOS tube.

10. a kind of synchronous commutating control circuit, which is characterized in that including the described in any item synchronous rectifications of such as claim 2 to 7 Control chip, further includes:

First end connection load, the vice-side winding of the pulse signal for receiving primary side winding transmitting；With

Drain electrode is connect with the second end of the vice-side winding, and source electrode ground connection, grid connects the driving pin, for according to Driving signal carries out on-off, to realize the third NMOS tube for synchronizing rectification to the pulse signal；Wherein

The drain pin connects the drain electrode of the third NMOS tube, and the source electrode pin connects the source of the third NMOS tube Pole, the signal pin connect the first end of the vice-side winding.