CN107422773A - Digital low-dropout regulator - Google Patents
Digital low-dropout regulator Download PDFInfo
- Publication number
- CN107422773A CN107422773A CN201710665533.5A CN201710665533A CN107422773A CN 107422773 A CN107422773 A CN 107422773A CN 201710665533 A CN201710665533 A CN 201710665533A CN 107422773 A CN107422773 A CN 107422773A
- Authority
- CN
- China
- Prior art keywords
- transistor
- drain electrode
- sampling resistor
- dropout regulator
- digital low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 239000000872 buffer Substances 0.000 claims description 21
- 230000005611 electricity Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Dc-Dc Converters (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a kind of digital low-dropout regulator, including power adjustment transistor, the first sampling resistor, the second sampling resistor and pulsewidth modulation generation circuit；The source electrode of the power adjustment transistor is connected to supply voltage, its drain electrode is used as output end, and first sampling resistor and second sampling resistor by forming series connection are grounded, its grid receives the control signal of pulsewidth modulation generation circuit production to realize that the power adjusts the turn-on and turn-off of transistor；The pulsewidth modulation generation circuit is connected to reference voltage and realizes its control source；The pulsewidth modulation generation circuit is connected between first sampling resistor and second sampling resistor, to receive the sampled signal of first sampling resistor and second sampling resistor feedback.Compared with correlation technique, digital low-dropout regulator circuit structure of the invention is simple, and output voltage ripple is small, stable performance and cost is low.
Description
【Technical field】
The present invention relates to a kind of electronic circuit field, more particularly to a kind of digital low-dropout regulator.
【Background technology】
In the application of integrated circuit, in order to adapt to the demand of various application scenarios, generally require to use different level,
Such as, it is necessary to which a variety of supply voltages, it passes through linear low voltage in system level chip (System on Chip, SOC)
Poor voltage-stablizer (low dropout regulator, LDO) realizes a variety of supply voltage needs in SOC.
And the LDO mainly has two classes：One kind is to realize that the advantage of this class formation is power supply ripple using pure analog form
It is smaller, but loop compensation is more complicated so that and chip area is bigger, and cost is of a relatively high；Other one kind is using numeral
Mode realizes that area is small, and cost is low, the conversion process construction cycle is relatively short, turns into Developing mainstream.
However, extra clock generation circuit is needed in the digital low-dropout regulator of correlation technique, the voltage of LDO outputs
Ripple size is related to the clock cycle, in order to meet the requirement of the power supply ripple under the conditions of different loads, it is necessary to the control of complexity
Circuit is realized, adds LDO cost.
Therefore, it is necessary to a kind of new digital low-dropout regulator is provided to solve the above problems.
【The content of the invention】
It is an object of the invention to provide a kind of digital low-dropout regulator, its circuit structure is simple, and with fixed
The structure ratio of clock frequency, output voltage ripple is small, stable performance and cost is low.
In order to achieve the above object, the invention provides a kind of digital low-dropout regulator, including power adjustment transistor,
First sampling resistor, the second sampling resistor and pulsewidth modulation generation circuit；
The source electrode of the power adjustment transistor is connected to supply voltage to be used as the defeated of the digital low-dropout regulator
Enter end；
The drain electrode of the power adjustment transistor passes through first sampling resistor for forming series connection and second sampling
Resistance eutral grounding, and output end of the drain electrode of power adjustment transistor as the digital low-dropout regulator；
The grid of power adjustment transistor receives the control signal of the pulsewidth modulation generation circuit production to realize
The turn-on and turn-off of the power adjustment transistor；
The pulsewidth modulation generation circuit is connected to reference voltage and realizes its control source；
The pulsewidth modulation generation circuit is connected between first sampling resistor and second sampling resistor, to
Receive the sampled signal of first sampling resistor and second sampling resistor feedback.
Preferably, the pulsewidth modulation generation circuit includes the first transistor, second transistor, third transistor, the 4th
Transistor, the 5th transistor, the 6th transistor, the first electric capacity and the second electric capacity；
The grid of the first transistor realizes input, the source of the first transistor by being connected to the sampled signal
Pole is connected to ground connection, and the drain electrode of the first transistor is connected to the drain electrode of the third transistor；
The grid of the second transistor realizes input, the source of the second transistor by being connected to the reference voltage
Pole is connected to ground connection, and the drain electrode of the second transistor is connected to the drain electrode of the 4th transistor；
The grid of the third transistor connects the grid of the 4th transistor, and the source electrode of the third transistor is used for
Supply voltage is connected to, the drain electrode of the third transistor is extremely grounded by first capacitance connection, wherein, described second is brilliant
Signal of the drain electrode of signal of the drain electrode of body pipe after logic gate buffer and the first transistor after logic gate buffer is common
The grid of the third transistor is connected to after logical AND gate；
The source electrode of 4th transistor is used to be connected to supply voltage, and the drain electrode of the 4th transistor passes through described the
Two capacitance connections are extremely grounded；
The source electrode of 5th transistor is used to be connected to supply voltage, and the drain electrode of the 5th transistor is connected to described
The grid of power adjustment transistor is used to export the control signal, and the drain electrode of the second transistor is successively through logic gate buffer
Signal of the drain electrode after logic gate buffer with the signal after logic inverter and the first transistor is jointly after logic sum gate
It is connected to the grid of the 5th transistor；
The source electrode of 6th transistor is used to be connected to ground connection, and the drain electrode of the 6th transistor is connected to the described 5th
The drain electrode of transistor, the signal after logic gate buffer and logic inverter and described first successively that drains of the second transistor
Signal of the drain electrode of transistor after logic gate buffer is connected to the grid of the 6th transistor after logical AND gate jointly.
Preferably, the first transistor, the second transistor and the 6th transistor are nmos pass transistor；Institute
It is PMOS transistor to state third transistor, the 4th transistor and the 5th transistor.
Preferably, the logic gate buffer is that two logic reversal devices are in series.
Preferably, the digital low-dropout regulator also includes load and compensating electric capacity, the power adjustment transistor
Drain electrode is grounded by the load and compensating electric capacity.
Preferably, the power adjustment transistor is PMOS transistor.
Preferably, the control signal is pulse-width signal.
Compared with correlation technique, digital low-dropout regulator of the invention sets up pulsewidth modulation generation circuit and produces pulsewidth tune
Signal processed inputs to the power and adjusts transistor to control its turn-on and turn-off, and produces electricity by inputting to the pulsewidth modulation
The difference of the reference voltage on road and the sampled signal of feedback determines the ON time of the power adjustment transistor, it is not necessary to extra
Clock generation circuit so that the output voltage ripple of the digital low-dropout regulator is smaller, and due to using pulsewidth modulation
So that its small power consumption, chip area is small and cost is low.
【Brief description of the drawings】
Fig. 1 is the structured flowchart of the digital low-dropout regulator of the present invention；
Fig. 2 is the pulsewidth modulation generation circuit structure chart of the digital low-dropout regulator of the present invention.
【Embodiment】
The invention will be further described with embodiment below in conjunction with the accompanying drawings.
Referring to Fig. 1, the structured flowchart for the digital low-dropout regulator of the present invention.The invention provides a kind of digital low pressure
Poor voltage-stablizer 10, including power adjustment transistor 1, the first sampling resistor R1, the second sampling resistor R2, pulsewidth modulation generation circuit
2, and load and compensating electric capacity CL.
Power adjustment transistor is PMOS transistor or nmos pass transistor or PNP transistor or NPN transistor etc.,
In present embodiment, illustrate so that power adjustment transistor is PMOS transistor as an example, the source of the power adjustment transistor 1
Pole is connected to supply voltage VDD using the input as the digital low-dropout regulator 10.
The drain electrode of the power adjustment transistor 1 is adopted by forming the first sampling resistor R1 and described second of series connection
Sample resistance R2 is grounded, and output end of the drain electrode of power adjustment transistor 1 as the digital low-dropout regulator 10.
The grid of the power adjustment transistor 1 receives the control signal Vctrl that the pulsewidth modulation generation circuit 2 produces
To realize the turn-on and turn-off of the power adjustment transistor 1.
Specifically, the control signal Vctrl is pulse-width signal.
The pulsewidth modulation generation circuit 2 is connected to reference voltage V ref and realizes its control source；The pulsewidth modulation production
Raw circuit 2 is connected between the first sampling resistor R1 and the second sampling resistor R2 simultaneously, to receive described first
The sampled signal Vfb (i.e. feedback voltage) of sampling resistor R1 and the second sampling resistor R2 feedbacks, is sampled by described first
Resistance R1 and the second sampling resistor R2 sampled signal Vfb are inputted to the pulsewidth modulation generation circuit as feedback voltage
2, realize feedback.
The power adjusts the ON time of transistor 1 by the sampled signal Vfb and reference voltage V ref difference
Different decision.
The load and compensating electric capacity CL are used to realize capacitance compensation, and the drain electrode of the power adjustment transistor 1 passes through institute
State load and compensating electric capacity CL ground connection.
Please refer to Fig. 2, the pulsewidth modulation generation circuit structure chart of the digital low-dropout regulator of the present invention.The pulsewidth
Modulating generation circuit 2 includes the first transistor MN1, second transistor MN2, third transistor MP1, the 4th transistor MP2, the 5th
Transistor MP3, the 6th transistor MN3, the first electric capacity C1 and the second electric capacity C2.
The grid of the first transistor MN1 realizes input, the first crystal by being connected to the sampled signal Vfb
Pipe MN1 source electrode is connected to ground connection, and the drain electrode of the first transistor MN1 is connected to the drain electrode of the third transistor MP1.
The grid of the second transistor MN2 realizes input by being connected to the reference voltage V ref, and described second is brilliant
Body pipe MN2 source electrode is connected to ground connection, and the drain electrode of the second transistor MN2 is connected to the drain electrode of the 4th transistor MP2.
The grid of the third transistor MP1 connects the grid of the 4th transistor MP2, the third transistor MP1
Source electrode be used to be connected to supply voltage VDD, third transistor MP1 drain electrode and be connected to and connect by the first electric capacity C1
Ground.Wherein, the drain electrode of signal of the drain electrode of the second transistor MN2 after logic gate buffer and the first transistor MN1
Signal after logic gate buffer is connected to the grid of the third transistor MP1 after logical AND gate jointly.
It should be noted that in present embodiment, the logic gate buffer is two logic reversal device (i.e. two logic NOTs
Door) it is in series.
The source electrode of the 4th transistor MP2 is used to be connected to supply voltage VDD, the drain electrode of the 4th transistor MP2
Ground connection is connected to by the second electric capacity C2.
The source electrode of the 5th transistor MP3 is used to be connected to supply voltage VDD, the drain electrode of the 5th transistor MP3
The grid for being connected to the power adjustment transistor 1 is used for output control signal Vctrl, wherein, the control signal Vctrl is
Pulse-width signal caused by the pulsewidth modulation generation circuit 2；The drain electrode of the second transistor MN2 buffers through logic successively
Signal of signal after device and logic inverter and the first transistor MN1 drain electrode after logic gate buffer jointly through logic or
The grid of the 5th transistor MP3 is connected to behind the door.
The source electrode of the 6th transistor MN3 is used to be connected to ground connection, and the drain electrode of the 6th transistor MN3 is connected to institute
State the 5th transistor MP3 drain electrode, the letter after logic gate buffer and logic inverter successively that drains of the second transistor MN2
Signal number with the drain electrode of the first transistor MN1 after logic gate buffer is connected to the described 6th after logical AND gate jointly
Transistor MN3 grid.
More excellent, in present embodiment, the first transistor MN1, the second transistor MN2 and the 6th crystal
Pipe MN3 is nmos pass transistor；The third transistor MP1, the 4th transistor MP2 and the 5th transistor MP3 are equal
For PMOS transistor.
In present embodiment, with the connection of the drain electrode and the drain electrode of the third transistor MP1 of the first transistor MN1
Place drains with the junction of the drain electrode of the 4th transistor MP2 as node as node N1's, the second transistor MN2
N2, the 5th transistor MP3 grid are said as node N3, the grid of the 6th transistor MN3 as node N4
It is bright：
The third transistor MP1 and the 4th transistor MP2 carries out preliminary filling to the node N1 and node N2
Electricity, the first transistor MN1 and the second transistor MN2 discharge the node N1 and node N2 respectively.It is described
The first transistor MN1 grid is connected to the sampled signal Vfb, and the grid of the second transistor MN2 is connected to the base
Quasi- voltage Vref.
When the reference voltage V ref is more than the sampled signal Vfb, the node N2 discharges into low level first, institute
State node N1 and still maintain high level, it can thus be concluded that the level to the node N4 is height, the level of the node N3 is also
Height, therefore, the 5th transistor MP3 shut-offs, the 6th transistor MN3 conductings.The control signal Vctrl is low electricity
Flat, this low level will cause the power adjustment transistor 1 to turn on, to the output node of the digital low-dropout regulator 10
Charged, make the sampled signal Vfb voltages progressively close to the reference voltage V ref.
When the sampled signal Vfb voltages are more than the reference voltage V ref, then the node N1 is discharged into low first
Level, so that the control signal Vctrl turns off the power for high level adjusts transistor 1.
, can be in the third transistor after node N1 and the one of nodes of node N2 reach low level
Low level signal is produced on MP1 grid RST nodes, then restarts the sampled signal Vfb and the reference voltage V ref
Voltage comparison procedure.So learn that the control signal Vctrl of the power adjustment transistor 1 pulsewidth is adopted with described
Sample signal Vfb and the reference voltage V ref associateds.When the sampled signal Vfb is infinitely close to the reference voltage V ref
When, the output voltage Vout that can obtain the digital low-dropout regulator 10 is：
Therefore, from the foregoing, it will be observed that the digital low-dropout regulator 10 of the present invention passes through the pulsewidth modulation generation circuit 2
Produce pulse width signal to be modulated, it is not necessary to extra clock generation circuit, make its small power consumption, chip area is small, and cost is low.
Compared with correlation technique, digital low-dropout regulator of the invention sets up pulsewidth modulation generation circuit and produces pulsewidth tune
Signal processed inputs to the power and adjusts transistor to control its conducting and shut-off, and produces electricity by inputting to the pulsewidth modulation
The difference of the reference voltage on road and the sampled signal of feedback determines the ON time of the power adjustment transistor, it is not necessary to extra
Clock generation circuit so that the output voltage ripple of the digital low-dropout regulator is smaller, and due to using pulsewidth modulation
So that its small power consumption, chip area is small and cost is low.
Above-described is only embodiments of the present invention, it should be noted here that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
Enclose.
Claims (7)
- A kind of 1. digital low-dropout regulator, it is characterised in that：Including power adjustment transistor, the first sampling resistor, the second sampling resistor and pulsewidth modulation generation circuit；The source electrode of the power adjustment transistor is connected to supply voltage using the input as the digital low-dropout regulator；The drain electrode of the power adjustment transistor passes through first sampling resistor for forming series connection and second sampling resistor Ground connection, and output end of the drain electrode of power adjustment transistor as the digital low-dropout regulator；The control signal that the grid of the power adjustment transistor receives the pulsewidth modulation generation circuit production is described to realize The turn-on and turn-off of power transmission transistor；The pulsewidth modulation generation circuit is connected to reference voltage and realizes its control source；The pulsewidth modulation generation circuit is connected between first sampling resistor and second sampling resistor, to receive The sampled signal of first sampling resistor and second sampling resistor feedback.
- 2. digital low-dropout regulator according to claim 1, it is characterised in that：The pulsewidth modulation generation circuit includes The first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the first electric capacity and Second electric capacity；The grid of the first transistor realizes input by being connected to the sampled signal, and the source electrode of the first transistor connects Ground connection is connected to, the drain electrode of the first transistor is connected to the drain electrode of the third transistor；The grid of the second transistor realizes input by being connected to the reference voltage, and the source electrode of the second transistor connects Ground connection is connected to, the drain electrode of the second transistor is connected to the drain electrode of the 4th transistor；The grid of the third transistor connects the grid of the 4th transistor, and the source electrode of the third transistor is used to connect To supply voltage, the drain electrode of the third transistor is extremely grounded by first capacitance connection, wherein, the second transistor Signal of the drain electrode after logic gate buffer and the first transistor signal of the drain electrode after logic gate buffer jointly through patrolling Collect the grid with being connected to the third transistor behind the door；The source electrode of 4th transistor is used to be connected to supply voltage, and the drain electrode of the 4th transistor passes through the described second electricity Appearance is connected to ground connection；The source electrode of 5th transistor is used to be connected to supply voltage, and the drain electrode of the 5th transistor is connected to the power The grid of adjustment transistor is used to export the control signal, and the drain electrode of the second transistor through logic gate buffer and is patrolled successively Signal of the non-signal behind the door with the drain electrode of the first transistor after logic gate buffer is collected to be connected after logic sum gate jointly To the grid of the 5th transistor；The source electrode of 6th transistor is used to be connected to ground connection, and the drain electrode of the 6th transistor is connected to the 5th crystal The drain electrode of pipe, the drain signal after logic gate buffer and logic inverter successively and the first crystal of the second transistor Signal of the drain electrode of pipe after logic gate buffer is connected to the grid of the 6th transistor after logical AND gate jointly.
- 3. digital low-dropout regulator according to claim 2, it is characterised in that：The first transistor, described second Transistor and the 6th transistor are nmos pass transistor；The third transistor, the 4th transistor and the described 5th Transistor is PMOS transistor.
- 4. digital low-dropout regulator according to claim 2, it is characterised in that：The logic gate buffer is two logics Reverser is in series.
- 5. digital low-dropout regulator according to claim 1, it is characterised in that：The digital low-dropout regulator also wraps Load and compensating electric capacity are included, the drain electrode of the power transmission transistor is grounded by the load and compensating electric capacity.
- 6. digital low-dropout regulator according to claim 1, it is characterised in that：The power adjustment transistor is PMOS Transistor.
- 7. digital low-dropout regulator according to claim 1, it is characterised in that：The control signal is believed for pulsewidth modulation Number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710665533.5A CN107422773B (en) | 2017-08-07 | 2017-08-07 | Digital low-dropout regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710665533.5A CN107422773B (en) | 2017-08-07 | 2017-08-07 | Digital low-dropout regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107422773A true CN107422773A (en) | 2017-12-01 |
| CN107422773B CN107422773B (en) | 2019-02-05 |
Family
ID=60437438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710665533.5A Active CN107422773B (en) | 2017-08-07 | 2017-08-07 | Digital low-dropout regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107422773B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108388299A (en) * | 2018-02-12 | 2018-08-10 | 上海集成电路研发中心有限公司 | Low pressure difference linear voltage regulator |
| CN112711287A (en) * | 2019-10-25 | 2021-04-27 | 恩智浦有限公司 | System including a low dropout regulator |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101065891A (en) * | 2004-12-03 | 2007-10-31 | 罗姆股份有限公司 | Switching power supply and its control circuit, and electronic apparatus employing such switching power supply |
| CN101286721A (en) * | 2007-11-16 | 2008-10-15 | 西北工业大学 | Stepper Motor Drive System with Current Negative Feedback |
| CN201352323Y (en) * | 2009-02-13 | 2009-11-25 | 深圳艾科创新微电子有限公司 | High-efficient synchronous rectification depressurization-type voltage stabilizer |
| US7710168B2 (en) * | 2007-08-17 | 2010-05-04 | National Semiconductor Corporation | Apparatus and method for two tier output stage for switching devices |
| CN101842970A (en) * | 2007-12-06 | 2010-09-22 | 英特赛尔美国股份有限公司 | System and method for improving inductor current sensing accuracy of a dc/dc voltage regulator |
| CN103558891A (en) * | 2013-09-22 | 2014-02-05 | 龙芯中科技术有限公司 | Low dropout regulator |
| CN103631299A (en) * | 2013-05-21 | 2014-03-12 | 中国科学院电子学研究所 | Constant-differential-pressure and variable-output-voltage low dropout regulator |
| CN206077347U (en) * | 2016-09-21 | 2017-04-05 | 湖北三江航天万峰科技发展有限公司 | Numeric type IGBT is controlled and driving means |
-
2017
- 2017-08-07 CN CN201710665533.5A patent/CN107422773B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101065891A (en) * | 2004-12-03 | 2007-10-31 | 罗姆股份有限公司 | Switching power supply and its control circuit, and electronic apparatus employing such switching power supply |
| US7710168B2 (en) * | 2007-08-17 | 2010-05-04 | National Semiconductor Corporation | Apparatus and method for two tier output stage for switching devices |
| CN101286721A (en) * | 2007-11-16 | 2008-10-15 | 西北工业大学 | Stepper Motor Drive System with Current Negative Feedback |
| CN101842970A (en) * | 2007-12-06 | 2010-09-22 | 英特赛尔美国股份有限公司 | System and method for improving inductor current sensing accuracy of a dc/dc voltage regulator |
| CN201352323Y (en) * | 2009-02-13 | 2009-11-25 | 深圳艾科创新微电子有限公司 | High-efficient synchronous rectification depressurization-type voltage stabilizer |
| CN103631299A (en) * | 2013-05-21 | 2014-03-12 | 中国科学院电子学研究所 | Constant-differential-pressure and variable-output-voltage low dropout regulator |
| CN103558891A (en) * | 2013-09-22 | 2014-02-05 | 龙芯中科技术有限公司 | Low dropout regulator |
| CN206077347U (en) * | 2016-09-21 | 2017-04-05 | 湖北三江航天万峰科技发展有限公司 | Numeric type IGBT is controlled and driving means |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108388299A (en) * | 2018-02-12 | 2018-08-10 | 上海集成电路研发中心有限公司 | Low pressure difference linear voltage regulator |
| CN112711287A (en) * | 2019-10-25 | 2021-04-27 | 恩智浦有限公司 | System including a low dropout regulator |
| CN112711287B (en) * | 2019-10-25 | 2024-04-19 | 恩智浦有限公司 | System including low dropout voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107422773B (en) | 2019-02-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2018161834A1 (en) | Low-dropout regulators | |
| CN102566633B (en) | Low Dropout Regulator | |
| CN101097456B (en) | Voltage regulator | |
| CN202486643U (en) | High-bandwidth low-voltage difference linear voltage-stabilizing source, system and chip | |
| CN107070202B (en) | Circuit for generating negative voltage with voltage automatic regulation function | |
| CN109088532A (en) | A kind of current mode segmentation gate driving circuit with active clamp | |
| CN105988495A (en) | LDO (Low Drop-out voltage regulator) overshooting protection circuit | |
| CN103268134B (en) | The low difference voltage regulator of transient response can be improved | |
| CN105932873B (en) | A kind of charge pump of low-power consumption high output voltage | |
| CN103647440A (en) | Soft-start circuit and DC-DC circuit including soft-start circuit | |
| CN103529890A (en) | Soft start device and method | |
| CN109565242A (en) | Series circuit, circuit board and calculating equipment | |
| CN107994767A (en) | Voltage source | |
| CN108806583A (en) | Shift register cell, driving method, shift register and display device | |
| CN205490463U (en) | Electrify restoration circuit | |
| CN101505094A (en) | Electric power supply module for portable equipment | |
| CN107422773B (en) | Digital low-dropout regulator | |
| CN208890646U (en) | Series circuit, circuit board and calculating equipment | |
| CN104950976A (en) | Voltage stabilizing circuit based on slew rate increasing | |
| CN103529891A (en) | Soft start device and method | |
| CN103529901B (en) | Circuit used for supplying power for bootstrap circuit | |
| CN109412395A (en) | Power supply starting adjusting circuit and power supply circuit | |
| CN103944554A (en) | Level switching circuit and digital-to-analog converter | |
| CN104470095B (en) | Ripple rejection LED drive circuit | |
| CN102591401B (en) | Built-in digital power circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20171201 Assignee: Shandong industry research information and Artificial Intelligence Integration Research Institute Co.,Ltd. Assignor: HUNAN GOKE MICROELECTRONICS Co.,Ltd. Contract record no.: X2021430000001 Denomination of invention: Digital low dropout regulator Granted publication date: 20190205 License type: Common License Record date: 20210115 |
|
| EE01 | Entry into force of recordation of patent licensing contract |