CN209000871U - A kind of wafer test system - Google Patents
A kind of wafer test system Download PDFInfo
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- CN209000871U CN209000871U CN201822053580.7U CN201822053580U CN209000871U CN 209000871 U CN209000871 U CN 209000871U CN 201822053580 U CN201822053580 U CN 201822053580U CN 209000871 U CN209000871 U CN 209000871U
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Abstract
The utility model provides a kind of wafer test system.The wafer test system includes tester table, pretest device, flash chip, wafer tester and probe card；Wherein, tester table is connected with each other pretest device, flash chip, wafer tester and probe card, and pretest device connects flash chip, and flash chip connects wafer tester；When the wafer test system of the utility model carries out wafer pretest, tester table sends prediction trial signal to pretest device, pretest device carries out pretest, since probe card is in lifting status, effective test result can't be returned, the unacceptable test result of test can be exported under normal circumstances, illustrate that tester table is in normal test mode, so that it is guaranteed that the accuracy of the wafer test of the subsequent progress of wafer tester, and then obtain true wafer yield.
Description
Technical field
The utility model relates to IC manufacturing and the field of test technology more particularly to a kind of wafer test systems.
Background technique
Wafer test (Circuit Probe, CP) is one of test after wafer manufacture is completed, for verifying wafer
Each bare die (DIE) whether meet device feature and other design specifications (Specification), On-Wafer Measurement it
Afterwards, underproof bare die can be screened, obtains the yield of wafer.
In order to improve testing efficiency, multi-bit parallel is mostly used to test at present, such as 64,128,256 etc., multidigit is simultaneously
Row test is in primary test, and multiple bare dies are put down and contacted simultaneously to probe card, and tester table sends out primary test signal and is
The test of achievable multiple bare die, wherein the corresponding bare die of a bit test.However, wherein exception ought occur by certain bit test,
Especially when passing through result extremely for test, this exception is difficult the On-Wafer Measurement stage and is identified, and causing may mistake
The bare die of effect is not screened out, obtains false wafer yield, and yield is that chip design side judges product quality
Important evidence, false yield will increase subsequent encapsulation and testing cost, also result in poor quality product and flow to terminal
Unnecessary loss is caused in market.
During applicant's long term monitoring, due to there is a large amount of unacceptable test result of same test item, such as
It is the test wafer figure of a wafer, which is tested using 64 parallel-by-bits of 16x4, in the big portion in the middle and lower part of wafer shown in Fig. 1
Point bare die is all that a test item does not pass through, and in these unacceptable regions, there is the regular bare die tested and passed through,
And after being retested to the wafer, as shown in Fig. 2, these it is regular test the bare die that passes through be shown as testing it is obstructed
It crosses, to capture the test abnormal case that test passes through.
The CP test of wafer is one of test after wafer manufacture is completed, to the device feature of each bare die on wafer
And other design specifications are verified, the result i.e. yield of test, are that chip design side judges product quality
Important evidence.In multidigit parallel testing, multiple bare dies are put down and contacted simultaneously to probe card, and tester table sends out primary test
The test of multiple bare die, the corresponding bare die of a bit test can be completed in signal.In the wafer figure (wafer of test result
Map on), different test results is indicated with different colors, when all for by when, usually with green show the bare die, when it
In certain bit test occur abnormal, especially when passing through result extremely for test, that is, unacceptable bare die quilt should be tested
Test for test pass through, this and other normal through bare die all shown as green, it is different by this kind to be difficult the On-Wafer Measurement stage
Often, this bare die that will lead to failure is not screened out, obtains false wafer yield.
Utility model content
In view of the above-mentioned deficiencies in the prior art, the purpose of the utility model is to provide a kind of wafer test system,
The wafer test system uses the structure of pretest device and wafer tester, not only guarantees the proper testing shape of tester table
State, moreover it is possible to ensure the accuracy of the wafer test of subsequent progress, and then obtain true wafer yield.
In order to reach above-mentioned technical purpose, the technical scheme adopted by the utility model is
A kind of wafer test system, the wafer test system include tester table, pretest device, flash chip, crystalline substance
Circle test device and probe card；Wherein, tester table is connected with each other pretest device, flash chip, wafer tester and spy
Needle card, pretest device connect flash chip, and flash chip connects wafer tester；
The tester table is located at the top of wafer tester, and for loading wafer to be tested, statistical analysis wafer is surveyed
Try data；
The wafer to be tested that the probe card is used to be in probe card the lifting status stage carries out the wafer of different directions
Pretest, when wafer pretest is that probe card is in lifting status, tester table sends prediction trial signal to pretest device, in advance
Test device starting carries out wafer test to wafer to be measured；
When the pretest device is in lifting status for probe card, tester table issues prediction trial signal, described pre-
Test device treats test wafer and carries out the pretest of multi-bit parallel wafer；
Flash chip storage wafer pretest data and wafer test data, and judge to obtain from pretest device
Wafer pretest data, when flash chip determine wafer pretest data markers be it is obstructed out-of-date, to wafer tester issue
Test signal；
After the wafer tester receives the test signal that flash chip is sent, treats test wafer and carry out multidigit simultaneously
Row wafer test, and tester table is sent by wafer test data.
Preferably, the probe card is multidigit probe card.
Preferably, the pretest device is integrated circuit or chip.
Preferably, the wafer tester is integrated circuit or chip.
The utility model is due to using above-mentioned pretest device, flash chip, wafer tester, tester table and spy
The structure of needle card, beneficial effect obtained are that the wafer test system first carries out before carrying out formal wafer test
The wafer pretest of wafer to be tested, in wafer pretest, probe card is in lifting status, and tester table is then normally sent out pre-
Test signal, and carry out multi-bit parallel wafer pretest, when flash chip determine wafer pretest data markers be it is obstructed out-of-date,
Wafer tester just treats test wafer and carries out multi-bit parallel wafer test, and sends test machine for wafer test data
Platform can't return to effective test result since probe card is in lifting status, can export test under normal circumstances and not pass through
Test result, illustrate that tester table is in normal test mode, so that it is guaranteed that the wafer of the subsequent progress of wafer tester
The accuracy of test, and then obtain true wafer yield.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is this
Some embodiments of utility model, for those of ordinary skill in the art, without creative efforts, also
Other drawings may be obtained according to these drawings without any creative labor.
Fig. 1 shows the abnormality test wafer figure of a wafer.
The test wafer figure after exception is removed after resurveying Fig. 2 shows the wafer in Fig. 1.
Fig. 3 is the wafer test system structural block diagram of the utility model specific implementation.
Specific embodiment
To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, with reference to the accompanying drawing to this
The specific embodiment of utility model is described in detail.
Many details are explained in the following description in order to fully understand the utility model, but this is practical new
Type can also be implemented using other than the one described here other way, and those skilled in the art can be without prejudice to this reality
With doing similar popularization in the case where novel intension, therefore the utility model is not limited by the specific embodiments disclosed below.
It is shown in Figure 3, for the wafer test system structural block diagram of the utility model specific implementation.The wafer test system
System includes tester table 100, pretest device 200, flash chip 300, wafer tester 400 and probe card 500；Wherein,
Tester table 100 is connected with each other pretest device 200, flash chip 300, wafer tester 400 and probe card 500, prediction
200 connection flash chips 300 are set in trial assembly, and flash chip 300 connects wafer tester 400；
The tester table 100 is located at the top of wafer tester 400, for loading wafer to be tested, statisticallys analyze
Wafer test data；
The wafer to be tested that the probe card 500 is used to be in probe card 500 the lifting status stage carries out different directions
Wafer pretest, wafer pretest is probe card when be in lifting status, and tester table 100 is to the transmission of pretest device 200
Predict trial signal, the starting of pretest device 200 carries out wafer test to wafer to be measured；
When the pretest device 200 is in lifting status for probe card 500, tester table 100 issues pretest letter
Number, the pretest device 200 treats test wafer and carries out the pretest of multi-bit parallel wafer；
The flash chip 300 stores wafer pretest data and wafer test data, and judges from pretest device 200
The wafer pretest data of acquisition, when flash chip 300 determine wafer pretest data markers be it is obstructed out-of-date, to wafer test
Device 400 issues test signal；
After the wafer tester 400 receives the test signal that flash chip 300 is sent, test wafer progress is treated
Multi-bit parallel wafer test, and tester table 100 is sent by wafer test data.
Further, the probe card 500 is multidigit probe card.
Further, the pretest device 200 is integrated circuit or chip.
Further, the wafer tester 400 is integrated circuit or chip.
When the wafer test system On-Wafer Measurement, tester table carries out wafer test, and wafer test includes a plurality of
Test item, each test item include a kind of test, and test item such as quiescent current, dynamic current etc. is produced according to different designs
Product, the quantity of test item is different in wafer test option, such as can have the test item of tens or up to a hundred, these surveys
Examination item is successively tested, and a test item passes through the test for then continuing next test item, and when a certain test item does not pass through, then display should
The failure of test item, and when the test of all test items all passes through, then the test result of bare die is to pass through.Wherein, probe card
It is the test interface between tester table and wafer, after probe card is put down, is contacted with the liner (PAD) of the bare die on wafer,
It will be sent to bare die from the test signal of tester table, to realize the test of each parameter of bare die.
The pretest is that wafer test is carried out before formal wafer test, and wafer pretest is that probe card is in always
Lifting status, but tester table normally sends prediction trial signal to pretest device, and pretest device treats test wafer progress
Wafer test.That is, the prediction trial signal that tester table is sent out is not through probe card and is sent to bare die, in this way, sending
Prediction trial signal out is unable to complete the test of each parameter of bare die, therefore, under normal circumstances, it may appear that test is unacceptable
Test result, on the contrary, can carry out subsequent wafer test if there is the test result that test passes through, then be abnormal feelings
There is exception in condition, that is, test, then without carrying out subsequent wafer test, improve testing efficiency, while avoiding testing different
The inaccuracy of the yield often resulted in is to obtain true yield.
When carrying out the wafer test of wafer to be tested, that is, when carrying out formal wafer test, during the test, probe
Card, which is put down, to be pricked into the liner of bare die, and the test signal that wafer tester receives flash chip sending is sent into bare die, with
Proper testing is carried out, and is had since testing process carried out pretest before, pretest is by then indicating at tester table state
It will be greatly enhanced in the authenticity of normal condition, the result of subsequent wafer test.
The crystal round test approach is particularly suitable for the multi-bit parallel test of wafer, and multi-bit parallel test is once to test
In, multiple bare dies are put down and contacted simultaneously to probe card, and tester table, which sends out primary test signal, can be completed multiple bare die
Test, wherein the corresponding bare die of a bit test, multi-bit parallel is tested such as 64,128,256, in multi-bit parallel
In test, the test result of each bit test is all obstructed out-of-date in multidigit test, then it is assumed that the test result of pretest is not
Pass through, think at this time tester table state be it is normal, formal wafer test can be continued；And work as in multidigit test at least
The test result for having a bit test is when passing through, then it is assumed that the test result of pretest is to pass through, and then thinks tester table at this time
State is exception, stops formal wafer test, then, can carry out the investigation of abnormality, such as can carry out tester table
Calibration, maintenance and/or test signal investigation etc..Tester table tests multidigit when this method can obtain multi-bit parallel test
The consistency of signal, thus, the accuracy of multi-bit parallel test is greatly improved, the appearance for avoiding test abnormal.
In specific application, it can according to need to determine wafer pretest option, which can be with
It is the partial test item selected in formal wafer test option, more fully, which can be formal wafer
Test option is directly tested using the option condition of tester table without retesting condition, is only set probe card
It sets in lifting status, in this way, without the option condition for increasing and changing tester table, while improving test accuracy.
In more preferably embodiment, multiple pretest can be carried out, when the test result of multiple pretest is all not pass through
When, then it is assumed that the test result of pretest is not pass through, in this way, the accuracy of pretest can be improved.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is system corresponding with embodiment of the method, so describing fairly simple, related place is referring to method reality
Apply the part explanation of example.
The above is only the preferred embodiment of the utility model, although the utility model is disclosed with preferred embodiment
As above, it however is not intended to limit the utility model.Anyone skilled in the art is not departing from the utility model skill
In the case of art aspects, many all is made to technical solutions of the utility model using the methods and technical content of the disclosure above
Possible changes and modifications or equivalent example modified to equivalent change.Therefore, all without departing from the utility model technical side
The content of case, according to the technical essence of the utility model it is made to the above embodiment it is any it is simple modify, equivalent variations and
Modification, still fall within technical solutions of the utility model protection in the range of.
Claims (3)
1. a kind of wafer test system, which is characterized in that the wafer test system includes tester table, pretest device, dodges
Deposit chip, wafer tester and probe card；Wherein, tester table is connected with each other pretest device, flash chip, wafer test
Device and probe card, pretest device connect flash chip, and flash chip connects wafer tester；
The tester table is located at the top of wafer tester, for loading wafer to be tested, statisticallys analyze wafer test number
According to；
The wafer that the wafer to be tested that the probe card is used to be in probe card the lifting status stage carries out different directions is predicted
Examination, when wafer pretest is that probe card is in lifting status, tester table sends prediction trial signal, pretest to pretest device
Device starting carries out wafer test to wafer to be measured；
When the pretest device is in lifting status for probe card, tester table issues prediction trial signal, the pretest
Device treats test wafer and carries out multi-bit parallel wafer test；
The flash chip storage wafer pretest data and wafer test data, and judge the wafer obtained from pretest device
Pretest data, when flash chip determine wafer pretest data markers be it is obstructed out-of-date, to wafer tester issue test
Signal；
After the wafer tester receives the test signal that flash chip is sent, treats test wafer and carry out multi-bit parallel crystalline substance
Circle test, and tester table is sent by wafer test data.
2. wafer test system according to claim 1, which is characterized in that the probe card is multidigit probe card.
3. wafer test system according to claim 1, which is characterized in that the pretest device is integrated circuit or core
Piece.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822053580.7U CN209000871U (en) | 2018-12-07 | 2018-12-07 | A kind of wafer test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201822053580.7U CN209000871U (en) | 2018-12-07 | 2018-12-07 | A kind of wafer test system |
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| CN209000871U true CN209000871U (en) | 2019-06-18 |
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| CN201822053580.7U Active CN209000871U (en) | 2018-12-07 | 2018-12-07 | A kind of wafer test system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504000A (en) * | 2019-08-26 | 2019-11-26 | 上海华力集成电路制造有限公司 | The method that wafer-level test identifies probe card information with test machine |
| CN110687430A (en) * | 2019-09-18 | 2020-01-14 | 四川豪威尔信息科技有限公司 | Integrated circuit wafer test optimization method |
| CN111293048A (en) * | 2018-12-07 | 2020-06-16 | 紫光同芯微电子有限公司 | Wafer test system and method thereof |
-
2018
- 2018-12-07 CN CN201822053580.7U patent/CN209000871U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293048A (en) * | 2018-12-07 | 2020-06-16 | 紫光同芯微电子有限公司 | Wafer test system and method thereof |
| CN111293048B (en) * | 2018-12-07 | 2024-07-02 | 紫光同芯微电子有限公司 | Wafer testing system and method thereof |
| CN110504000A (en) * | 2019-08-26 | 2019-11-26 | 上海华力集成电路制造有限公司 | The method that wafer-level test identifies probe card information with test machine |
| CN110504000B (en) * | 2019-08-26 | 2021-04-13 | 上海华力集成电路制造有限公司 | Method for identifying probe card information of wafer-level test tester |
| CN110687430A (en) * | 2019-09-18 | 2020-01-14 | 四川豪威尔信息科技有限公司 | Integrated circuit wafer test optimization method |
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Effective date of registration: 20201124 Address after: 100083 18 / F, building 4, yard 1, Wangzhuang Road, Haidian District, Beijing Patentee after: ZIGUANG TONGXIN MICROELECTRONICS Co.,Ltd. Patentee after: TANGSHAN GUOXIN JINGYUAN ELECTRONICS Co.,Ltd. Address before: 100083 Beijing City, Haidian District Wudaokou Wangzhuang Road No. 1 Tongfang Technology Plaza D floor 18 West Patentee before: ZIGUANG TONGXIN MICROELECTRONICS Co.,Ltd. |