CN208655651U - Buried word line structure and memory - Google Patents
Buried word line structure and memory Download PDFInfo
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- CN208655651U CN208655651U CN201821533453.0U CN201821533453U CN208655651U CN 208655651 U CN208655651 U CN 208655651U CN 201821533453 U CN201821533453 U CN 201821533453U CN 208655651 U CN208655651 U CN 208655651U
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Abstract
本实用新型涉及集成电路领域，提供了一种埋入式字线结构及存储器。所述埋入式字线结构包括具有沟槽的基底以及形成于沟槽中的字线，沟槽包括沿深度方向相互连通的第一沟槽和第二沟槽，其中第二沟槽远离基底表面，且第二沟槽的平均宽度大于第一沟槽的平均宽度，即字线的下端较上端宽，有助于减小字线的电阻以及减小尖端聚集效应，在用作存储器的晶体管时，有利于晶体管的可靠性。所述存储器包括上述埋入式字线结构。
The utility model relates to the field of integrated circuits, and provides an embedded word line structure and a memory. The buried word line structure includes a substrate having a trench and a word line formed in the trench, the trench includes a first trench and a second trench communicated with each other in a depth direction, wherein the second trench is away from the substrate surface, and the average width of the second trench is greater than the average width of the first trench, that is, the lower end of the word line is wider than the upper end, which helps to reduce the resistance of the word line and reduce the tip aggregation effect. is beneficial to the reliability of the transistor. The memory includes the buried word line structure described above.
Description
Technical field
The utility model relates to integrated circuit fields, in particular to a kind of embedded type word line structure and include the embedment
The memory of formula word line structure.
Background technique
DRAM (Dynamic Random Access Memory), i.e., dynamic RAM is in relatively conventional system
It deposits, wherein each storage unit (cell) includes a transistor and a corresponding capacitor, utilizes capacitor memory storage lotus
Number represents 0 and 1, in order to avoid charge deficiency leads to corrupt data, needs periodically to refresh capacitor.To promote DRAM's
Integrated level is to accelerate the service speed to each storage unit, and reply comes from the markets such as PC, smart phone, plate to DRAM
Solid demand, developed in recent years embedded type word line DRAM (i.e. buried word line DRAM) structure to meet on
State demand.
In embedded type word line DRAM structure, embedded type word line is formed in substrate and intersects with the active area in substrate,
To which part wordline may be used as the grid of the transistor of storage unit, the source-drain area of transistor is formed in the lining of the grid two sides
In bottom.But although being improved using the integrated level of current technique DRAM, embedded type word line contacts down with substrate
Hold width smaller, it is sharper, cause word line resistance value greatly and tip building-up effect is obvious, causes the Performance And Reliability of transistor
It is poor.
Utility model content
Transistor performance existing for the embedded type word line DRAM structure formed for current technique and reliability is poor asks
Topic, the utility model provide a kind of embedded type word line structure and the memory comprising the embedded type word line structure, purpose
It is the resistance value for reducing wordline and the reliability for improving transistor.
One aspect according to the present utility model provides a kind of embedded type word line structure, comprising:
Substrate has groove in the substrate, and the groove extends along the direction for being parallel to the substrate surface, the ditch
Slot includes the first groove and second groove being interconnected along depth direction, wherein the second groove is far from the substrate table
Face, and the mean breadth of the second groove is greater than the mean breadth of the first groove；And it is formed in the groove
Wordline, the wordline fill up first groove described in the second groove and fill part.
Optionally, the embedded type word line structure further include:
Gate dielectric layer, the gate dielectric layer are covered in the inner wall of the groove to separate the wordline and the substrate；
And coating, the coating cover the wordline and fill up the first groove.
Optionally, the first groove includes opposite the first side wall and second sidewall, the first side wall and described
Two side walls are parallel to each other.
Optionally, along perpendicular to the groove extend direction, the section of the second groove include the circle of non-close,
One of oval, rectangular, trapezoidal, pentagon, hexagon or two or more combinations.
Optionally, the material of the wordline include metal, metal silicide, metal nitride, conduction polysilicon group
At one of group or two or more combinations.
Another aspect according to the present utility model also provides a kind of memory, including above-mentioned embedded type word line structure.
Embedded type word line structure provided by the utility model includes having fluted substrate and being formed in the groove
Wordline, the groove include along depth direction be interconnected first groove and second groove, wherein the second groove is remote
From substrate surface, and the mean breadth of the second groove is greater than the mean breadth of the first groove, that is, is filled in substrate
Wordline lower end it is wide compared with upper end, be used as memory transistor grid when, facilitate reduce tip building-up effect, improve
The reliability of transistor.Also, embedded type word line structure provided by the utility model is larger with the contact area of substrate, thus
The resistance value that can reduce wordline is conducive to the service speed for improving memory when being used as memory.
Memory provided by the utility model includes above-mentioned embedded type word line structure, thus is had and above-mentioned embedded type word line
The same or like advantage of structure.
Detailed description of the invention
Fig. 1 is a kind of diagrammatic cross-section of the embedded type word line structure of memory.
Fig. 2 is the flow chart of the forming method of the embedded type word line structure of the utility model embodiment.
Fig. 3 is the forming method according to the embedded type word line structure of the utility model embodiment after forming first groove
Diagrammatic cross-section.
Fig. 4 is to form the second mask material according to the forming method of the embedded type word line structure of the utility model embodiment
Diagrammatic cross-section after layer.
Fig. 5 is after forming the second mask layer according to the forming method of the embedded type word line structure of the utility model embodiment
Diagrammatic cross-section.
Fig. 6 is to form second groove according to the forming method of the embedded type word line structure of the utility model one embodiment
Diagrammatic cross-section afterwards.
Fig. 6 a to Fig. 6 c is the forming method according to the embedded type word line structure of the utility model other embodiments in shape
At the diagrammatic cross-section after second groove.
Fig. 7 is to remove first mask according to the forming method of the embedded type word line structure of the utility model embodiment
Diagrammatic cross-section after layer and second mask layer.
Fig. 8 according to the embedded type word line structure of the utility model embodiment forming method cuing open after forming gate dielectric layer
Face schematic diagram.
Section of the Fig. 9 according to the forming method of the embedded type word line structure of the utility model embodiment after forming conductive layer
Schematic diagram.
Figure 10 is forming method the cuing open after forming wordline according to the embedded type word line structure of the utility model embodiment
Face schematic diagram.
Figure 11 is the forming method according to the embedded type word line structure of the utility model embodiment after forming coating
Diagrammatic cross-section.
Figure 11 a to Figure 11 c is the diagrammatic cross-section of the embedded type word line structure of the utility model other embodiment.
Description of symbols:
100,200: substrate；101: wordline groove；
110,210: wordline；120,220: isolation structure；
201: first groove；201a: bottom wall；
201b: side wall；201b-1: the first side wall；
201b-2: second sidewall；202: pad oxide；
203: the first mask layers；230: the second layer of mask material；
204: the second mask layers；205: second groove；
206: gate dielectric layer；207: conductive layer；
208: coating.
Specific embodiment
As stated in the background art, although being improved using the integrated level of current embedded type word line technique DRAM,
Be wordline lower end width it is smaller sharper so that word line resistance be worth larger and tip building-up effect it is obvious, influence the property of transistor
Energy and reliability.Fig. 1 is a kind of diagrammatic cross-section of the embedded type word line structure of memory.Referring to Fig.1, it is formed in substrate 100
There is wordline groove 101, wordline 110 is formed in wordline groove 101, and wordline 110 extends along the surface for being parallel to substrate 100,
When as memory, can also have active area (not shown) and the isolation structure for limiting active area regions in substrate 100
120, the part that wordline 110 intersects with active area may be used as the source electrode of the transistor of memory, and present inventor studies hair
It is existing, as shown in Figure 1, the bottom width of wordline groove 101 of the technique by once etching formation is usually relatively narrow at present, or even have
Apparent tip, thus the lower end for the wordline 110 being filled in wordline groove 101 also relatively narrow sharper namely wordline lower end song
Rate is larger, and the density of surface charge between the grid of transistor and channel can be made higher, causes this part wordline lower end
Field strength is stronger, makes transistor that can generate apparent tip building-up effect, less reliable.Also, sharper lower end be easy so that
The resistance value of the grid of wordline and transistor is excessive, increases power consumption and the response time of transistor, leads to degradation.
Current embedded type word line technique and be formed by embedded type word line structure there are aiming at the problem that, the utility model mentions
A kind of embedded type word line structure, and the memory comprising the embedded type word line structure are supplied, it is therefore an objective to improve transistor
Performance and reliability.
Make below in conjunction with embedded type word line structure and memory of the drawings and specific embodiments to the utility model further
It is described in detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It should be noted that attached drawing is all made of
Very simplified form and use non-accurate ratio, only to it is convenient, lucidly aid in illustrating the utility model embodiment
Purpose.It should be understood that in the following description, can be carried out based on attached drawing about the reference in each layer "up" and "down".But
It should be understood that spatially relative term is intended to comprising using or operating other than orientation of the device described in figure
In different direction.For example, if the device in attached drawing is squeezed or with the positioning of other different modes (as rotated), it is exemplary
Term " ... on " also may include " ... under " and other position relations.When layer, region, pattern or structure are referred to as
When substrate, layer, region and/or pattern "upper", it can be on another layer or substrate, and/or there may also be insert
Enter layer.Similar, when layer is referred to as at another layer of "lower", it can be under another layer, and/or can also deposit
In one or more insert layers.
The utility model embodiment includes a kind of forming method of embedded type word line structure.Fig. 2 is that the utility model is implemented
The flow chart of the forming method of the embedded type word line structure of example.Referring to Fig. 2, the forming method of the embedded type word line structure includes
Following steps:
S1: forming first groove in substrate, and the first groove extends along the direction for being parallel to the substrate surface, institute
First groove is stated with bottom wall interconnected and side wall, the substrate surface is covered with the first mask layer；
S2: the second mask layer is formed in the first groove, second mask layer covers the side wall and exposes
The bottom wall；
S3: the substrate is etched to form second groove in the substrate along the bottom wall, the second groove is put down
Equal width is greater than the mean breadth of the first groove；
S4: first mask layer and second mask layer are removed；
S5: wordline is formed in the first groove and the second groove, the wordline fills up the second groove simultaneously
First groove described in fill part；
S6: coating is formed in the first groove, the coating covers the wordline and fills up the first groove.
Fig. 3 to Figure 11 shows according to the section of the forming method of embedded type word line structure shown by the utility model embodiment
It is intended to.Make furtherly below in conjunction with forming method of the Fig. 2 to Figure 11 to the embedded type word line structure of the utility model embodiment
It is bright.
Fig. 3 is the forming method according to the embedded type word line structure of the utility model embodiment after forming first groove
Diagrammatic cross-section.Referring to Fig. 2 and Fig. 3, step S1 is first carried out, forms first groove 201 in substrate 200, first ditch
Slot 201 extends along the direction for being parallel to 200 surface of substrate, and the first groove 201 has bottom wall 201a interconnected
With side wall 201b, 200 surface of substrate is covered with the first mask layer 203.
In the present embodiment, substrate 200 is, for example, silicon base.Multiple first grooves 201 can be formed in substrate 200, also,
It may also be formed with multiple isolation structures 220 in substrate 201.Isolation structure 220 is, for example, fleet plough groove isolation structure (STI), each
Spacer medium (the example that isolation structure 220 includes the isolated groove formed in substrate 200 and fills in the isolation trench
Silica in this way).
First mask layer 203 is covered in 200 surface of substrate, in the present embodiment, on 200 surface of substrate and the first mask layer
Pad oxide 202 is also formed between 203.The forming method of first groove 201 may include following procedure: sink on a substrate 200
Product laying (belonging to same film layer with pad oxide 202) and the first layer of mask material (belong to same with the first mask layer 203
Film layer)；In one layer photoresist of upper surface spin coating of the first layer of mask material, it is exposed developing process by mask later,
The photoresist for corresponding to first groove region in substrate is opened, is then that mask is carved downwards using the photoresist with patterns of openings
Erosion, lithographic method are, for example, plasma dry etching, by first layer of mask material of part in corresponding first groove region and portion
Point laying etches opening, then using with patterns of openings the first layer of mask material and laying as mask, continue to etch
Substrate 200, to form first groove 201 in substrate 200.Remaining laying can be used as above-mentioned pad oxide 202, material
Material e.g. silica, remaining first layer of mask material can be used as the first mask layer 203, and material is, for example, silicon nitride, but
Without being limited thereto, the material of the first mask layer 203 is also possible to oxide USG (undoped silicate glass, undoped silicon
Glass), BPSG (borophosphosilicate glass, boron-phosphorosilicate glass), BSG (Pyrex), PSG (phosphorosilicate glass),
The combination of one or more of TEOS (tetraethoxysilane, silester).First layer of mask material and
The forming method of laying includes chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD), atomic layer deposition (ALD), highly dense
Spend plasma CVD (HDPCVD), metallorganic CVD (MOCVD), plasma enhanced CVD (PECVD) or other suitable depositions
Technique, in addition, laying (by taking silica as an example) can also utilize thermal oxide, RTA (rapid thermal annealing), ISSG (situ steam
Generate), DPN (decoupling pecvd nitride) or other suitable techniques are formed.Second mask layer described below, gate medium
Layer also can use similar deposition method production, thus the formation to embedded type word line structure below with film layers such as dielectric layers
In the description of method, the deposition method of each film layer will not be described again.
First groove 201 along be parallel to 200 surface of substrate direction extend, so as to in substrate 200 be located at be isolated
Active area intersection between structure 220.The first groove 201 has bottom wall 201a interconnected and side wall 201b.This reality
It applies in example, the side wall 201b of the first groove 201 includes opposite the first side wall 201b-1 and second sidewall 201b-2, described
The first side wall 201b-1 and the second sidewall 201b-2 are parallel to each other.But not limited to this, in other embodiments, the first side wall
201b-1 and second sidewall 201b-2 is also possible to not parallel.
In the utility model embodiment, aggregation effect in tip is caused in order to avoid the lower end width for the wordline being subsequently formed is too narrow
It answers, continues to etch the bottom wall 201a of first groove 201 using individual etching technics, thus the first groove that step S1 is formed
201 depth is less than the lower end depth of wordline to be formed.
Fig. 4 is to form the second mask material according to the forming method of the embedded type word line structure of the utility model embodiment
Diagrammatic cross-section after layer.Fig. 5 is to form second according to the forming method of the embedded type word line structure of the utility model embodiment
Diagrammatic cross-section after mask layer.Referring to Fig. 2, Fig. 4 and Fig. 5, step S2 is executed, forms the second mask layer 204 in first groove
201, second mask layer 204 covers the side wall 201b of first groove 201 and exposes bottom wall 201a.
As an example, the forming process of the second mask layer 204 specifically may include following sub-step:
Firstly, referring to Fig. 4, the second layer of mask material 230 is formed in substrate 200 and in first groove 201, described second
Layer of mask material 230 is conformally covered in the surface of first mask layer 203 and the side wall 201b and bottom wall of first groove 201
201a.The material of second layer of mask material 230 is, for example, silicon nitride.It " conformally covers " herein and refers to that the covered surface in edge is suitable
It deposits to answering property, alternatively referred to as conformal (conformal) covering.
Then, the second layer of mask material 230 is etched using Self-aligned etching technique referring to Fig. 5, with the corresponding covering of removal
In the second layer of mask material of part 230 of the bottom wall 201a of first groove 201, using remaining second layer of mask material 230 as
Second mask layer 204 of the present embodiment.The Self-aligned etching technique uses anisotropic dry method etch technology.
Fig. 6 is to form second groove according to the forming method of the embedded type word line structure of the utility model one embodiment
Diagrammatic cross-section afterwards.Referring to Fig. 6, step S3 is executed, the bottom wall 201a along first groove 201 etches substrate 200, to form the
For two grooves 205 in substrate 200, the mean breadth of the second groove 205 is greater than the mean breadth of the first groove 201.
To, second groove 205 and first groove 201 are interconnected, and the surface at 201 linker bottom 200 of first groove is opposite, the
Two surfaces of the groove 205 far from substrate 200.After forming second groove 205 below bottom wall 201a, the position of first groove 201
Setting can be determined by the first side wall 201b-1 and second sidewall 201b-2.
Etch the bottom wall 201a and formed the second groove 205 method can using wet etching process and/or
Dry method etch technology, for wet etching process, the etching liquid of use can be acid etching liquid or alkaline etch bath.For example,
In one embodiment of the utility model, etches the bottom wall 201a and the acid etching liquid including highly acid substance is utilized,
Such as including HNO3And HF, so that the inner wall for being formed by second groove 205 is cambered surface, as shown in Figure 6.And it is practical at this
In other novel embodiments, etches the bottom wall 201a and the alkaline etch bath including alkaline matter is utilized, such as wherein
Including NH4OH and/or KOH, the alkaline etch bath can also include TMAH ((CH3)4NOH) etching liquid.By adjusting the alkali
The concentration of property substance, can form the second groove 205 of different size and inner wall shape.Second groove 205 can also be by multiple
Etching technics is formed.It is appreciated that either dry method etch technology or wet etching process, should have can be conditioned
Etching parameter, such as etching solution (or etching gas) used, etch temperature, etching solution (or etching gas) concentration, etching
Pressure, power, RF bias voltage, RF bias power, etching solution (or etching gas) flow velocity and other suitable parameters,
To obtain the size and shape of second groove 205 described in the utility model embodiment.
Fig. 6 a to Fig. 6 c is the forming method according to the embedded type word line structure of the utility model other embodiments in shape
At the diagrammatic cross-section after second groove, it is formed by other embodiments of the utility model referring to Fig. 6 a to Fig. 6 c
Second groove 205 can be the rectangle (such as Fig. 6 a) of non-close, arcuate oblong shape along the section perpendicular to its extending direction (such as
Fig. 6 b) or it is trapezoidal (such as Fig. 6 c).But the utility model is without being limited thereto, in some other embodiment of the utility model, along vertical
Directly in the direction that first groove 201 or second groove 205 extend, the section of second groove 205 can also be five sides of non-close
Shape, hexagon etc., it is preferred that the section of second groove 205 can be the circle of non-close, ellipse, rectangular, trapezoidal, five sides
One of shape, hexagon or two or more combinations.
In the utility model embodiment, the mean breadth by the step S3 second groove 205 formed is greater than first groove
201 mean breadth." mean breadth " also refers to first groove 201 or second groove 205 perpendicular to its extension herein
The average distance of both sides of the edge on direction, for example, second groove 205 can be made to exist by the etching technics of rate-determining steps S3
It is parallel to 200 surface of substrate and the direction far from the first side wall 201b-1 and second sidewall 201b-2 to extend a distance into, to increase
Add the mean breadth of second groove 205.On the depth direction of second groove 205, the bottom wall depth of second groove 205 is substantially true
The lower surface position of subsequent wordline to be formed is determined.
Fig. 7 is to remove first mask according to the forming method of the embedded type word line structure of the utility model embodiment
Diagrammatic cross-section after layer and second mask layer.Referring to Fig. 7, step S4 is executed, removes above-mentioned first mask layer 203 and the
Two mask layers 204.It specifically can use dry method etch technology or wet etching process, such as can use the quarter including phosphoric acid
Lose the first mask layer 203 and the second mask layer 204 of liquid wet process removal silicon nitride material.After executing step S4, it can retain
Pad oxide 202 positioned at 200 surface of substrate, with 200 surface of protecting group bottom.
Fig. 8 according to the embedded type word line structure of the utility model embodiment forming method cuing open after forming gate dielectric layer
Face schematic diagram.Fig. 9 according to the embedded type word line structure of the utility model embodiment forming method cuing open after forming conductive layer
Face schematic diagram.Figure 10 is forming method the cuing open after forming wordline according to the embedded type word line structure of the utility model embodiment
Face schematic diagram.Referring to Fig. 2 and Fig. 8 to Figure 10, step S5 is executed, forms wordline 210 in first groove 201 and the second groove
In 205, the wordline 201 fills up first groove 201 described in the second groove 205 and fill part.
As an example, forming wordline 201 specifically may include following procedure:
Firstly, referring to Fig. 8, gate dielectric layer 206 is formed in first groove 201 and second groove 205, the gate dielectric layer
206 are conformally covered in the inner wall of the first groove 201 and the second groove 205.The material of gate dielectric layer 206 is, for example,
Silica.
Then, referring to Fig. 9, conductive layer 207 is formed in the gate dielectric layer surface, the conductive layer 207 covers gate medium
First groove 201 and second groove 205 are simultaneously filled up in 206 surface of layer.In some embodiments of the utility model, conductive layer is being formed
Before 207, a lining (not shown) is selectively initially formed in 206 surface of gate dielectric layer, the material of lining is, for example, titanium nitride
Or conductive polysilicon etc..The material of conductive layer 207 can be selected from metal (such as tantalum, titanium, molybdenum, tungsten, platinum, aluminium, hafnium, ruthenium), gold
Belong to silicide (such as titanium silicide, cobalt silicide, nickle silicide, tantalum silicide), metal nitride (such as titanium nitride, tantalum nitride), conduction
Polysilicon composed by group one or more of.Conductive layer 207 can also be covered in 202 surface of pad oxide.
Then, referring to Fig.1 0, it is etched back to conductive layer 207, remaining conductive layer 207 is made to be only filled with part first groove 201,
That is, the upper surface of remaining conductive layer 207 is made to keep certain distance away from 200 surface of substrate.After being etched back to, correspond to
Remaining conductive layer in second groove 205 and part first groove 201 can be used as the present embodiment flush type word to be formed
The wordline 210 of cable architecture.
Figure 11 is the forming method according to the embedded type word line structure of the utility model embodiment after forming coating
Diagrammatic cross-section.Referring to Fig. 2 and Figure 11, the forming method of the embedded type word line structure of the present embodiment may also include step S6, shape
At coating 208 in first groove 201, the coating 208 covers the wordline 210 and fills up the first groove 201.It covers
The material of cap rock 208 may include silicon nitride, silica, silicon oxynitride, other insulating materials or their combination.Coating
208 can also extend in 200 surface of substrate.
From the above, it can be seen that the forming method of the embedded type word line structure according to the present embodiment, is formed by
The mean breadth of two grooves 205 is greater than the mean breadth of first groove 201, to be filled in second groove 205 and fill part
The lower end of wordline 210 obtained from first groove 201 is wider compared with upper end.For wordline 110 as shown in Figure 1, utilize
The above-mentioned forming method of the present embodiment is formed by wordline 210 with lesser resistance value, is being used as the transistor of memory
When grid, be conducive to reduce tip building-up effect, improve the reliability of transistor, and improve the service speed of memory.
The utility model embodiment further includes a kind of embedded type word line structure.Referring to Fig.1 1, the embedded type word line structure
Including the wordline 210 in substrate 200 and the groove being formed in substrate 200, the groove edge is parallel to 200 surface of substrate
Direction extends, and the groove includes the first groove 201 and second groove 205 being interconnected along depth direction, wherein described the
Two grooves 205 are far from 200 surface of substrate, and the mean breadth of second groove 205 is greater than the average width of the first groove 201
Degree；The wordline 210 fills up second groove 205 and fill part first groove 201." depth direction " refers to the first ditch herein
The depth direction of slot (or second groove), the i.e. direction perpendicular to 200 surface of substrate." mean breadth " refers to the first ditch herein
Slot (or second groove) is perpendicular to the average distance between the both sides of the edge on its extending direction.
Specifically, multiple above-mentioned grooves filled with wordline 210 can be formed in substrate 200.It can also shape in substrate 200
At there is isolation structure 220, for limiting the active area in substrate 200.As an example, the same active area can be with two wordline
210 intersections.When being used for memory such as DRAM, the active area in substrate 200 can be formed with transistor, thus and active area
The part wordline 210 of intersection can be used as the grid of the transistor.
The first groove 201 may include opposite the first side wall 210b-1 and second sidewall 201b-2 (referring to Fig. 7), institute
State the first side wall 210b-1 and the second sidewall 201b-2 be parallel to each other, i.e., along perpendicular to first groove 201 extend direction,
The section of first groove 201 can be rectangle (opposite both sides are unclosed).In the same plane, the section of second groove 205
It can be the circle of non-close, tip building-up effect can be reduced significantly.In the utility model other embodiment, along vertical
Directly in second groove 205 extend direction, the section of second groove 205 may also include the circle of non-close, ellipse, it is rectangular,
One of trapezoidal, pentagon, hexagon or two or more combinations.Figure 11 a to Figure 11 c is the utility model other
The diagrammatic cross-section of the embedded type word line structure of embodiment.1a to Figure 11 c referring to Fig.1 is implemented in the utility model other
In the embedded type word line structure of example, the section of second groove 205 is also possible to the rectangle of non-close, ellipse or trapezoidal,
Forming method can use the same or similar method of forming method with aforementioned embedded type word line structure.
1 and Figure 11 a to Figure 11 c referring to Fig.1, above-mentioned embedded type word line structure further include gate dielectric layer 206 and coating
208, the gate dielectric layer 206 configures the inner wall surface in first groove 201 and second groove 205, by wordline 210 and substrate
200 separate.The material of gate dielectric layer 206 is, for example, silica, silicon oxynitride or high-k dielectric material.The material example of wordline 210
Tungsten in this way.Coating 208 covers the wordline 210 and fills up the first groove 201 (such as coating 208 is filled with first
Groove 201 is filling the remaining space after a part of wordline 210) with formed in isolation word line 210 and substrate 200 other are conductive
Structure.The material of coating 208 may include one of silicon nitride, silica, silicon oxynitride, other insulating materials or they
Combination.
In the embedded type word line structure of the utility model embodiment, the mean breadth of second groove 205 is greater than first groove
201 mean breadth is being used as memory so that the lower end for being formed by wordline 210 is wider (having biggish lower end)
When the grid of transistor, helps to reduce tip building-up effect, improve the reliability of transistor.Also, due under wordline 210
End is wider, thus the situation relatively narrow compared with lower end is compared, and wordline 210 and the contact area of substrate become larger, so as to reduce wordline
210 resistance value is conducive to the service speed for improving memory.
The utility model embodiment further includes a kind of memory, including above-mentioned embedded type word line structure.The memory example
Such as with the structure of DRAM.Specifically, 1 and Figure 11 a to Figure 11 c, the memory may include being formed in substrate 200 referring to Fig.1
In a plurality of wordline 210, part of or whole wordline 210 can have the wordline shape in above-mentioned embedded type word line structure,
Multiple active areas are also provided in substrate 200, each active area is formed at least one transistor, with control corresponding capacitor into
Row charge storage.A plurality of wordline 210 intersects with active area, and separates corresponding source region and drain region, thus, be located at the source region and
Part wordline between drain region can be used as the grid of transistor in memory.Due to the wordline 210 that is embedded in substrate 200
Lower end is wider, is conducive to the resistance value for reducing wordline, and reduce or avoid being formed about tip building-up effect in grid, can be with
The reliability of transistor is improved, and is conducive to improve the service speed of memory.
It should be noted that the embodiment in this specification is described in a progressive manner, each embodiment is stressed
Be all difference with previous embodiment, identical and similar place may refer to each other between each embodiment.
Foregoing description is only the description to the utility model preferred embodiment, is not appointed to the utility model interest field
What is limited, and anyone skilled in the art without departing from the spirit and scope of the utility model, may be by the disclosure above
Methods and technical content possible variation and modification are made to technical solutions of the utility model, it is therefore, all without departing from this reality
With the content of new technique scheme, any simple modification made by the above technical examples according to the technical essence of the present invention,
Equivalent variations and modification belong to the protection scope of technical solutions of the utility model.
Claims (6)
1. a kind of embedded type word line structure characterized by comprising
Substrate has groove in the substrate, and the groove extends along the direction for being parallel to the substrate surface, the groove packet
Include along depth direction be interconnected first groove and second groove, wherein the second groove far from the substrate surface, and
The mean breadth of the second groove is greater than the mean breadth of the first groove；And
The wordline being formed in the groove, the wordline fill up first groove described in the second groove and fill part.
2. embedded type word line structure as described in claim 1, which is characterized in that further include:
Gate dielectric layer, the gate dielectric layer are covered in the inner wall of the groove to separate the wordline and the substrate；And
Coating, the coating cover the wordline and fill up the first groove.
3. embedded type word line structure as described in claim 1, which is characterized in that the first groove includes the first opposite side
Wall and second sidewall, the first side wall and the second sidewall are parallel to each other.
4. embedded type word line structure as described in claim 1, which is characterized in that the direction that edge extends perpendicular to the groove,
The section of the second groove include one of the circle of non-close, ellipse, rectangular, trapezoidal, pentagon, hexagon or
Two or more combinations.
5. embedded type word line structure as described in claim 1, which is characterized in that the material of the wordline includes metal, metal
Silicide, metal nitride, conduction polysilicon composed by group one of or two or more combinations.
6. a kind of memory, which is characterized in that including embedded type word line structure such as described in any one of claim 1 to 5.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931486A (en) * | 2018-09-19 | 2020-03-27 | 长鑫存储技术有限公司 | Embedded word line structure, forming method thereof and memory |
| WO2021109580A1 (en) * | 2019-12-06 | 2021-06-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11056175B1 (en) | 2020-07-28 | 2021-07-06 | Winbond Electronics Corp. | Semiconductor device and manufacturing method thereof |
-
2018
- 2018-09-19 CN CN201821533453.0U patent/CN208655651U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931486A (en) * | 2018-09-19 | 2020-03-27 | 长鑫存储技术有限公司 | Embedded word line structure, forming method thereof and memory |
| WO2021109580A1 (en) * | 2019-12-06 | 2021-06-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11056175B1 (en) | 2020-07-28 | 2021-07-06 | Winbond Electronics Corp. | Semiconductor device and manufacturing method thereof |
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