CN111508841A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising the following steps: providing a semiconductor substrate with an active area formed on the surface; forming a groove on the semiconductor substrate and forming a source/drain connected to the groove on the opposite sides of the groove; forming a gate in the groove, and forming a gate dielectric layer between the gate and the groove; partially removing the gate dielectric layer between the gate and the source/drain overlapping area; depositing an isolation layer above the gate to form a closed gap layer between the gate and the source/drain overlapping area. The present invention reduces the gate-drain voltage and effectively suppresses the gate-induced drain leakage current by introducing a gap layer to replace the gate dielectric layer in the gate-drain overlapping area of the transistor, thereby improving the device reliability and reducing the device power consumption, so that the data storage and read-write performance of the DRAM device are improved.

Description

Semiconductor structure and method of making the same

technical field

The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

DRAM (Dynamic Random Access Memory), namely dynamic random access memory, is a widely used storage device. As the requirements for DRAM storage capacity continue to increase, the device density per unit area of the wafer increases and the design feature size decreases. In order to ensure that DRAM devices continue to operate for hours, the data retention time and refresh characteristics of memory cells can still meet the design requirements. In the design of DRAM devices, the development and optimization of word line structures are an important part of it.

Currently, in the existing DRAM word line structure, there is a gate oxide layer between the gate metal layer and the drain doped region in the gate-drain overlap region for isolation. When the gate-drain voltage of the gate-drain overlap region is large, the electrons in the silicon substrate near the interface of the overlap region undergo band-to-band tunneling between the valence band and the conduction band, thereby forming a drain Current, namely gate-induced drain leakage current (GIDL, gate-induced drain leakage). The gate-induced drain leakage current will become more significant as the device size decreases and the gate oxide is thinned. Excessive gate-induced drain leakage current will reduce the reliability of the device and increase the power consumption of the device, which will adversely affect the data storage and reading and writing of the DRAM device.

Therefore, it is necessary to propose a new semiconductor structure and a manufacturing method thereof to solve the above problems.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the problem that the reliability and power consumption of semiconductor devices are affected by excessive gate-induced drain leakage current in the prior art. The problem.

In order to achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, which is characterized in that it includes the following steps:

providing a semiconductor substrate, the surface of which forms an active region;

A trench is provided on the active region, and source/drain is formed on opposite sides of the trench, and the source/drain is connected to the trench;

A gate is formed in the trench, and a gate dielectric layer is further formed between the gate and the trench;

partially removing the gate dielectric layer between the gate electrode and the source/drain overlap region;

An isolation layer is deposited over the gate to form a closed void layer between the gate and the source/drain overlap region.

As an optional solution of the present invention, the bottom of the void layer is at least not lower than the bottom of the source/drain.

As an optional solution of the present invention, the top of the gate is higher than the bottom of the source/drain and lower than the top of the trench.

As an optional solution of the present invention, the top of the void layer is at least not higher than the top of the gate.

As an optional solution of the present invention, the top of the isolation layer is flush with the top of the trench; the bottom of the isolation layer is flush with the top of the gate.

As an optional solution of the present invention, the semiconductor substrate includes a P-type semiconductor substrate, and the source/drain includes an N-type doped source/drain.

The present invention also provides a semiconductor structure, comprising:

a semiconductor substrate, an active region is formed on the surface of the semiconductor substrate;

a trench, located on the active region, the opposite sides of the trench are respectively formed with source/drain, and the source/drain is connected to the trench;

a gate located in the trench;

a gate dielectric layer, located between the gate and the trench, the top of the gate dielectric layer is lower than the top of the gate;

an isolation layer, located above the gate;

A void layer is formed between the gate electrode and the source/drain overlap region, and is located above the gate dielectric layer.

As an optional solution of the present invention, the bottom of the void layer is at least not lower than the bottom of the source/drain.

As an optional solution of the present invention, the top of the gate is higher than the bottom of the source/drain and lower than the top of the trench.

As an optional solution of the present invention, the top of the void layer is at least not higher than the top of the gate.

As described above, the present invention provides a semiconductor structure and a manufacturing method thereof. By introducing a void layer in the gate-drain overlap region of a transistor to replace the gate dielectric layer, the gate-drain voltage is reduced and gate-induced drain leakage is effectively suppressed. Therefore, the reliability of the device is improved, the power consumption of the device is reduced, and the data storage and read/write performance of the DRAM device are improved.

Description of drawings

FIG. 1 is a top view of the semiconductor structure obtained by the method for fabricating the semiconductor structure provided in the first embodiment of the present invention.

2 to 10 are cross-sectional views of each step in the manufacturing method for providing a semiconductor structure according to Embodiment 1 of the present invention at aa' of FIG. 1 .

11 to 12 are cross-sectional views of the semiconductor structure provided in the second embodiment of the present invention taken at aa' of FIG. 1 .

Component label description

100 Semiconductor substrates

100a active area

100b Shallow Trench Isolation Structure

101 Source/Drain

102 Groove

103 gate dielectric layer

104 grid

104a gate material layer

105 isolation layer

105a Isolation material layer

106 void layer

106a void groove

107 Hard mask layer

107a Hard mask material layer

108 Gate-Drain Overlap

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 to 12. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, although the diagrams only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the shape, quantity and proportion of each component can be arbitrarily changed during actual implementation, and the component layout shape may also be more complicated.

Example 1

Referring to FIG. 1 to FIG. 10 , the present embodiment provides a method for fabricating a semiconductor structure, including the following steps:

A semiconductor substrate 100 is provided, and an active region is formed on the surface of the semiconductor substrate 100;

A trench 102 is provided on the active region, and source/drain 101 are respectively formed on opposite sides of the trench 102, and the source/drain 101 is connected to the trench 102;

A gate electrode 104 is formed in the trench 102, and a gate dielectric layer 103 is further formed between the gate electrode and the trench;

Partially remove the gate dielectric layer 103 between the gate electrode 104 and the source/drain 101 overlapping region;

An isolation layer 105 is deposited over the gate electrode 104 to form a closed void layer 106 between the gate electrode 104 and the overlapping region of the source/drain 101 .

As shown in FIG. 1 , it is a top view of the semiconductor structure obtained by the manufacturing method of the semiconductor structure provided in this embodiment. 2 to 11 are cross-sectional views at aa' of FIG. 1 of each step in the manufacturing method of the semiconductor structure provided in this embodiment.

As an example, as shown in FIGS. 1 to 4 , the semiconductor structure in this embodiment includes a buried word line structure applied to a DRAM device. A plurality of active regions 100a and a shallow trench isolation structure 100b separating the active regions are formed on the semiconductor substrate 100; the source/drain 101 is formed on the active region 100a; the trenches 102 It is formed on the active region 100a and the shallow trench isolation structure 100b and communicates with a plurality of the active regions 100a. It should be noted that the semiconductor substrate 100 covered by the active region 100a and the STI structure 100b is not shown in FIG. 1 , and the STI structure is not shown in FIGS. 2 to 4 . Structure 100b. In this embodiment, a plurality of active regions 100a and a shallow trench isolation structure 100b separating the active regions 100a are formed on the semiconductor substrate 100, and an ion implantation process is performed on the active regions 100a. Source/drain 101 is formed. Optionally, the semiconductor substrate 100 includes a P-type silicon substrate, the source/drain 101 includes N-type doped source/drain, and the shallow trench isolation structure 100b includes a silicon dioxide layer. In this embodiment, the source/drain 101 is formed by doping on the active region 100a at the same time, and can be further classified into source or drain according to the connection relationship in the transistor structure, as shown in FIG. 11 . As shown, the source/drain 101 connected to the bit line on the left side of the trench in the figure is the source electrode, and the source/drain 101 connected to the capacitor on the right side of the trench is the drain electrode. As shown in FIG. 1 , the active regions 100a are periodically arranged on the semiconductor substrate 100 at certain intervals, and the formed trenches 102 laterally pass through a plurality of the active regions 100a and between the active regions 100a. the shallow trench isolation structure 100b between. By forming word line structures in the trenches 102, the word line structures are connected to several of the active regions 100a.

As an example, as shown in FIGS. 2 to 4 , the process of forming the trench 102 on the semiconductor substrate 100 includes the following steps:

forming a hard mask material layer 107a on the semiconductor substrate 100, as shown in FIG. 2;

A patterned hard mask layer 107 is formed by photolithography and etching, as shown in FIG. 3 ;

Using the hard mask layer 107 as an etching mask, the trench 102 is formed by dry etching, as shown in FIG. 4 .

In this embodiment, before the trench 102 is formed, the source/drain 101 and the shallow trench isolation structure 100b have been formed on the semiconductor substrate 100. Therefore, the hard mask material layer 107a is deposited on the semiconductor substrate 100. The source/drain 101 and the upper surface of the shallow trench isolation structure 100b are shown in FIG. 2 . Optionally, the hard mask material layer 107a includes a silicon dioxide layer. By performing photolithography and etching on the hard mask material layer 107a, a patterned hard mask layer 107 is obtained, as shown in FIG. 3 . The trench 102 formed by dry etching penetrates the source/drain 101 and contacts the semiconductor substrate 100, that is, the bottom of the trench 102 is at least lower than the bottom of the source/drain 101, as shown in FIG. 4 shown. In FIG. 4, the trench 102 separates the source/drain 101 into a source on the left and a drain on the right. It should be noted that the present invention does not limit the formation sequence of the trench 102 , the source/drain 101 and the shallow trench isolation structure 100b. For example, in other embodiments, the trench 102 may be formed on the semiconductor substrate 100 first, a sacrificial layer may be introduced to cover the trench 102, and then the trench 102 may be formed on the semiconductor substrate 100 by ion implantation. The source/drain 101. In addition, in addition to the silicon dioxide layer, the hard mask material layer 107a may also include an amorphous carbon layer formed on the upper layer, so as to improve the etching selectivity ratio during dry etching, and be removed after dry etching Residual of the amorphous carbon layer.

As an example, as shown in FIG. 5 , a gate dielectric layer 103 is formed on the surface of the trench 102 . Optionally, the gate dielectric layer 103 includes a silicon dioxide layer, and the method for forming the silicon dioxide layer includes using a furnace tube thermal oxidation process to grow silicon dioxide on the sidewalls and the silicon material at the bottom of the trench 102 silicon layer. In this embodiment, since other positions except the surface of the trench 102 are covered by the silicon dioxide layer, the furnace tube thermal oxidation process is only performed on the silicon material on the surface of the trench 102 The silicon dioxide layer is generated.

As an example, as shown in FIGS. 6 to 7 , the process of forming the gate 104 in the trench 102 includes the following steps:

depositing a gate material layer 104a in the trench 102, the gate material layer 104a at least filling the trench 102;

Part of the gate material layer 104a in the trench 102 is removed by etchback, and the remaining part of the gate material layer 104a forms the gate 104, and the top of the gate 104 is higher than the source/ The bottom of the drain 101 is lower than the top of the trench 102 .

Optionally, as shown in FIG. 6 , a gate material layer 104 a is deposited on the hard mask layer 107 and in the trenches 102 through a process such as chemical vapor deposition or atomic layer deposition. The gate material layer 104a includes a tungsten metal layer. In FIG. 6, part of the gate material layer 104a on the hard mask layer 107 and in the trench 102 is removed by an etch-back process, and the remaining part at the bottom of the trench 102 forms the gate 104, as shown in FIG. 7 . The etch-back process can be selected from dry etching or wet etching.

In addition, as an optional solution of this embodiment, before depositing the gate material layer 104a, an adhesion layer, such as a titanium nitride layer, may be deposited first, so as to improve the connection between the gate material layer 104a and the gate material layer 104a. The bonding performance of the gate oxide layer on the surface of the trench 102 can be prevented to prevent delamination and cracking. In FIG. 7 , when part of the gate material layer 104a is removed by etching back, the adhesion layer under the part of the gate material layer 104a is also removed at the same time.

As an example, as shown in FIG. 8 , the method for removing part of the gate dielectric layer 103 on the sidewall of the trench 102 includes dry etching or wet etching, and the gate dielectric layer 103 is removed by etching. The top is lower than the top of the gate 104 . Optionally, the gate dielectric layer 103 includes a silicon dioxide layer, and the dry etching method can use CF-based gas such as CF ₄ and CHF ₃ as the etching gas to perform isotropic etching, or can use DHF and other drugs. liquid to wet-etch the silicon dioxide layer. During the etching process, the exposed part of the gate dielectric layer 103 located at the upper part of the sidewall of the trench 102 is removed by etching, and as the etching proceeds, the gate material layer 104a and the trench Part of the gate dielectric layer 103 between the sidewalls of the trench 102 will also be removed by etching, and a trench structure is formed between the source/drain 101 , the gate electrode 104 and the gate dielectric layer 103 , It is defined as void trench 106a in the present invention. In FIG. 8 , one of the gap trenches 106 a is formed on the left and right sides of the gate 104 .

It should be noted that, in this embodiment, the bottom of the void trench 106 a is higher than the top of the source/drain 101 . That is, the void trench 106a does not extend into the semiconductor substrate 100 underlying the source/drain 101 . The semiconductor substrate 100 and the gate electrode 104 are also isolated by the gate dielectric layer 103, that is, the silicon dioxide layer. In other embodiments of the present invention, the void trench 106a may also further extend into the semiconductor substrate 100 under the source/drain 101 , that is, between the semiconductor substrate 100 and the gate 104 . Part of the area between is isolated by the void trench 106a. The above differences determine the composition of the gate-drain overlap region and the isolation dielectric of part of the channel region of the transistor structure obtained in the present invention. The choice of the isolation dielectric will affect the gate-induced drain leakage current and switching characteristics of the transistor. performance has an important impact. In this embodiment, the isolation dielectric in the channel region will be entirely composed of a silicon dioxide gate dielectric layer, which ensures that the resulting device has better switching characteristics.

As an example, as shown in FIG. 9 to FIG. 10 , the process of forming the isolation layer 105 over the gate 104 includes the following steps:

depositing an isolation material layer 105a on the surface of the hard mask layer 107 and above the gate electrode 104 in the trench 102;

The isolation material layer 105a on the surface of the hard mask layer 107 is removed, and the isolation layer 105 is formed on the part of the isolation material layer 105a remaining in the trench 102, and the source/drain 101, the A void layer 106 is formed between the gate electrode 104 and the gate dielectric layer 103 .

Optionally, the top of the void layer 106 is at least not higher than the top of the gate 104 . This ensures that the void layer 106 only exists between the gate electrode 104 and the source/drain 101 , and does not intrude upward into the isolation layer 105 , thereby affecting the isolation effect of the isolation layer 105 .

Optionally, an isolation material layer 105 a is deposited on the surface of the hard mask layer 107 and above the gate electrode 104 in the trench 102 by chemical vapor deposition or atomic layer deposition, etc., the isolation material layer 105 a A silicon nitride layer is included, as shown in Figure 9. The isolation material layer 105 a on the surface of the hard mask layer 107 is removed by an etch-back process or chemical mechanical polishing, and the isolation layer 105 is formed in the part of the isolation material layer 105 a remaining in the trench 102 . Optionally, the etch-back process or chemical mechanical polishing further removes the hard mask layer 107 , and finally the top of the isolation layer 105 is flush with the surface of the source/drain 101 , as shown in FIG. 10 . .

Specifically, when depositing the isolation material layer 105 a above the gate electrode 104 in the trench 102 , it is necessary to ensure that the void trench 106 a will not be filled due to the deposition of the isolation material layer 105 a , so as to form a void layer 106 between the source/drain 101 , the gate electrode 104 and the gate dielectric layer 103 . Therefore, when the isolation material layer 105a is deposited by chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD) with high deposition rate and relatively weak step coverage can be used, so that When the isolation material layer 105a has not yet been deposited in the void trench 106a or the isolation material layer 105a is less deposited, the top of the void trench 106a has been sealed and closed due to deposition. The void layer 106 is formed there. Since the gate dielectric layer 103 is relatively thin in the transistor structure, and the opening of the gap trench 106a formed by the gate dielectric layer 103 is also small, the gap can be completely realized by using the existing deposition process. The isolation material layer 105a is not or less deposited in the trenches 106a. Optionally, when the isolation material layer 105a is a silicon nitride layer, the silicon nitride layer and the silicon substrate on the sidewall of the trench 102 may have stress problems, and the sidewall of the trench 102 may be first A pad oxide layer is deposited on the wall to improve the stress problem. The thickness of the pad oxide layer is much smaller than the thickness of the gate dielectric layer 103 and does not affect the formation of the void layer 106 .

It should be noted that, what is shown in FIG. 10 is the case where the isolation material layer 105a is not deposited in the void trench 106a in this embodiment. In other embodiments of the present invention, a thin layer of the isolation material layer 105a may be deposited on the sidewall and bottom of the void trench 106a based on a deposition process, and a thin layer of the isolation material layer 105a is deposited in the middle of the void trench 106a. The void layer 106 is formed at the position, but this does not affect the technical effect achieved by the present invention. In addition, in other embodiments of the present invention, a sacrificial material layer may be filled in the void trench 106a first, and then the isolation material layer 105a may be deposited. After the isolation material layer 105a is deposited, the sacrificial material layer is removed by a dry or wet etching process. This solution can also prevent the isolation material layer 105a from being deposited in the void trench 106a at all.

The void layer 106 introduced in the present invention may be a vacuum layer, an air layer or other low dielectric constant gas filled layers. The vacuum layer is an ideal low-k dielectric layer, the relative permittivity of vacuum is 1.0, and the relative permittivity of air (~1.0006) is very close to that of vacuum. When used as low-k media, the performance of the two is similar. Therefore, in the present invention, the void layer 106 is not specifically limited to a vacuum layer or an air layer. If the influence of selecting a vacuum layer or an air layer on the reliability of the device structure is also considered, when the void layer 106 is an air layer, there may be a risk of affecting the device performance due to thermal expansion of the air or moisture contained in the air. Therefore, as an optional solution, when depositing the isolation material layer 105a, a deposition process such as PECVD under vacuum conditions can be selected to keep the vacuum in the void layer, so as to further improve the stability of the obtained device. The deposition process and process parameters also need to be optimized and selected according to the actual needs of device design to ensure that while reducing the relative dielectric constant of the isolation dielectric in the gate-drain overlap region, it will not affect the performance and reliability of the resulting semiconductor device. .

Embodiment 2

This embodiment provides a semiconductor structure, as shown in FIG. 1 and FIG. 10 , the semiconductor structure includes:

A semiconductor substrate 100, an active region is formed on the surface of the semiconductor substrate 100;

The trench 102 is located on the active region, and the opposite sides of the trench 102 are formed with source/drain 101 respectively, and the source/drain 101 is connected to the trench 102;

gate 104, located in the trench 102;

The gate dielectric layer 103 is located between the gate electrode 104 and the trench 102, and the top of the gate dielectric layer 103 is lower than the top of the gate electrode 104;

The isolation layer 105 is located above the gate 104;

A void layer 106 is formed between the overlapping region of the gate electrode 104 and the source/drain 101, and is located above the gate dielectric layer 103;

As shown in FIG. 1 , it is a top view of the semiconductor structure provided in this embodiment. Fig. 10 is a cross-sectional view at aa' of Fig. 1 of the semiconductor structure provided in this embodiment. Optionally, the semiconductor structure in this embodiment can be obtained according to the manufacturing method of the semiconductor structure described in the first embodiment.

As an example, as shown in FIGS. 1 and 10, the semiconductor structure includes a buried word line structure applied to a DRAM device. The semiconductor substrate 100 further includes a plurality of active regions 100a and a shallow trench isolation structure 100b separating the active regions 100a; the source/drain 101 is located on the upper surface of the active region 100a; the trenches The trenches 102 are located on the active region 100a and the shallow trench isolation structure 100b and communicate with a plurality of the active regions 100a. It should be noted that the semiconductor substrate 100 covered by the active region 100a and the shallow trench isolation structure 100b is not shown in FIG. 1 , and the shallow trench isolation structure 100b is not shown in FIG. 10 . Optionally, the semiconductor substrate 100 includes a P-type semiconductor substrate, such as a P-type silicon substrate, and the source/drain 101 includes N-type doped source/drain. As shown in FIG. 1 , the active regions 100a are periodically arranged on the semiconductor substrate 100 at certain intervals, and the formed trenches 102 laterally pass through a plurality of the active regions 100a and between the active regions 100a. the shallow trench isolation structure 100b between. By forming word line structures in the trenches 102, the word line structures are connected to several of the active regions 100a.

As an example, as shown in FIG. 10 , the gate 104 includes a tungsten layer, the gate dielectric layer 103 includes a silicon dioxide layer, the isolation layer 105 includes a silicon nitride layer, and the void layer 106 includes a vacuum layer or air layer.

As an example, as shown in FIG. 10 , the top of the gate 104 is higher than the bottom of the source/drain 101 and lower than the top of the trench 102 .

As an example, as shown in FIG. 10 , the top of the void layer 106 is at least not higher than the top of the gate 104 .

As an example, as shown in FIG. 10 , the bottom of the void layer 106 is at least not lower than the bottom of the source/drain 101 . In this embodiment, as shown in FIG. 10 , most of the space above the gate-drain overlap region 108 is formed by the void layer 106 , and a portion of the space near the bottom of the source/drain 101 is still reserved. Gate dielectric layer 103 . This not only ensures that the gate-drain leakage current of the gate-drain overlap region 108 is improved by introducing the void layer 106, but also ensures that the gate dielectric layer 103 is still used for isolation in the channel region, and has good switching characteristics . Optionally, the bottom of the void layer 106 is flush with the bottom of the source/drain 101 , and the isolation medium of the gate-drain overlap region 108 is completely constituted by the void layer 106 . In this case, the gate-drain overlap region 108 will have better resistance to gate-induced drain leakage current.

In this embodiment, by defining that the top of the gate 104 is at least not higher than the bottom of the source/drain 101, and the top of the second gate 105 is higher than the bottom of the source/drain 101, the The gate material at the gate-drain overlap region 108 is entirely composed of the second gate 105 , that is, composed of a polysilicon layer instead of a tungsten metal layer. This will significantly reduce the gate-induced drain leakage current generated at the gate-drain overlap region 108 .

As shown in FIG. 11, it is the buried word line structure provided by the present invention, wherein most of the isolation dielectric at the gate-drain overlap region 108 is formed by the void layer 106, and the source/drain 101 is N type doping, the semiconductor substrate 100 is a P-type silicon substrate. When the transistor is turned off and the DRAM stores data, the gate of the word line remains negatively biased and the drain of the capacitor connected to the right end is positively biased. At this time, the gate-to-drain voltage will be the maximum possible for the device. As shown in FIG. 12 , when the isolation dielectric at the gate-drain overlap region 108 is completely composed of the gate dielectric layer 103 , that is, the silicon dioxide layer, at a higher gate-drain voltage, the gate-drain voltage will appear in FIG. 12 . A large amount of gate-induced drain leakage current is generated in the direction of the arrow. However, in the buried word line structure provided by the present invention in FIG. 11, since the silicon dioxide layer is partially replaced by the void layer 106, when the transistor is turned off, the gate at the gate-drain overlap region 108 The drain voltage will be greatly reduced, which will greatly reduce the gate-induced drain leakage current at the gate-drain overlap region 108, and even avoid the generation of the gate-induced drain leakage current. By improving the characteristics of the gate-induced drain leakage current at the gate-drain overlap region 108 of the DRAM memory cell, the reliability and read/write performance of the DRAM device can be significantly improved and the power consumption when the device is turned off can be reduced. It should be pointed out that although this embodiment illustrates the advantages of the semiconductor structure provided by the present invention in improving the gate-induced drain leakage current when the semiconductor structure is applied to the DRAM buried word line structure, it does not limit the advantages provided by the present invention. Scope of application of semiconductor structures. The present invention can significantly improve the gate-induced drain leakage current caused by the gate-drain voltage in other transistor structures.

In summary, the present invention provides a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure includes the following steps: providing a semiconductor substrate, an active region is formed on the surface of the semiconductor substrate; A trench is formed on the semiconductor substrate, the trench penetrates the active region and the bottom of the trench is lower than the bottom of the active region; a gate dielectric layer is formed on the surface of the trench; A gate is formed in the trench, and the top of the gate is higher than the bottom of the active region and lower than the top of the trench; part of the gate dielectric layer on the sidewall of the trench is removed to make The top of the gate dielectric layer is lower than the top of the gate; an isolation layer is formed over the gate, the isolation layer fills up the space above the gate in the trench, and is located on the A void layer is formed between the source region, the gate electrode and the gate dielectric layer. The semiconductor structure includes: a semiconductor substrate, an active area is formed on the surface of the semiconductor substrate; a trench is located on the semiconductor substrate, the trench penetrates the active area and the trench is the bottom is lower than the bottom of the active region; the gate is located in the trench, the top of the gate is higher than the bottom of the active region and lower than the top of the trench; the gate dielectric layer, between the gate and the semiconductor substrate, the top of the gate dielectric layer is lower than the top of the gate; the void layer is located between the active region, the gate and the gate dielectric layer between; an isolation layer, located above the gate, filling the space above the gate in the trench. The invention reduces the gate-drain voltage and effectively suppresses the gate-induced drain leakage current by introducing a void layer in the gate-drain overlap region of the transistor to replace the gate dielectric layer, thereby improving the reliability of the device and reducing the power consumption of the device. The data storage and read/write performance of the DRAM device have been improved.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising the steps of:

providing a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate;

arranging a groove on the active region, and respectively forming an active/drain on opposite side edges of the groove, wherein the active/drain is connected to the groove;

forming a grid electrode in the groove, and forming a grid dielectric layer between the grid electrode and the groove;

partially removing the gate dielectric layer between the gate and the source/drain overlapping region;

and depositing an isolation layer above the grid electrode so as to form a closed gap layer between the grid electrode and the source/drain overlapping region.

2. The method of claim 1, wherein a bottom of said void layer is at least not lower than said source/drain bottom.

3. The method as claimed in claim 1, wherein the top of the gate is higher than the bottom of the source/drain and lower than the top of the trench.

4. The method of claim 1, wherein a top of said spacer layer is at least no higher than a top of said gate.

5. The method of claim 1, wherein a top of said isolation layer is flush with a top of said trench; the bottom of the isolation layer is flush with the top of the gate.

6. The method of claim 1, wherein said semiconductor substrate comprises a P-type semiconductor substrate and said source/drain comprises an N-type doped source/drain.

7. A semiconductor structure, comprising:

the semiconductor device comprises a semiconductor substrate, wherein an active region is formed on the surface of the semiconductor substrate;

a trench on the active region, opposite sides of the trench having a source/drain formed thereon, respectively, the source/drain being connected to the trench;

a gate located in the trench;

the gate dielectric layer is positioned between the gate and the groove, and the top of the gate dielectric layer is lower than that of the gate;

the isolation layer is positioned above the grid;

and the gap layer is formed between the grid electrode and the source/drain overlapping region and is positioned above the grid dielectric layer.

8. The semiconductor structure of claim 7, wherein said voided layer has a bottom that is at least not lower than said source/drain bottom.

9. The semiconductor structure of claim 7, wherein the top of said gate is higher than the bottom of said source/drain and lower than the top of said trench.

10. The semiconductor structure of claim 7, wherein the top of said spacer layer is at least no higher than the top of said gate.

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