CN207690795U - Semiconductor device - Google Patents

Abstract

The utility model relates to a semiconductor device, for an improve the packaging structure who dispels the heat and reduce the resistance. The semiconductor device includes a substrate, a wafer, a first clip and a second clip. The chip includes a first transistor and a second transistor with common drain, and the common drain is connected to the substrate. The first clamping piece is connected with the source electrode of the first transistor; the second clamping piece is connected with the source electrode of the second transistor, and the first clamping piece and the second clamping piece are electrically separated from each other.

Description

Semiconductor device

technical field

The utility model generally relates to a semiconductor device, and specifically, the utility model relates to a package structure of a common-drain transistor wafer.

Background technique

At present, most of the packaging structures of the existing common-drain integrated circuits use wire bonding to connect the pins of the integrated circuit and the contact pads of the chip to achieve electrical connection, so the heat dissipation effect is poor, and the resistance value is relatively high, which directly affects The source-to-source on-resistance (Rsson) of the chip. On the other hand, the Wafer Level Chip Scale Package (WLCSP) structure is to directly solder the chip on the printed circuit board. Although the size can be smaller and the component resistance is lower, it is not conducive to the process of surface mount technology. .

Utility model content

In view of the problems in the prior art, an object of the present invention is to provide a packaging structure of a semiconductor device with low on-resistance and high heat dissipation effect.

Another object of the present invention is to provide a semiconductor device, which uses a plurality of metal clips to respectively connect the source and the gate of the common-drain transistor chip, thereby effectively simplifying the manufacturing process.

Another object of the present invention is to provide a semiconductor device, which utilizes metal clips as the pins of the packaging structure to connect the sources of multiple transistors that are drained together, so as to improve the reliability of the electrical connection and the heat dissipation effect.

In one embodiment, the utility model provides a semiconductor device, which includes a substrate, a chip, a first clip and a second clip, the chip includes a first transistor and a second transistor with a common drain, and the common drain is connected to the substrate ; the first clip is connected to the source of the first transistor; the second clip is connected to the source of the second transistor, and the first clip and the second clip are electrically separated from each other.

In one embodiment, the semiconductor device of the present invention further includes an encapsulation material layer covering the chip, the first clip and the second clip on the substrate.

In one embodiment, the top surface of at least one of the first clip and the second clip is at least partially exposed outside the packaging material layer.

In one embodiment, at least one of the first clip and the second clip has a pin exposed outside the packaging material layer.

In one embodiment, the semiconductor device of the present invention further includes a third clip and a fourth clip, the third clip is connected to the gate of the first transistor, and the fourth clip is connected to the gate of the second transistor.

In one embodiment, the semiconductor device of the present invention further includes an encapsulation material layer covering the chip, the first clip, the second clip, the third clip and the fourth clip on the substrate.

In one embodiment, the top surface of at least one of the third clip and the fourth clip is at least partially exposed outside the packaging material layer.

In one embodiment, at least one of the third clip and the fourth clip has a pin exposed outside the packaging material layer.

In one embodiment, the semiconductor device of the present invention further includes a first wire and a second wire, the first wire is connected to the gate of the first transistor, and the second wire is connected to the gate of the second transistor.

In one embodiment, the semiconductor device of the present invention further includes a first contact portion and a second contact portion, and the first clip and the second clip are respectively connected to the first contact portion and the second contact portion to electrically connect the first transistor The source of the second transistor is connected to the first contact portion, and the source electrode of the second transistor is electrically connected to the second contact portion.

Compared with the prior art, the semiconductor device disclosed in the present invention uses clips to electrically connect the sources and/or gates of the two transistors that share the drain, so that all the clips can be made in one process. The connection is completed, the process steps are simplified, the source-source on-resistance (Rsson) of the chip is effectively improved, and the heat dissipation effect is improved. Furthermore, the semiconductor device disclosed in the utility model can directly use the part of the clip as the pin of the package structure, reducing the welding position of the electrical connection, and can also effectively improve the open circuit or electrical failure caused by poor welding in the prior art. Poor connection phenomenon.

The advantages and spirit of the present utility model can be further understood through the following detailed description of the utility model and the accompanying drawings.

Description of drawings

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 1A is a side view of an embodiment of the semiconductor device of FIG. 1 .

FIG. 1B is a side view of another embodiment of the semiconductor device of FIG. 1 .

FIG. 2 is a plan view of a semiconductor device according to another embodiment of the present invention.

FIG. 2A is a side view of an embodiment of the semiconductor device of FIG. 2 .

FIG. 2B is a side view of another embodiment of the semiconductor device of FIG. 2 .

FIG. 3 is a plan view of a semiconductor device according to another embodiment of the present invention.

FIG. 3A is a side view of an embodiment of the semiconductor device of FIG. 3 .

FIG. 3B is a side view of another embodiment of the semiconductor device of FIG. 3 .

FIG. 4 is a plan view of a semiconductor device according to another embodiment of the present invention.

FIG. 4A is a side view of an embodiment of the semiconductor device of FIG. 4 .

FIG. 4B is a side view of another embodiment of the semiconductor device of FIG. 4 .

Description of main component symbols:

1, 2, 3, 4 semiconductor devices

110 substrate

112 first contact part

114 second contact part

116 third contact part

118 fourth contact part

20 chips

22 common drain

210 first transistor

212 source

214 gate

220 second transistor

222 source

224 gate

31 first clip

312 vertical segments

314 horizontal section

316 top surface

32 second clip

322 vertical segments

324 horizontal sections

326 top surface

33 first wire

34 second wire

40, 40' layers of encapsulation material

41 third clip

42 fourth clip

51 first clip

512 pins

514 horizontal section

516 top surface

52 second clip

522 pins

524 horizontal sections

526 top surface

61 third clip

62 fourth clip

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. For the sake of simplifying the drawings, some common structures and components will be shown in a simple and schematic way in the drawings. In addition, elements/members with the same or similar numbers used in the drawings and embodiments are used to represent the same or similar parts. In the following embodiments, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements or specific materials , for example: colloid or solder.

As shown in FIG. 1 and FIG. 1A , in one embodiment, the semiconductor device 1 includes a substrate 110 , a wafer 20 , a first clip 31 and a second clip 32 . The chip 20 includes a first transistor 210 and a second transistor 220 having a common drain 22 , and the common drain 22 is connected to the substrate 110 . The first clip 31 is connected to the source 212 of the first transistor 210 , the second clip 32 is connected to the source 222 of the second transistor 220 , and the first clip 31 and the second clip 32 are electrically separated from each other.

Specifically, in the chip 20, the first transistor 210 and the second transistor 220 are preferably two metal-oxide-semiconductor field-effect transistors (MOSFETs) with the same size and a common drain 22, and the two metal-oxide-semiconductor field-effect transistors The source and gate are separated from each other. In other words, the source 212 and the gate 214 of the first transistor 210 are separated from the source and the gate 224 of the second transistor 220 . In this embodiment, the source 212 and gate 214 of the first transistor 210 and the source and gate 224 of the second transistor 220 are preferably located on the chip 20 with the common drains 22 of the first transistor 210 and the second transistor 220 respectively. the opposite surface. For example, the common drains 22 of the first transistor 210 and the second transistor 220 are located on the lower surface of the chip 20, and the source 212 and the gate 214 of the first transistor 210 and the source 222 and the gate 224 of the second transistor 220 are located at the lower surface of the chip 20. The upper surface of the wafer 20, so that the first transistor 210 and the second transistor 220 of the common drain 22 form a single semiconductor wafer structure.

The substrate 110 can be a lead frame, a bonding pad, or a contact plate electrically connected to the common drains 22 of the first transistor 210 and the second transistor 220 of the chip 20 . The chip 20 is disposed on the substrate 110 , and the common drains 22 of the first transistor 210 and the second transistor 220 are preferably electrically connected to the substrate 110 through, for example, a conductive adhesive layer (such as solder). The semiconductor device 1 further includes a first contact portion 112 , a second contact portion 114 , a third contact portion 116 and a fourth contact portion 118 . The first contact portion 112, the second contact portion 114, the third contact portion 116 and the fourth contact portion 118 can be connected to the source 212/222 and the gate 214/224 of the first transistor 210 and the second transistor 220 of the wafer 20. A lead frame, bonding pad, or contact plate forming an electrical connection, the first contact portion 112 is electrically connected to the source electrode 212 of the first transistor 210, the second contact portion 114 is electrically connected to the source electrode 222 of the second transistor 220, and the third contact portion 116 is electrically connected to the gate 214 of the first transistor 210 , and the fourth contact 118 is electrically connected to the gate 224 of the second transistor 220 .

Specifically, the first clip 31 is disposed on the first transistor 210 and the first contact portion 112 , so that the source 212 of the first transistor 210 can be electrically connected to the first contact portion 112 through the first clip 31 . In one embodiment, the first clip 31 can be electrically connected to the source 212 of the first transistor 210 through the conductive adhesive layer and can be electrically connected to the first contact portion 112 through the conductive adhesive layer.

Similarly, the second clip 32 is disposed on the second transistor 220 and the second contact portion 114 , so that the source 222 of the second transistor 220 can be electrically connected to the second contact portion 114 through the second clip 32 . In one embodiment, the second clip 32 can be electrically connected to the source 222 of the second transistor 220 through the conductive adhesive layer and can be electrically connected to the second contact portion 114 through the conductive adhesive layer, so that the second transistor The source 222 of 220 can be electrically connected to the second contact portion 114 through the second clip 32 .

For example, as shown in FIG. 1A , the first clip 31 and the second clip 32 are preferably pre-pressed metal clips, such as L-shaped copper sheets. The horizontal sections 314/324 of the first clip 31 and the second clip 32 are located on the source 212 of the first transistor 210 and the source 222 of the second transistor 220 respectively, and the first clip 31 and the second clip 32 The vertical segments 312 / 322 of the vertical segments extend downward toward the first contact portion 112 and the second contact portion 114 respectively. Thus, the horizontal section 314 of the first clip 31 can be electrically connected to the source 212 of the first transistor 210 through the conductive adhesive layer, and the vertical section 312 can be electrically connected to the first contact portion 112 through the conductive adhesive layer. . Similarly, the horizontal section 324 of the second clip 32 can be electrically connected to the source 212 of the second transistor 220 through the conductive adhesive layer, and the vertical section 322 can be electrically connected to the second contact portion 114 through the conductive adhesive layer. .

In this embodiment, the semiconductor device 1 further includes a first wire 33 and a second wire 34, the first wire 33 is connected to the gate 214 of the first transistor 210 and the third contact portion 116, and the first wire 34 is connected to the second transistor The gate 224 of 220 is connected to the fourth contact 118 . Thus, the third contact portion 116 is electrically connected to the gate 214 of the first transistor 210 , and the fourth contact portion 118 is electrically connected to the gate 224 of the second transistor 220 . In one embodiment, the first wire 33 and the second wire 34 are preferably copper wires, but not limited thereto.

In one embodiment, as shown in FIG. 1 and FIG. 1A , the semiconductor device 1 further includes an encapsulation material layer 40 to cover the chip 20 to prevent moisture or other substances from corroding or damaging the chip 20 . Specifically, the packaging material layer 40 covers the chip 20 , the first clip 31 , the second clip 32 , the first wire 33 and the second wire 34 on the substrate 110 . In this embodiment, the top surface 316 of the first clip 31 and the top surface 326 of the second clip 322 are completely covered by the packaging material layer 40, only the substrate 110, the first contact portion 112, the second contact portion 114, the second contact portion The third contact portion 116 and the fourth contact portion 118 are exposed outside the packaging material layer 40 .

In addition, the packaging material layer 40 can at least partially cover the first clip 31 and the second clip 32 . In one embodiment, as shown in FIG. 1B , the top surface 316, 326 of at least one of the first clip 31 and the second clip 32 is at least partially exposed outside the packaging material layer 40'. In other words, the packaging material layer 40' may expose the top surface 316 of the first clip 31, the top surface 326 of the second clip 32 or a combination thereof to assist the chip 20 to dissipate heat, but not limited thereto.

In another embodiment, as shown in FIG. 2 and FIG. 2A, the semiconductor device 2 further includes a third clip 41 and a fourth clip 42, the third clip 41 is connected to the gate 214 of the first transistor 210, and the fourth The clip 42 is connected to the gate 224 of the second transistor 220 . Specifically, the semiconductor device 2 uses the third clip 41 and the fourth clip 42 to replace the first wire 33 and the second wire 34 in the above embodiment, so that the gate 214 of the first transistor 210 is electrically connected through the third clip 41. The third contact portion 116 is connected, and the gate 224 of the second transistor 220 is electrically connected to the fourth contact portion 118 through the third clip 42 . For example, the third clip 41 and the fourth clip 42 can be pre-pressed metal clip structures similar to the above-mentioned first clip 31 and second clip 32 , such as L-shaped copper sheets. Thus, the horizontal section of the clip 41/42 can be electrically connected to the gate 214/224 of the transistor 210/220 through the conductive adhesive layer, and the vertical section of the clip 41/42 can be connected to the contact portion 116 through the conductive adhesive layer. /118 forms an electrical connection, so that the gate 214/224 of the transistor 210/220 can form an electrical connection with the contact portion 116/118 through the clip 41/42.

When the source 212 and the gate 214 of the first transistor 210 and the source 222 and the gate 224 of the second transistor 220 respectively use the first clip 31, the third clip 41, the second clip 32 and the fourth clip 42 When electrically connecting the first contact portion 112, the third contact portion 116, the second contact portion 114, and the fourth contact portion 118, all the connections can be completed by one clip manufacturing process without additional wire bonding process, which effectively simplifies Process steps.

Similarly, the packaging material layer 40 can cover the chip 20 , the first clip 31 , the second clip 32 , the third clip 41 and the fourth clip 42 on the substrate 110 to prevent moisture or other substances from affecting the chip 20 cause corrosion or damage. In one embodiment, as shown in FIG. 2A , the third clip 41 and the fourth clip 42 can be completely covered by the packaging material layer 40 . In another embodiment, as shown in FIG. 2B , the top surface of at least one of the third clip 41 and the fourth clip 42 may be at least partially exposed outside the packaging material layer 40'.

It should be noted here that according to practical applications, the encapsulation material layer 40 ′ may at least partially cover the first clip 31 , the second clip 32 , the third clip 41 and the fourth clip 42 , while exposing the first clip 31 , the partial surface of at least one of the second clamping piece 32 , the third clamping piece 41 and the fourth clamping piece 42 are not limited to those shown in the drawings.

Moreover, although the above-mentioned embodiment shows that the contact portions 112 , 114 are electrically connected by the clips 31 , 32 , the clips may have different designs. In another embodiment, as shown in FIG. 3 and FIG. 3A, the semiconductor device 3 includes a substrate 110, a third contact portion 116, and a fourth contact portion 118, but does not include the above-mentioned first contact portion 112 and second contact portion 114. . Correspondingly, the first clip 51 and the second clip 52 of the semiconductor device 3 replace the first clip 31 and the second clip 32 of FIG. pins. Specifically, the first clamping piece 51 and the second clamping piece 52 are Z-shaped copper pieces whose ends of the vertical section are bent and extended outward to form the pin portions 512 and 522 . For example, the horizontal section 514 of the first clip 51 is located on the source 212 of the first transistor 210, and the vertical section is bent downward from the end of the horizontal section 514 for a certain distance, and then bent outward and extended horizontally to form Pin portion 512 . The bottom surface of the pin portion 512 is preferably coplanar with the bottom surface of the substrate 110 . Similarly, the horizontal section 524 of the second clip 52 is located on the source 222 of the second transistor 220, and the vertical section bends downward from the end of the horizontal section 524 and extends for a certain distance, and then bends outward and extends horizontally to form a junction. Foot 522 . The bottom surface of the pin portion 522 is preferably coplanar with the bottom surface of the substrate 110 . When the packaging material layer covers the chip 20 , the first clip 51 and the second clip 52 , the pin portions 512 and 522 of the first clip 51 and the second clip 52 are exposed outside the packaging material layer 40 . Therefore, the welding between the clip and the contact portion can be avoided, which not only simplifies the manufacturing process, solves the problem of increased resistance caused by welding, but also improves the heat dissipation effect.

Similarly, as shown in FIG. 3B , not only the pin portions 512 and 522 of the first clip 51 and the second clip 52 are exposed on the lower surface of the packaging material layer 40 ′, but also the first clip 51 and the second clip 52 The top surfaces 516 and 526 are also partially exposed on the upper surface of the packaging material layer 40 ′, so that the heat dissipation effect is further improved.

In another embodiment, as shown in FIG. 4 and FIG. 4A , the difference from FIG. 3 is that the third clip 61 and the fourth clip 62 of the semiconductor device 4 replace the first wire 33 and the second wire 34 of FIG. 3 , and respectively have pin portions as pins of the semiconductor device 4 . Therefore, the welding between the clip and the contact portion can be avoided, which not only simplifies the manufacturing process, solves the problem of increased resistance caused by welding, but also improves the heat dissipation effect.

As shown in FIG. 4B , not only the pins of the third clip 61 and the fourth clip 62 can be exposed on the lower surface of the packaging material layer 40 ′, but the top surfaces of the third clip 61 and the fourth clip 62 are also partially exposed. On the upper surface of the encapsulation material layer 40 ′, the heat dissipation effect is further improved.

The utility model has been described by the above-mentioned embodiments, but the above-mentioned embodiments are only for illustration purposes and not for limitation. Those skilled in the art will appreciate that other modifications of the illustrated embodiments can be made to the embodiments specifically described herein without departing from the spirit of the present invention. Accordingly, the scope of the present invention also covers such modifications and is limited only by the appended claims.

Claims (10)

1. a kind of semiconductor device, which is characterized in that include：

One substrate；

One chip a, including the first transistor and a second transistor for drain altogether, the wherein total drain connect the substrate；

One first clamping piece connects the source electrode of the first transistor；And

One second intermediate plate connects the source electrode of the second transistor,

Wherein first clamping piece and the second intermediate plate is electrically isolated from each other.

2. semiconductor device as described in claim 1, which is characterized in that further include an encapsulating material layer, wherein the package material The bed of material covers the chip, the first clamping piece and the second intermediate plate on the substrate.

3. semiconductor device as claimed in claim 2, which is characterized in that the first clamping piece and the second intermediate plate are at least one of A top surface is at least partly exposed to outside the encapsulating material layer.

4. semiconductor device as claimed in claim 2, which is characterized in that the first clamping piece and the second intermediate plate are at least one of It is a that there is a pin portion to be exposed to outside the encapsulating material layer.

5. semiconductor device as described in claim 1, which is characterized in that a third intermediate plate and one the 4th intermediate plate are further included, In the third intermediate plate connect the gate of the first transistor, and the 4th intermediate plate connects the gate of the second transistor.

6. semiconductor device as claimed in claim 5, which is characterized in that further include an encapsulating material layer, wherein the package material The bed of material covers the chip, the first clamping piece, the second intermediate plate, the third intermediate plate and the 4th intermediate plate on the substrate.

7. semiconductor device as claimed in claim 6, which is characterized in that the third intermediate plate and the 4th intermediate plate are at least one of A top surface is at least partly exposed to outside the encapsulating material layer.

8. semiconductor device as claimed in claim 6, which is characterized in that the third intermediate plate and the 4th intermediate plate are at least one of It is a that there is a pin portion to be exposed to outside the encapsulating material layer.

9. semiconductor device as described in claim 1, which is characterized in that one first conducting wire and one second conducting wire are further included, In first conducting wire connect the gate of the first transistor, and second conducting wire connects the gate of the second transistor.

10. semiconductor device as described in claim 1, which is characterized in that the semiconductor device further includes one first contact site And one second contact site, the first clamping piece and the second intermediate plate are separately connected first contact site and second contact site, with electricity The source electrode of the first transistor and first contact site are connected, and is electrically connected the source electrode of the second transistor and second is contacted with this Portion.