CN207250482U - Wafer stage chip encapsulating structure - Google Patents
Wafer stage chip encapsulating structure Download PDFInfo
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- CN207250482U CN207250482U CN201721319954.4U CN201721319954U CN207250482U CN 207250482 U CN207250482 U CN 207250482U CN 201721319954 U CN201721319954 U CN 201721319954U CN 207250482 U CN207250482 U CN 207250482U
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- dielectric layer
- wafer stage
- encapsulating structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model provides a kind of wafer stage chip encapsulating structure, and wafer stage chip encapsulating structure includes：Semiconductor chip；Re-wiring layer, including low-k dielectric layer, in low-k dielectric layer and low-k dielectric layer upper surface metal line layer；Groove, in the low-k dielectric layer between semiconductor chip；Solder projection, is electrically connected positioned at the upper surface of re-wiring layer, and with metal line layer；Protective layer, is filled between the solder projection and peripheral, and covers the exposed low-k dielectric layer and the metal line layer.The utility model in low-k dielectric layer and metal line layer upper surface and periphery by forming protective layer; the steam of outside can be effectively avoided to penetrate into low-k dielectric layer so that low-k dielectric layer is more easily rupturable; firm low-k dielectric layer can be played again; the effect for preventing external force from being destroyed to low-k dielectric layer; so that low-k dielectric layer is not in slight crack in cutting process, and then it ensure that the performance of encapsulation chip.
Description
Technical field
A kind of semiconductor package and method for packing are the utility model is related to, is sealed more particularly to a kind of wafer stage chip
Assembling structure.
Background technology
, can be in crystalline substance in order to meet the needs of small size development in existing wafer stage chip encapsulating structure (FWLCSP)
Low-k dielectric layer (for example, re-wiring layer) is used in circle level chip-packaging structure, and to be subsequently cut by laser
(laser saw) or blade cut (blade saw)；But since low-k dielectric layer is more crisp, especially exposed in low-k dielectric layer
In atmospheric environment, after the steam in air is entered in low-k dielectric layer so that the low-k dielectric layer is in follow-up cutting
During can easily produce slight crack (crack), and the presence of slight crack can seriously affect the performance of encapsulation chip in low-k dielectric layer.
In addition, in existing wafer stage chip encapsulating structure, re-wiring layer generally comprises two layers of low-k dielectric layer, at least
One layer of metal line layer in the low-k dielectric layer and in low-k dielectric layer and upper surface Underbump metallization layer；It is above-mentioned
The structure of re-wiring layer is more complicated, and manufacture cost is higher.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of encapsulation of wafer stage chip
Structure, can cause low-k dielectric layer to produce slight crack for solving presence of the prior art in cutting process, and then influence encapsulation
The problem of performance of chip, and structure existing for re-wiring layer it is more complicated, manufacture cost it is higher the problem of.
In order to achieve the above objects and other related objects, the utility model provides a kind of wafer stage chip encapsulating structure, institute
Stating wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface gold
Belong to line layer；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal line layer and semiconductor chip electricity
Connection；
Groove, in the low-k dielectric layer between the semiconductor chip, and around the semiconductor chip；Institute
State low-k dielectric layer described in groove up/down perforation；
Solder projection, is electrically connected positioned at the upper surface of the re-wiring layer, and with the metal line layer；
Protective layer, is filled between the solder projection and peripheral, and covers the exposed low-k dielectric layer and the gold
Belong to line layer.
Preferably, the wafer stage chip encapsulating structure includes a semiconductor chip.
Preferably, the wafer stage chip encapsulating structure includes at least two semiconductor chips.
Preferably, the re-wiring layer includes one layer of low-k dielectric layer and one layer of metal line layer.
Preferably, the protective layer is high polymer waterproof material layer.
Preferably, the material of the protective layer is epoxy resin layer.
Preferably, the upper surface of the protective layer is not higher than the upper surface of the solder projection.
The utility model also provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer stage chip encapsulation knot
The preparation method of structure includes the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) in the Semiconductor substrate upper surface formed re-wiring layer, the re-wiring layer include low-k dielectric layer,
In the low-k dielectric layer and the low-k dielectric layer upper surface metal line layer；
3) solder projection is formed in the upper surface of the re-wiring layer, the solder projection is electrically connected with the metal line layer
Connect；
4) in forming groove in the low-k dielectric layer, the groove runs through the low-k dielectric layer, the groove position up and down
Between each semiconductor chip, and around each semiconductor chip；
5) protective layer is formed in the structure upper surface that step 4) obtains, the protective layer is filled between the solder projection
And periphery, and cover the exposed low-k dielectric layer and the metal line layer；
6) cutting separation is carried out from the groove, to obtain wafer stage chip encapsulating structure.
Preferably, step 2) includes the following steps：
2-1) low-k dielectric layer is formed in the upper surface of the Semiconductor substrate；
2-2) in forming opening in the low-k dielectric layer, the opening exposes the connection weld pad；
2-3) metal wire is formed in the opening and upper surface of the low-k dielectric layer of the mouth periphery
Layer, the metal line layer are connected with the connection weld pad.
Preferably, in step 4), using laser in forming the groove in the low-k dielectric layer.
Preferably, in step 6), cutting separation is carried out from the groove using laser cutting parameter.
As described above, the wafer stage chip encapsulating structure of the utility model, has the advantages that：
The wafer stage chip encapsulating structure of the utility model passes through the low-k dielectric layer and metal line layer in re-wiring layer
Upper surface and periphery form protective layer, and protective layer is by the side wall plastic packaging of low-k dielectric layer, you can effectively to avoid the steam of outside from oozing
Enter into low-k dielectric layer to cause that low-k dielectric layer is more easily rupturable, and the firm low-k dielectric layer can be played, prevent external force to institute
The effect of low-k dielectric layer destruction is stated, so that the low-k dielectric layer in the utility model is not in split in cutting process
Trace, and then ensure that the performance of encapsulation chip；Meanwhile protective layer can also play the role of fixing solder projection, this sample
The re-wiring layer of utility model only includes one layer of low-k dielectric layer and one layer of metal line layer, compared to existing re-wiring layer
Reduce one layer of low-k dielectric layer and Underbump metallization layer, have the advantages that simple in structure and manufacturing cost is low etc..
Brief description of the drawings
Fig. 1 is shown as the flow of the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment one
Figure.
Fig. 2~Figure 10 is shown as the preparation method of the wafer stage chip encapsulating structure provided in the utility model embodiment one
The structure diagram that each step is presented, wherein, Fig. 9 and Figure 10 are shown as the wafer stage chip encapsulating structure of the utility model
Structure diagram.
Component label instructions
10 semiconductor chips
101 connection pads
11 re-wiring layers
111 low-k dielectric layer
112 metal line layers
12 grooves
13 solder projections
14 protective layers
15 Semiconductor substrates
16 lasers
17 synthesizing knives
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1~Figure 10.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the utility model provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer scale core
The preparation method of chip package includes the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) in the Semiconductor substrate upper surface formed re-wiring layer, the re-wiring layer include low-k dielectric layer,
In the low-k dielectric layer and the low-k dielectric layer upper surface metal line layer；
3) solder projection is formed in the upper surface of the re-wiring layer, the solder projection is electrically connected with the metal line layer
Connect；
4) in forming groove in the low-k dielectric layer, the groove runs through the low-k dielectric layer, the groove position up and down
Between each semiconductor chip, and around each semiconductor chip；
5) protective layer is formed in the structure upper surface that step 4) obtains, the protective layer is filled between the solder projection
And periphery, and cover the exposed low-k dielectric layer and the metal line layer；
6) cutting separation is carried out from the groove, to obtain wafer stage chip encapsulating structure.
In step 1), S1 steps and Fig. 2 in please referring to Fig.1, there is provided semi-conductive substrate 15, the Semiconductor substrate
Formed with several semiconductor chips 10 in 15.
As an example, the Semiconductor substrate 15 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 15 is Silicon Wafer.
As an example, the semiconductor chip 10 can be any one semiconductor functional chip, the semiconductor chip
10 front is exposed formed with the connection weld pad 101 for drawing its inside function device electricity, the upper surface of the connection weld pad 101
In the upper surface of the semiconductor chip 10, i.e., the upper surface of described connection weld pad 101 and the upper table of the semiconductor chip 10
Face flush.
S2 steps and Fig. 3 in please referring to Fig.1, re-wiring layer 11 is formed in the upper surface of the Semiconductor substrate 15,
The re-wiring layer 11 includes low-k dielectric layer 111, in the low-k dielectric layer 111 and 111 upper table of low-k dielectric layer
The metal line layer 112 in face.
In one example, as shown in figure 3, the re-wiring layer 11 includes one layer of low-k dielectric layer 111 and one layer of metal wire
Layer 1121, forms the re-wiring layer 11 in the upper surface of the Semiconductor substrate 15 and includes the following steps：
2-1) low-k dielectric layer 111 is formed in the upper surface of the Semiconductor substrate 15；
2-2) in forming opening (not shown) in the low-k dielectric layer 111, the opening exposes the connection weld pad
101；
2-3) in the opening and the low-k dielectric layer 111 of the mouth periphery upper surface formed metal line layer
1121, the metal line layer 1121 is connected with the connection weld pad 101.
Since the protective layer being subsequently formed is between the solder projection being subsequently formed and peripheral, can play convex to solder
The effect that block is fixed, the re-wiring layer 11 of such the utility model could be provided as only including one layer of low k dielectric
Layer 111 and one layer of metal line layer 112, reduce under one layer of low-k dielectric layer and convex block compared to existing re-wiring layer
Metal layer, has the advantages that simple in structure and manufacturing cost is low etc..
In step 3), S3 steps and Fig. 4 in please referring to Fig.1, weldering is formed in the upper surface of the re-wiring layer 11
Expect convex block 13, the solder projection 13 is electrically connected with the metal line layer 11.
In one example, solder projection 13 is formed in the upper surface of the re-wiring layer 11 to include the following steps：
3-1) metal column is formed in the upper surface of the re-wiring layer 11；
3-2) soldered ball is formed in the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, can form the soldered ball by planting ball reflux technique.
In another example, can be by planting ball reflux technique as shown in figure 4, the solder projection 13 is a soldered ball
Soldered ball is directly formed as the solder projection 13.
In step 4), the S4 steps and Fig. 5 that please refer to Fig.1 are described in formation groove 12 in the low-k dielectric layer 111
Groove runs through the low-k dielectric layer 111 about 12, the groove 12 is surround each between each semiconductor chip 10
The semiconductor chip 10.
As an example, the laser that laser 16 is launched can be used in the formation groove in the low-k dielectric layer 111
12, certainly, in other examples, etching technics or mechanical cutting processes can also be used in formation in the low-k dielectric layer 111
The groove 12.
It should be noted that the lateral dimension of the groove 12 can be less than the adjacent semiconductor chip as shown in Figure 5
Spacing between 10；Can also be that the lateral dimension of the groove 12 is equal to the spacing between the adjacent semiconductor chip 10.
In step 5), the S5 steps and Fig. 6 that please refer to Fig.1, protective layer is formed in the structure upper surface that step 4) obtains
14, the protective layer 14 is filled between the solder projection 13 and periphery, and cover the exposed low-k dielectric layer 111 and
The metal line layer 112.
Protected as an example, gluing process meeting InkJet printing processes can be used to be formed in the structure upper surface that step 4) obtains
Sheath 14.
As an example, the protective layer 14 can be high polymer waterproof material layer, the protective layer 14 is used for follow-up each institute
The upper surface and periphery of the low-k dielectric layer 111 and the metal line layer 112 are covered after stating the cutting separation of semiconductor chip 10
Plastic packaging, you can effectively to avoid the steam of outside from penetrating into the low-k dielectric layer 111 so that the low-k dielectric layer 111 is more easy to
Rupture, and the firm low-k dielectric layer 111 can be played, the effect for preventing external force from being destroyed to the low-k dielectric layer 111, so that
So that the low-k dielectric layer 111 in the utility model is not in slight crack in cutting process, and then it ensure that encapsulation chip
Performance.
As an example, the protective layer 14 can be but be not limited only to epoxy resin layer.
As an example, as shown in fig. 7, further included after step 5) from the lower surface of the Semiconductor substrate 15 to described half
Conductor substrate 15 carries out the processing of reduction processing so that the lower surface of the protective layer 14 and the Semiconductor substrate 15 retained
Lower surface flush.
As an example, can use the technique such as grinding technics, etching technics to the Semiconductor substrate 15 from lower surface into
Row reduction processing.
In step 6), S7 steps and Fig. 8 and Figure 10 in please referring to Fig.1, cutting separation is carried out from the groove 12,
To obtain wafer stage chip encapsulating structure.
As an example, cutting separation can be carried out from the groove 12, you can using mechanical cutting processes to use brill
Stone synthesis knife 17 carries out cutting separation from the groove 12.Certainly, in other examples, laser cutting parameter can also be used
Cutting separation is carried out from the groove 12.
In one example, can be cut in step 6) from the groove 12 between each semiconductor chip 10
Cut, to obtain including the wafer stage chip encapsulating structure of a semiconductor chip 10, as shown in Figure 9.
In another example, can be in the groove 12 between two or more semiconductor chips 10 in step 6)
Place is cut, to obtain including the wafer stage chip encapsulating structure of two or more semiconductor chips 10, Figure 10 be with
The wafer stage chip encapsulating structure obtained after cutting is used as example including two semiconductor chips 10.
Embodiment two
A kind of wafer stage chip encapsulating structure is also provided with continued reference to Fig. 9 and Figure 10, the present embodiment incorporated by reference to Fig. 2 to Fig. 8,
The wafer stage chip encapsulating structure includes：Semiconductor chip 10；Re-wiring layer 11, the re-wiring layer 11 include low k
Dielectric layer 111, in the low-k dielectric layer 111 and 111 upper surface of low-k dielectric layer metal line layer 112；The low k
Dielectric layer 111 is located at the front of the semiconductor chip 10, and the metal line layer 111 is electrically connected with the semiconductor chip 10
Connect；Groove 12, the groove 12 surround described half in the low-k dielectric layer 111 between the semiconductor chip 10
Conductor chip 10；Low-k dielectric layer 111 described in 12 up/down perforation of groove；Solder projection 13, the solder projection 13 are located at institute
The upper surface of re-wiring layer 11 is stated, and is electrically connected with the metal line layer 112；Protective layer 14, the protective layer 14 are filled in
Between the solder projection 13 and periphery, and cover the exposed low-k dielectric layer 111 and the metal line layer 112.
It should be noted that can as shown in FIG. 9 and 10, the wafer stage chip encapsulating structure further includes semiconductor
Substrate 15, the semiconductor chip 10 are located in the Semiconductor substrate 15；Institute can also be located at for the semiconductor chip 10
State all areas of the lower section of re-wiring layer 11 between protective layer 14, described between the semiconductor chip 10 is partly led
Body substrate 15 is completely removed during cutting.
As an example, the Semiconductor substrate 15 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 15 is Silicon Wafer.
As an example, the semiconductor chip 10 can be any one semiconductor functional chip, the semiconductor chip
10 front is exposed formed with the connection weld pad 101 for drawing its inside function device electricity, the upper surface of the connection weld pad 101
In the upper surface of the semiconductor chip 10, i.e., the upper surface of described connection weld pad 101 and the upper table of the semiconductor chip 10
Face flush.
As an example, the re-wiring layer 11 includes one layer of low-k dielectric layer 111 and one layer of metal line layer
112。
In one example, the solder projection 13 includes metal column and soldered ball, wherein, the metal column positioned at it is described again
The upper surface of wiring layer 11, and be electrically connected with the re-wiring layer 11；The soldered ball is located at the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials.The material of the soldered ball can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials.
In another example, as shown in FIG. 9 and 10, the solder projection 12 is a soldered ball.
As an example, the protective layer 14 is high polymer waterproof material layer.Preferably, the material of the protective layer 14 can be with
For but be not limited only to epoxy resin layer.
As an example, the upper surface of the protective layer 14 is not higher than the upper surface of the solder projection 13, i.e., described protection
Upper surface flush of the upper surface of layer 14 less than the upper surface of the solder projection 13 or with the solder projection 13.
It should be noted that the protective layer 14 fills up the gap between the re-wiring layer 11, i.e., described protective layer
14 fill up the groove 12 between the low-k dielectric layer, the gap between the metal line layer 112.
In one example, as shown in figure 9, the wafer stage chip encapsulating structure can include a semiconductor chip
10。
In another example, as shown in Figure 10, the wafer stage chip encapsulating structure can also include two or more institutes
State semiconductor chip 10.
In conclusion the wafer stage chip encapsulating structure of the utility model, the wafer stage chip encapsulating structure includes：Half
Conductor chip；Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface
Metal line layer；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal line layer and the semiconductor chip
It is electrically connected；Groove, in the low-k dielectric layer between the semiconductor chip, and around the semiconductor chip；It is described
Low-k dielectric layer described in groove up/down perforation；Solder projection, positioned at the upper surface of the re-wiring layer, and with the metal wire
Layer is electrically connected；Protective layer, is filled between the solder projection and periphery, and covers the exposed low-k dielectric layer and described
Metal line layer.The wafer stage chip encapsulating structure of the utility model passes through the low-k dielectric layer and metal line layer in re-wiring layer
Upper surface and periphery form protective layer, protective layer is by the side wall plastic packaging of low-k dielectric layer, you can effectively to avoid the steam of outside
Penetrate into low-k dielectric layer and make it that low-k dielectric layer is more easily rupturable, and the firm low-k dielectric layer can be played, prevent external force pair
The effect that the low-k dielectric layer is destroyed, so that the low-k dielectric layer in the utility model is not in split in cutting process
Trace, and then ensure that the performance of encapsulation chip；Meanwhile protective layer can also play the role of fixing solder projection, this sample
The re-wiring layer of utility model only includes one layer of low-k dielectric layer and one layer of metal line layer, compared to existing re-wiring layer
Reduce one layer of low-k dielectric layer and Underbump metallization layer, have the advantages that simple in structure and manufacturing cost is low etc..
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (7)
1. a kind of wafer stage chip encapsulating structure, it is characterised in that the wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface metal wire
Layer；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal line layer is electrically connected with the semiconductor chip
Connect；
Groove, in the low-k dielectric layer between the semiconductor chip, and around the semiconductor chip；The ditch
Low-k dielectric layer described in groove up/down perforation；
Solder projection, is electrically connected positioned at the upper surface of the re-wiring layer, and with the metal line layer；
Protective layer, is filled between the solder projection and peripheral, and covers the exposed low-k dielectric layer and the metal wire
Layer.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The wafer stage chip encapsulating structure
Including a semiconductor chip.
3. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The wafer stage chip encapsulating structure
Including at least two semiconductor chips.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The re-wiring layer includes one layer
The low-k dielectric layer and one layer of metal line layer.
5. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The protective layer is macromolecule waterproof
Material layer.
6. wafer stage chip encapsulating structure according to claim 5, it is characterised in that：The material of the protective layer is epoxy
Resin bed.
7. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The upper surface of the protective layer is not high
In the upper surface of the solder projection.
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| CN201721319954.4U CN207250482U (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure |
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| CN201721319954.4U CN207250482U (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611091A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611091A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |