CN107611095A - Wafer stage chip encapsulating structure and preparation method thereof - Google Patents
Wafer stage chip encapsulating structure and preparation method thereof Download PDFInfo
- Publication number
- CN107611095A CN107611095A CN201710954743.6A CN201710954743A CN107611095A CN 107611095 A CN107611095 A CN 107611095A CN 201710954743 A CN201710954743 A CN 201710954743A CN 107611095 A CN107611095 A CN 107611095A
- Authority
- CN
- China
- Prior art keywords
- layer
- low
- dielectric layer
- semiconductor chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of wafer stage chip encapsulating structure and preparation method thereof, and the wafer stage chip encapsulating structure includes：Semiconductor chip；Re-wiring layer, including low-k dielectric layer, in low-k dielectric layer and low-k dielectric layer upper surface metal connecting layer；Solder projection, electrically connected positioned at the upper surface of re-wiring layer, and with metal connecting layer；First protective layer, positioned at the periphery of semiconductor chip and re-wiring layer；Second protective layer, positioned at the back side of semiconductor chip and the bottom of the first protective layer.The present invention forms the first protective layer by the low-k dielectric layer periphery in semiconductor chip and re-wiring layer; it can effectively avoid the steam of outside from penetrating into low-k dielectric layer and make it that low-k dielectric layer is more easily rupturable; firm low-k dielectric layer can be played again; the effect for preventing external force from being destroyed to low-k dielectric layer; so that low-k dielectric layer is not in slight crack in cutting process, and then it ensure that the performance of encapsulation chip.
Description
Technical field
The present invention relates to a kind of semiconductor package and method for packing, encapsulates and ties more particularly to a kind of wafer stage chip
Structure and preparation method thereof.
Background technology
, can be in wafer in order to meet the needs of small size development in existing wafer stage chip encapsulating structure (WLCSP)
Low-k dielectric layer (for example, re-wiring layer) is used in level chip-packaging structure, and to be subsequently cut by laser (laser
Saw) or blade cuts (blade saw)；But because low-k dielectric layer is more crisp, especially it is exposed to big compression ring in low-k dielectric layer
In border, after the steam in air is entered in low-k dielectric layer so that low-k dielectric layer meeting in follow-up cutting process
Slight crack (crack) is easily produced, and the presence of slight crack can have a strong impact on the performance of encapsulation chip in low-k dielectric layer.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of wafer stage chip encapsulating structure
And preparation method thereof, for solving presence of the prior art low-k dielectric layer can be caused to produce slight crack in cutting process, and then
The problem of influenceing the performance of encapsulation chip.
In order to achieve the above objects and other related objects, the present invention provides a kind of wafer stage chip encapsulating structure, the crystalline substance
Circle level chip-packaging structure includes：
Semiconductor chip；
Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface gold
Belong to articulamentum；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal connecting layer and the semiconductor core
Piece electrically connects；
Solder projection, electrically connected positioned at the upper surface of the re-wiring layer, and with the metal connecting layer；
First protective layer, positioned at the periphery of the semiconductor chip and the re-wiring layer, and by the semiconductor core
The side of piece and the side plastic packaging of the low-k dielectric layer；
Second protective layer, positioned at the back side of the semiconductor chip and the bottom of first protective layer.
Preferably, the re-wiring layer includes：
First low-k dielectric layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, electrically connected in first low-k dielectric layer, and with the semiconductor chip；
Second low-k dielectric layer, it is covered in the upper surface of first low-k dielectric layer and the metal line layer；
Underbump metallization layer, in second low-k dielectric layer and the second low-k dielectric layer surface, and it is described convex
The lower surface of block lower metal layer electrically connects with the upper surface of the metal line layer；Wherein
First low-k dielectric layer and second low-k dielectric layer collectively form the low-k dielectric layer, the metal wire
Layer and the Underbump metallization layer collectively form the metal connecting layer.
Preferably, the metal connecting layer includes layer of metal line layer, and the metal line layer is located at the low-k dielectric layer
It is interior, electrically connected with the semiconductor chip and the solder projection.
Preferably, first protective layer and second protective layer are high polymer waterproof material layer.
Preferably, the material of first protective layer and second protective layer is epoxy resin layer.
Preferably, the upper surface of first protective layer is not less than the upper surface of the low-k dielectric layer, and described first protects
The lower surface of sheath and the lower surface flush of the semiconductor chip.
The present invention also provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer stage chip encapsulating structure
Preparation method comprises the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) in the Semiconductor substrate upper surface formed re-wiring layer, the re-wiring layer include low-k dielectric layer,
In the low-k dielectric layer and the low-k dielectric layer upper surface metal connecting layer；
3) solder projection, the solder projection and metal connecting layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) in forming groove in the low-k dielectric layer and the Semiconductor substrate, the groove is situated between through the low k up and down
Matter layer is simultaneously extended in the Semiconductor substrate, and the groove surround each described half between each semiconductor chip
Conductor chip；
5) in filling the first protective layer in the groove；
6) reduction processing is carried out to the Semiconductor substrate from the lower surface of the Semiconductor substrate so that described first protects
The lower surface of sheath and the lower surface flush of the Semiconductor substrate retained；
7) the second protective layer is formed in the lower surface of the Semiconductor substrate；
8) cutting separation is carried out from first protective layer.
Preferably, step 4) comprises the following steps：
4-1) in formation first groove portion, low k dielectric described in first groove portion up/down perforation in the low-k dielectric layer
Layer, the first groove portion surround each semiconductor chip between each semiconductor chip；
4-2) in formation second groove portion, the second groove in the Semiconductor substrate of first groove portion bottom
Portion is connected with the first groove portion；The second groove portion is surround each described between each semiconductor chip
Semiconductor chip；The second groove portion and the first groove portion collectively form the groove.
Preferably, step 4-1) in, using laser in forming the first groove portion in the low-k dielectric layer；Step 4-
2) in, using synthesizing knife in forming the second groove portion in the Semiconductor substrate of first groove portion bottom.
Preferably, in step 8), using laser cutting parameter by each semiconductor chip from first protective layer
Carry out cutting separation.
As described above, wafer stage chip encapsulating structure of the present invention and preparation method thereof, has the advantages that：
The wafer stage chip encapsulating structure of the present invention passes through in the low-k dielectric layer periphery of semiconductor chip and re-wiring layer
Form the first protective layer, the first protective layer is by semiconductor chip and the side wall plastic packaging of low-k dielectric layer, you can effectively to avoid outside
Steam penetrate into low-k dielectric layer and make it that low-k dielectric layer is more easily rupturable, the firm low-k dielectric layer can be played again, prevented
The effect that external force is destroyed to the low-k dielectric layer, so that the low-k dielectric layer in the present invention is not in cutting process
Slight crack, and then ensure that the performance of encapsulation chip；
The second protective layer in the wafer stage chip encapsulating structure of the present invention can play to be consolidated to semiconductor chip
Protective effect, it can play a part of avoiding steam from entering semiconductor chip and low-k dielectric layer from the bottom of semiconductor chip again,
So as to play the protection to wafer stage chip encapsulating structure.
Brief description of the drawings
Fig. 1 is shown as the flow chart of the preparation method of the wafer stage chip encapsulating structure provided in the embodiment of the present invention one.
The preparation method for the wafer stage chip encapsulating structure that Fig. 2~Figure 11 is shown as providing in the embodiment of the present invention one respectively walks
Suddenly the structural representation presented, wherein, Figure 11 is shown as the structural representation of the wafer stage chip encapsulating structure of the present invention.
Component label instructions
10 semiconductor chips
101 connection weld pads
11 re-wiring layers
111 low-k dielectric layer
1111 first low-k dielectric layer
1112 second low-k dielectric layer
112 metal connecting layers
1121 metal line layers
1122 Underbump metallization layers
12 solder projections
13 first protective layers
14 second protective layers
15 Semiconductor substrates
16 grooves
161 first groove portions
162 second groove portions
17 lasers
18 synthesizing knives
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of wafer stage chip encapsulating structure, the wafer stage chip envelope
The preparation method of assembling structure comprises the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) in the Semiconductor substrate upper surface formed re-wiring layer, the re-wiring layer include low-k dielectric layer,
In the low-k dielectric layer and the low-k dielectric layer upper surface metal connecting layer；
3) solder projection, the solder projection and metal connecting layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) in forming groove in the low-k dielectric layer and the Semiconductor substrate, the groove is situated between through the low k up and down
Matter layer is simultaneously extended in the Semiconductor substrate, and the groove surround each described half between each semiconductor chip
Conductor chip；
5) in filling the first protective layer in the groove；
6) reduction processing is carried out to the Semiconductor substrate from the lower surface of the Semiconductor substrate so that described first protects
The lower surface of sheath and the lower surface flush of the Semiconductor substrate retained；
7) the second protective layer is formed in the lower surface of the Semiconductor substrate；
8) cutting separation is carried out from first protective layer.
In step 1), S1 steps and Fig. 2 in Fig. 1 are referred to, there is provided semi-conductive substrate 15, the Semiconductor substrate
Formed with several semiconductor chips 10 in 15.
As an example, the Semiconductor substrate 15 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 15 is Silicon Wafer.
As an example, the semiconductor chip 10 can be any one semiconductor functional chip, the semiconductor chip
10 front is exposed formed with the connection weld pad 101 for drawing its inside function device electricity, the upper surface of the connection weld pad 101
In the upper surface of the semiconductor chip 10, i.e., the upper surface of described connection weld pad 101 and the upper table of the semiconductor chip 10
Face flush.
S2 steps and Fig. 3 in Fig. 1 are referred to, re-wiring layer 11 is formed in the upper surface of the Semiconductor substrate 15,
The re-wiring layer 11 includes low-k dielectric layer 111, in the low-k dielectric layer 111 and the upper table of low-k dielectric layer 111
The metal connecting layer 112 in face.
In one example, wrapped as shown in figure 3, forming the re-wiring layer 11 in the upper surface of the Semiconductor substrate 15
Include following steps：
2-1) the first low-k dielectric layer 1111 is formed in the upper surface of the Semiconductor substrate 15；
2-2) in forming the first opening (not shown) in first low-k dielectric layer 1111, first opening exposes
The connection weld pad 101；
2-3) in the described first opening and first low-k dielectric layer 1111 of first mouth periphery upper surface
Metal line layer 1121 is formed, the metal line layer 1121 contacts connection with the connection weld pad 101；
2-4) the second low k dielectric is formed in the upper surface of the metal line layer 1121 and first low-k dielectric layer 1111
Layer 1112；
2-5) in forming the second opening (not shown) in second low-k dielectric layer 1112, second opening exposes
The metal line layer 1121；
2-6) in the described second opening and second low-k dielectric layer 1112 of second mouth periphery upper surface
Underbump metallization layer 1122 is formed, the Underbump metallization layer 1122 contacts connection with the metal line layer 1121.
Certainly, in other examples, existing any one re-wiring layer preparation technology can also be used to prepare includes
The re-wiring layer 11 of the low-k dielectric layer 111, the metal line layer 1121 and the Underbump metallization layer 1122.
In another example, the re-wiring layer 11 includes one layer of low-k dielectric layer 111 and layer of metal line layer 1121,
The re-wiring layer 11 is formed in the upper surface of the Semiconductor substrate 15 to comprise the following steps：
2-1) low-k dielectric layer 111 is formed in the upper surface of the Semiconductor substrate 15；
2-2) in forming opening (not shown) in the low-k dielectric layer 111, the opening exposes the connection weld pad
101；
2-3) in the opening and the low-k dielectric layer 111 of the mouth periphery upper surface formed metal line layer
1121, the metal line layer 1121 contacts connection with the connection weld pad 101.
In step 3), S3 steps and Fig. 4 in Fig. 1 are referred to, weldering is formed in the upper surface of the re-wiring layer 11
Expect projection 12, the solder projection 12 electrically connects with the metal connecting layer 112.
In one example, solder projection 12 is formed in the upper surface of the re-wiring layer 11 to comprise the following steps：
3-1) metal column is formed in the upper surface of the re-wiring layer 11；
3-2) soldered ball is formed in the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, the soldered ball can be formed by planting ball reflux technique.
In another example, can be by planting ball reflux technique as shown in figure 4, the solder projection 12 is a soldered ball
Soldered ball is directly formed as the solder projection 12.
Specifically, when the metal connecting layer 112 in the re-wiring layer 11 includes metal line layer 1121 and described
During Underbump metallization layer 1122, the solder projection 12 is formed at the upper surface of the Underbump metallization layer 1122；When described heavy
When the metal connecting layer 112 in new route layer 11 only includes the metal line layer 1121, the solder projection 12 is formed at
The upper surface of the metal line layer 1121.
In step 4), Fig. 1 S4 steps and Fig. 5 to Fig. 6 are referred to, in the low-k dielectric layer 111 and the semiconductor
Groove 16 is formed in substrate 15, the groove through the low-k dielectric layer 111 and extends to the Semiconductor substrate 15 about 16
Interior, the groove 16 surround each semiconductor chip 10 between each semiconductor chip 10.
As an example, include following step in forming groove 16 in the low-k dielectric layer 111 and the Semiconductor substrate 15
Suddenly：
4-1) in formation first groove portion 161, up/down perforation institute of the first groove portion 161 in the low-k dielectric layer 111
Low-k dielectric layer 111 is stated, the first groove portion 161 surround each semiconductor between each semiconductor chip 10
Chip 10, as shown in Figure 5；
It is described 4-2) in formation second groove portion 162 in the Semiconductor substrate 15 of the bottom of first groove portion 161
Second groove portion 162 is connected with the first groove portion 161；The second groove portion 162 is located at each semiconductor chip
Between 10, and around each semiconductor chip 10；The second groove portion 162 collectively forms with the first groove portion 161
The groove 16, as shown in Figure 6.
It should be noted that step 4-2) in shape in the Semiconductor substrate 15 of the bottom of first groove portion 161
Into the second groove portion 162 lateral dimension can as shown in Figure 6 be less than the adjacent semiconductor chip 10 between
Away from during forming the second groove portion 162, removing that the part between the adjacent semiconductor chip 10 is described partly to lead
Body substrate 15；Can also be between the lateral dimension in the second groove portion 162 is equal between the adjacent semiconductor chip 10
Away from during forming the second groove portion 162, remove between the adjacent semiconductor chip 10 all described partly leads
Body substrate 15.
As an example, step 4-1) in, the laser that laser 17 is launched can be used in shape in the low-k dielectric layer 111
Into the first groove portion 161, certainly, in other examples, etching technics or mechanical cutting processes can also be used in described
The first groove portion 161 is formed in low-k dielectric layer 111.
As an example, step 4-2) in, partly led in the described of the bottom of first groove portion 161 using synthesizing knife 18
The second groove portion 162 is formed in body substrate 15, certainly, in other examples, can also use laser or etching technics in institute
State and the second groove portion 162 is formed in the Semiconductor substrate 15 of the bottom of first groove portion 161.
In step 5), Fig. 1 S5 steps and Fig. 7 are referred to, in the first protective layer 13 of filling in the groove 16.
As an example, gluing process meeting InkJet printing processes can be used in first protection of filling in the groove 16
Layer 13.
As an example, first protective layer 13 can be high polymer waterproof material layer, first protective layer 13 is used for
By the semiconductor chip 10 and four surface sides of the low-k dielectric layer 111 after the follow-up each cutting of semiconductor chip 10 separation
Wall plastic packaging, you can cause the low-k dielectric layer 111 more effectively to avoid the steam of outside from penetrating into the low-k dielectric layer 111
It is easily rupturable, the firm low-k dielectric layer 111 can be played again, the effect for preventing external force from being destroyed to the low-k dielectric layer 111, from
And make it that the low-k dielectric layer 111 in the present invention is not in slight crack in cutting process, and then ensure that encapsulation chip
Performance.
As an example, first protective layer 13 can be but be not limited only to epoxy resin layer.
In step 6), S6 steps and Fig. 8 in Fig. 1 are referred to, from the lower surface of the Semiconductor substrate 15 to described
Semiconductor substrate 15 carries out reduction processing so that the lower surface of first protective layer 13 and the Semiconductor substrate 15 retained
Lower surface flush.
As an example, the techniques such as grinding technics, etching technics can be used to enter the Semiconductor substrate 15 from lower surface
Row reduction processing.
In step 7), S7 steps and Fig. 9 in Fig. 1 are referred to, the is formed in the lower surface of the Semiconductor substrate 15
Two protective layers 14.
As an example, gluing process, InkJet printing processes, barbola work can be used to be equal to the Semiconductor substrate 15
Lower surface forms second protective layer 14.
As an example, second protective layer 14 can be high polymer waterproof material layer, second protective layer 14
With the firm protective effect to the semiconductor chip 10, it can play again and avoid steam from the bottom of the semiconductor chip 10
Into the effect of the semiconductor chip 10 and the low-k dielectric layer 111, so as to play the guarantor to wafer stage chip encapsulating structure
Shield.Meanwhile second protective layer 14 cooperatively realizes five faces to semiconductor chip 10 with first protective layer 13
Plastic packaging so that the wafer stage chip encapsulating structure obtained after follow-up cutting is more firm, and anti-steam effect is more preferable.
In step 8), S8 steps and Figure 10 and Figure 11 in Fig. 1 are referred to, is cut from first protective layer 13
Cut separation.
In one example, laser cutting parameter can be used from first protection between each semiconductor chip 10
Carry out cutting separation at layer 13, you can with using the laser that laser 17 is launched by each semiconductor chip 10 from described first
Cutting separation is carried out at protective layer 13, knot is encapsulated to obtain including the wafer stage chip of a semiconductor chip 10
Structure, as shown in figure 11.
In another example, laser cutting parameter can also be used between two or more semiconductor chips 10
Cutting separation is carried out at first protective layer 13, to obtain the wafer scale core of two or more semiconductor chips 10
Chip package.
Embodiment two
Incorporated by reference to Fig. 2 to Figure 10 with continued reference to Figure 11, the present embodiment also provides a kind of wafer stage chip encapsulating structure, described
Wafer stage chip encapsulating structure includes：Semiconductor chip 10；Re-wiring layer 11, the re-wiring layer 11 include low k dielectric
Layer 111, in the low-k dielectric layer 111 and the upper surface of low-k dielectric layer 111 metal connecting layer 112；The low k is situated between
Matter layer 111 is located at the front of the semiconductor chip 10, and the metal connecting layer 112 is electrically connected with the semiconductor chip 10
Connect；Solder projection 12, the solder projection 12 are located at the upper surface of the re-wiring layer 11, and with the metal connecting layer
112 electrical connections；First protective layer 13, first protective layer 13 are located at the semiconductor chip and 10 re-wiring layers 11
Periphery, and by the side of the semiconductor chip 10 and the side plastic packaging of the low-k dielectric layer 111；Second protective layer 14, institute
State the second protective layer 14 and be located at the back side of the semiconductor chip 10 and the bottom of first protective layer 13.
It should be noted that can be as shown in figure 11, the wafer stage chip encapsulating structure also includes Semiconductor substrate
15, the semiconductor chip 10 is located in the Semiconductor substrate 15, and first protective layer 13 is located at the semiconductor chip
The surrounding side of the Semiconductor substrate 15 of 10 peripheries, by the semiconductor chip 10 and the periphery of the semiconductor chip 10
The plastic packaging of the Semiconductor substrate 15；Can also be that first protective layer 13 can be located immediately at the semiconductor chip 10
Surrounding side, by the 10 direct plastic packaging of semiconductor chip, i.e., can also be to serve as a contrast the semiconductor as shown in Figure 11
Bottom 15 is removed, and the semiconductor chip 10 is occupied such as the position of the Semiconductor substrate 15 in Figure 11, that is, the semiconductor
The all areas of the lower section of re-wiring layer 11 between first protective layer 13 of chip 10.
As an example, the Semiconductor substrate 15 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 15 is Silicon Wafer.
As an example, the semiconductor chip 10 can be any one semiconductor functional chip, the semiconductor chip
10 front is exposed formed with the connection weld pad 101 for drawing its inside function device electricity, the upper surface of the connection weld pad 101
In the upper surface of the semiconductor chip 10, i.e., the upper surface of described connection weld pad 101 and the upper table of the semiconductor chip 10
Face flush.
In one example, as shown in Fig. 3 and Figure 11, the re-wiring layer 11 includes：First low-k dielectric layer 1111, institute
State the front that the first low-k dielectric layer 1111 is located at the semiconductor chip 10；At least one layer of metal line layer 1121, the metal wire
Layer 1121 electrically connects in first low-k dielectric layer 1111 with the semiconductor chip 10；Second low-k dielectric layer
1112, second low-k dielectric layer 1112 is covered in first low-k dielectric layer 1111 and the upper table of the metal line layer 1121
Face；Underbump metallization layer 1122, the Underbump metallization layer 1122 are located in second low-k dielectric layer 1112 and described second
The surface of low-k dielectric layer 1112, and the lower surface of the Underbump metallization layer 1122 and the upper surface electricity of the metal line layer 1121
Connection；Wherein, first low-k dielectric layer 1111 and second low-k dielectric layer 1112 collectively form the low-k dielectric layer
111, the metal line layer 1121 and the Underbump metallization layer 1122 collectively form the metal connecting layer 112.
In another example, the metal connecting layer 112 only includes layer of metal line layer 1121, the low-k dielectric layer 111
Only single layer structure, and the metal line layer 1121 is located in the low-k dielectric layer 111, with the semiconductor chip 10 and institute
Solder projection 12 is stated to electrically connect.
In one example, the solder projection 12 includes metal column and soldered ball, wherein, the metal column positioned at it is described again
The upper surface of wiring layer 11, and electrically connected with the re-wiring layer 11；The soldered ball is located at the upper surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials.The material of the soldered ball can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials.
In another example, as shown in figure 11, the solder projection 12 is a soldered ball.
As an example, the material of first protective layer 13 and second protective layer 14 are high polymer waterproof material
Layer.Preferably, the material of first protective layer 13 and second protective layer 14 can be but be not limited only to epoxy resin
Layer.
As an example, the upper surface of first protective layer 13 is not less than the upper surface of the low-k dielectric layer 111, i.e. institute
The upper surface of the first protective layer 13 is stated with the upper surface flush of the low-k dielectric layer 111 or higher than the low-k dielectric layer 111
Upper surface, and the lower surface flush of the lower surface of first protective layer 13 and the semiconductor chip 10, to ensure
The first protective layer 13 is stated by the side of the semiconductor chip 10 and the side plastic packaging of the low-k dielectric layer 111.
In one example, as shown in figure 11, the wafer stage chip encapsulating structure includes a semiconductor chip 10.
In another example, the wafer stage chip encapsulating structure can also include two or more semiconductor chips
10.First protective layer 13 around each semiconductor chip 10 is provided between the adjacent semiconductor chip 10.
In summary, wafer stage chip encapsulating structure of the invention and preparation method thereof, the wafer stage chip encapsulation knot
Structure includes：Semiconductor chip；Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer
The metal connecting layer of upper surface；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal connecting layer and institute
State semiconductor chip electrical connection；Solder projection, it is electrically connected positioned at the upper surface of the re-wiring layer, and with the metal connecting layer
Connect；First protective layer, positioned at the periphery of the semiconductor chip and the re-wiring layer, and by the side of the semiconductor chip
Face and the side plastic packaging of the low-k dielectric layer；Second protective layer, positioned at the back side of the semiconductor chip and first protection
The bottom of layer.The wafer stage chip encapsulating structure of the present invention passes through outside the low-k dielectric layer of semiconductor chip and re-wiring layer
Enclose to form the first protective layer, the first protective layer is by semiconductor chip and the side wall plastic packaging of low-k dielectric layer, you can outer effectively to avoid
The steam in portion, which is penetrated into low-k dielectric layer, make it that low-k dielectric layer is more easily rupturable, can play the firm low-k dielectric layer again, prevent
The effect that only external force is destroyed to the low-k dielectric layer, so that the low-k dielectric layer in the present invention will not go out in cutting process
Existing slight crack, and then ensure that the performance of encapsulation chip；The second protective layer in the wafer stage chip encapsulating structure of the present invention
To play the firm protective effect to semiconductor chip, it can play avoiding steam from from the bottom of semiconductor chip entering partly leading again
The effect of body chip and low-k dielectric layer, so as to play the protection to wafer stage chip encapsulating structure.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of wafer stage chip encapsulating structure, it is characterised in that the wafer stage chip encapsulating structure includes：
Semiconductor chip；
Re-wiring layer, including low-k dielectric layer, in the low-k dielectric layer and the low-k dielectric layer upper surface metal connect
Connect layer；The low-k dielectric layer is located at the front of the semiconductor chip, and the metal connecting layer and semiconductor chip electricity
Connection；
Solder projection, electrically connected positioned at the upper surface of the re-wiring layer, and with the metal connecting layer；
First protective layer, positioned at the periphery of the semiconductor chip and the re-wiring layer, and by the semiconductor chip
Side and the side plastic packaging of the low-k dielectric layer；
Second protective layer, positioned at the back side of the semiconductor chip and the bottom of first protective layer.
2. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The re-wiring layer includes：
First low-k dielectric layer, positioned at the front of the semiconductor chip；
At least one layer of metal line layer, electrically connected in first low-k dielectric layer, and with the semiconductor chip；
Second low-k dielectric layer, it is covered in the upper surface of first low-k dielectric layer and the metal line layer；
Underbump metallization layer, in second low-k dielectric layer and the second low-k dielectric layer surface, and under the projection
The lower surface of metal level electrically connects with the upper surface of the metal line layer；Wherein
First low-k dielectric layer and second low-k dielectric layer collectively form the low-k dielectric layer, the metal line layer and
The Underbump metallization layer collectively forms the metal connecting layer.
3. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The metal connecting layer includes one layer
Metal line layer, and the metal line layer is located in the low-k dielectric layer, is electrically connected with the semiconductor chip and the solder projection
Connect.
4. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：First protective layer and described
Two protective layers are high polymer waterproof material layer.
5. wafer stage chip encapsulating structure according to claim 4, it is characterised in that：First protective layer and described
The material of two protective layers is epoxy resin layer.
6. wafer stage chip encapsulating structure according to claim 1, it is characterised in that：The upper surface of first protective layer
Not less than the upper surface of the low-k dielectric layer, and the lower surface of first protective layer and the lower surface of the semiconductor chip
Flush.
A kind of 7. preparation method of wafer stage chip encapsulating structure, it is characterised in that the system of the wafer stage chip encapsulating structure
Preparation Method comprises the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate is interior formed with several semiconductor chips；
2) re-wiring layer is formed in the upper surface of the Semiconductor substrate, the re-wiring layer includes low-k dielectric layer, is located at
The metal connecting layer of in the low-k dielectric layer and low-k dielectric layer upper surface；
3) solder projection is formed in the upper surface of the re-wiring layer, the solder projection is electrically connected with the metal connecting layer
Connect；
4) in forming groove in the low-k dielectric layer and the Semiconductor substrate, the groove runs through the low-k dielectric layer up and down
And extend in the Semiconductor substrate, the groove surround each semiconductor between each semiconductor chip
Chip；
5) in filling the first protective layer in the groove；
6) reduction processing is carried out to the Semiconductor substrate from the lower surface of the Semiconductor substrate so that first protective layer
Lower surface with retain the Semiconductor substrate lower surface flush；
7) the second protective layer is formed in the lower surface of the Semiconductor substrate；
8) cutting separation is carried out from first protective layer.
8. the preparation method of wafer stage chip encapsulating structure according to claim 7, it is characterised in that：Step 4) is included such as
Lower step：
4-1) in forming first groove portion in the low-k dielectric layer, low-k dielectric layer described in first groove portion up/down perforation,
The first groove portion surround each semiconductor chip between each semiconductor chip；
4-2) in forming second groove portion in the Semiconductor substrate of first groove portion bottom, the second groove portion with
The first groove portion is connected；Described partly led between each semiconductor chip, and around each in the second groove portion
Body chip；The second groove portion and the first groove portion collectively form the groove.
9. the preparation method of wafer stage chip encapsulating structure according to claim 8, it is characterised in that：Step 4-1) in,
Using laser in forming the first groove portion in the low-k dielectric layer；Step 4-2) in, using synthesizing knife in described
The second groove portion is formed in the Semiconductor substrate of one trough base.
10. the preparation method of wafer stage chip encapsulating structure according to claim 7, it is characterised in that：In step 8), adopt
Each semiconductor chip from first protective layer is subjected to cutting separation with laser cutting parameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710954743.6A CN107611095A (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710954743.6A CN107611095A (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107611095A true CN107611095A (en) | 2018-01-19 |
Family
ID=61078161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710954743.6A Pending CN107611095A (en) | 2017-10-13 | 2017-10-13 | Wafer stage chip encapsulating structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107611095A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI802181B (en) * | 2020-12-30 | 2023-05-11 | 加拿大商萬國半導體國際有限合夥公司 | Semi-wafer level chip scale semiconductor package and method thereof |
| US11664734B2 (en) | 2020-02-19 | 2023-05-30 | Alpha And Omega Semiconductor International Lp | Flyback converter for controlling on time variation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090091001A1 (en) * | 2007-10-09 | 2009-04-09 | Nepes Corporation | Crack resistant semiconductor package and method of fabricating the same |
| CN101552248A (en) * | 2008-03-31 | 2009-10-07 | 卡西欧计算机株式会社 | A semiconductor device and a manufacturing method thereof |
| JP2009267330A (en) * | 2008-03-31 | 2009-11-12 | Casio Comput Co Ltd | Semiconductor device and method of manufacturing the same |
| US20130049195A1 (en) * | 2011-08-23 | 2013-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional Integrated Circuit (3DIC) Formation Process |
| US20150214077A1 (en) * | 2014-01-24 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of Packaging and Dicing Semiconductor Devices and Structures Thereof |
-
2017
- 2017-10-13 CN CN201710954743.6A patent/CN107611095A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090091001A1 (en) * | 2007-10-09 | 2009-04-09 | Nepes Corporation | Crack resistant semiconductor package and method of fabricating the same |
| CN101552248A (en) * | 2008-03-31 | 2009-10-07 | 卡西欧计算机株式会社 | A semiconductor device and a manufacturing method thereof |
| JP2009267330A (en) * | 2008-03-31 | 2009-11-12 | Casio Comput Co Ltd | Semiconductor device and method of manufacturing the same |
| US20130049195A1 (en) * | 2011-08-23 | 2013-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional Integrated Circuit (3DIC) Formation Process |
| US20150214077A1 (en) * | 2014-01-24 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of Packaging and Dicing Semiconductor Devices and Structures Thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11664734B2 (en) | 2020-02-19 | 2023-05-30 | Alpha And Omega Semiconductor International Lp | Flyback converter for controlling on time variation |
| TWI802181B (en) * | 2020-12-30 | 2023-05-11 | 加拿大商萬國半導體國際有限合夥公司 | Semi-wafer level chip scale semiconductor package and method thereof |
| US11721665B2 (en) | 2020-12-30 | 2023-08-08 | Alpha And Omega Semiconductor International Lp | Wafer level chip scale semiconductor package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7960841B2 (en) | Through-hole via on saw streets | |
| CN102569194B (en) | Protecting T-contacts of chip scale packages from moisture | |
| US7750452B2 (en) | Same size die stacked package having through-hole vias formed in organic material | |
| KR101581465B1 (en) | Semiconductor device and manufacturing method thereof | |
| US8053898B2 (en) | Connection for off-chip electrostatic discharge protection | |
| US7585750B2 (en) | Semiconductor package having through-hole via on saw streets formed with partial saw | |
| TWI427754B (en) | Package-in-package using through-hole via die on saw streets | |
| CN104882417B (en) | Integrating passive Flip-Chip Using | |
| US8062929B2 (en) | Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die | |
| JP3660918B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN205645792U (en) | Electronic package | |
| CN105938804A (en) | Wafer level chip scale packaging method and package | |
| CN101110401A (en) | Semiconductor device and semiconductor package structure | |
| US9472451B2 (en) | Technique for wafer-level processing of QFN packages | |
| US20210242151A1 (en) | NIckel Alloy for Semiconductor Packaging | |
| CN107527895A (en) | Collective's manufacture is configured in the method higher than the 3D electronic building bricks to be worked under 1GHz | |
| CN107611096A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| CN107611095A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| CN207250486U (en) | Wafer stage chip encapsulating structure | |
| CN108269768A (en) | Semiconductor package and method of manufacturing the same | |
| CN107611093A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| CN107611094A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| CN107611092A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| US20030071354A1 (en) | Wafer level chip scale package and method of fabricating the same | |
| CN207250485U (en) | Wafer stage chip encapsulating structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Applicant before: SJ Semiconductor (Jiangyin) Corp. |
|
| CB02 | Change of applicant information | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180119 |
|
| RJ01 | Rejection of invention patent application after publication |