CN206877987U - Integrated circuit - Google Patents

Abstract

The utility model discloses a kind of integrated circuit, including：The multiple metal levels being alternately stacked and multiple via layers；Multiple conductive channels in the multiple metal level and the multiple via layer；And device layer, abutted with the bottommost metal level in the multiple metal level, and comprise at least one group of XOR gate, every group of XOR gate includes multiple XOR gates, wherein, the multiple conductive channel forms multiple conductive paths from the top metal level in the multiple metal level to bottommost metal level, each expression logical value that is turned on or off in the multiple conductive path, the multiple XOR gate is connected with the multiple conductive path, for reading the logical value, wherein, the logical value characterizes version number.The utility model can realize the change of logical value by changing any metal level or via layer, and floating is not present in conductive channel, improves antijamming capability.

Description

Integrated circuit

Technical field

The utility model belongs to IC design field, more particularly, to a kind of integrated circuit.

Background technology

In the design cycle of circuit rear end, after the completion of being designed in rear end, image layout system (Graphic is just submitted Design System, GDS) via foundries mask is made to make integrated circuit, and verify whether to meet according to this involved Specification, for example whether can reach required function or whether can reach certain reliability.However, although set in integrated circuit Still may be because each by the specification of substantial amounts of computer or the simplation verification integrated circuit of hardware, entity integrated circuit during meter Some or defect be present in kind factor.If some less problems or defect, can pass through engineering change order The mode of (Engineering Change Order, ECO) is solved；If the problem of larger, defect add new Function, then need to do rear end design cycle again, it is therefore desirable to the version number of these design operations of making identification, therefore current circuit The function of design most likely this number of the integrated circuit version of the record of increase by one.Integrated circuit version number (chip version) is used to identify The version of integrated circuit (Integrated Circuit, IC) integrated circuit.

On the other hand, because integrated circuit has been carried out largely emulating before making, therefore only have a small amount of problem and deposit It is entity integrated circuit.Therefore, when correct the layout coiling of the integrated circuit, to prevent from largely recombining electricity Road, simplation verification and time spent by coiling is laid out again, designer most likely changes these in a manner of ECO and asked again Topic, that is, domain wiring is changed manually.Because the manufacturing cost of mask is fairly expensive, problem can be changed in a manner of ECO Both it can avoid remaking the expense of overall mask, and only need to remake the mask at changed position, save cost.

Similarly, designer can also change the modification connected up into line integrated circuit version number by ECO modes.Fig. 1 is shown The schematic diagram of integrated circuit architecture in the prior art.As shown in figure 1, the integrated circuit shares four metal levels, respectively M1, M2, M3 and M4,3 via layers, respectively VIA1, VIA2, VIA3 are also clipped between 4 metal levels.The integrated circuit is at least deposited In one group of passage, every group of passage includes passage 1 and passage 2.Wherein, passage 1 and passage 2 are two and mutually disconnected independently led to Road.Two passages since M1, through each metal level and via layer, are communicated to M4 always respectively.Wherein, in M1, passage 1 and device There is provided in part layer and stablize low level unit TIEL connections, passage 2 connects with providing the unit TIEH of stable high level in device layer Connect.In M4, passage 1 can draw a read-only logical zero, and passage 2 can draw a read-only logical one.As Wherein one of integrated circuit version number, if the position is designed as logical zero, extraction channel 1, if the position is designed as logic " 1 ", then extraction channel 2.

The integrated circuit can make two passage interconnections by changing the connection of metal wire or through hole, then two it is logical The output result in road is exchanged, to change the output result of passage.Every group of passage exports a logical value, and multigroup passage exports multidigit Logical value, to form the version number of integrated circuit, as long as changing the logical value of some groups of passages, so that it may change the version of integrated circuit This number.

But the integrated circuit structure of binary channels design has the disadvantage that in use：As one in one group of passage When passage is output, another passage easily causes cross-interference issue by floating, floating port；The flat shape complications of passage are circuitous Return, domain modification is cumbersome；The length of the dislocation connection of different metal layer is different, and whether metal level or via layer, It is required for changing the connection of two metal lines or the position of two through holes simultaneously to change the logical value of passage output.

Utility model content

The purpose of this utility model is to provide a kind of logic electricity with identification version number for being placed in IC interior Road domain module.

According to one side of the present utility model, there is provided a kind of integrated circuit, including：Multiple metal levels for being alternately stacked and more Individual via layer；Multiple conductive channels in the multiple metal level and the multiple via layer；And device layer, it is and described Bottommost metal level adjoining in multiple metal levels, and one group of XOR gate is comprised at least, every group of XOR gate includes multiple XORs Door, wherein, the multiple conductive channel is formed from the top metal level in the multiple metal level to bottommost metal level Multiple conductive paths, each in the multiple conductive path, which is turned on or off, represents logical value, the multiple XOR gate with The multiple conductive path connection, for reading the logical value, wherein, the logical value characterizes version number.

Preferably, multiple XOR gates in every group of XOR gate cascade with one another, the first input end warp of each XOR gate Low level or high level are connected to by corresponding metal level or via layer.

Preferably, the second input of the first XOR gate is connected to low level or high level via corresponding metal level.

Preferably, the logical value is 0 or 1.

Preferably, multiple metal levels or multiple via layers stablize low electricity by being provided in corresponding conductive path and device layer The unit TIEH connections of the flat stable high level of unit TIEL or offer.

The conductive channel for being preferably located at the multiple metal level shows as a section lead, positioned at the multiple via layer Conductive channel show as a through hole.

Wire corresponding to the conductive channel being preferably located in the multiple metal level can form two conductive paths, its A kind of middle conductive path makes its corresponding conductive layer be connected to low level, and another conductive path connects its corresponding conductive layer It is connected to high level.

Through hole corresponding to the conductive channel being preferably located in the via layer can form two kinds of through hole positions, its In, a kind of through hole position makes its corresponding via layer be connected to low level, and another through hole position makes its corresponding Via layer is connected to high level.

Preferably, each metal level or the conductive channel of each via layer via different conductive paths directly and low level Or high level connection.

Preferably, each XOR gate via each via layer it is corresponding to two through holes.

Preferably, the multiple metal level includes multiple regions being spaced apart respectively, and the multiple via layer is used for The metal level is connected in different regions, wherein, each region is connected with corresponding one group of XOR gate.

Preferably, multigroup XOR gate reads the logical value in multiple regions to form version number respectively.The utility model provides Integrated circuit, multiple conductive channels that multiple metal levels and multiple via layers are set formed from the top metal level to Multiple conductive paths of bottommost metal level, in device layer at least provided with one group of XOR gate, wherein, it is multiple in one group of XOR gate XOR gate is cascaded with one another, and low level or high level are connected to via multiple conductive paths, and exports logical value to form version This number.The integrated circuit can change each XOR gate and height by changing the metal wire of metal level or the position of through hole Level or low level connection, to change the logical value of one group of XOR gate output.In addition, metal wire or through hole using directly with High level or the mode of low level connection, in revision, need to only move the position of a wires or a through hole , in the absence of the output result of floating.

Further, integrated circuit provided by the utility model can record whole design cycle (Flow) number respectively And some Flow ECO number.

Brief description of the drawings

By the description to the utility model embodiment referring to the drawings, of the present utility model above-mentioned and other mesh , feature and advantage will be apparent from, in the accompanying drawings：

Fig. 1 shows the integrated circuit structure schematic diagram of 4 metal levels in the prior art；

Fig. 2 shows the floor map of the integrated circuit of 4 metal levels in the utility model first embodiment；

Fig. 3 a- Fig. 3 b show a logic in M4 layers and VIA3 layers to version number in the utility model first embodiment The example that value is modified；

Fig. 4 shows the three-dimensional structure diagram of the integrated circuit of 4 metal levels in the utility model embodiment；

Fig. 5 shows Fig. 4 partial enlarged drawing；

Fig. 6 shows the domain of the integrated circuit of 4 metal levels in the utility model first embodiment；

Fig. 7 a- Fig. 7 b show a logic in M4 layers and VIA3 layers to version number in the utility model first embodiment The domain that value is modified；

Fig. 8 shows the floor map of the integrated circuit of 4 metal levels in the utility model second embodiment.

Embodiment

Various embodiments of the present utility model are more fully described hereinafter with reference to accompanying drawing.In various figures, identical Element is represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not drawn to paint System.

The utility model can be presented in a variety of manners, some of examples explained below.In specification in the whole text and right "comprising" of the claim mentioned in is for an open term, therefore should be construed to " include but be not limited to ".In addition, " An electric connection " word is comprising any direct and indirect electrical connection herein.Therefore, if the first device of described in the text one Be electrically connected at a second device, then represent the first device and may be directly connected to the second device, or through other devices or Connection means are coupled indirectly to the second device.

The utility model embodiment is related to a kind of integrated circuit.

First the structure of integrated circuit is illustrated.

The integrated circuit includes：The multiple metal levels being alternately stacked and multiple via layers；Positioned at the multiple metal level and Multiple conductive channels in the multiple via layer；And the bottommost metal level in device layer, with the multiple metal level is adjacent Connecing, and comprise at least one group of XOR gate, every group of XOR gate includes multiple XOR gates, wherein, the multiple conductive channel is formed From the top metal level in the multiple metal level to multiple conductive paths of bottommost metal level, the multiple conductive path In each be turned on or off represent logical value, the multiple XOR gate is connected with the multiple conductive path, for reading The logical value, wherein, the logical value characterizes version number.

Multiple XOR gates in every group of XOR gate cascade with one another, and the first input end of each XOR gate is via corresponding Metal level or via layer are connected to low level or high level.

Second input of the first XOR gate is connected to low level or high level via corresponding metal level.

It is appreciated that low level, high level are the terms of this area, in the utility model embodiment, low level is exactly generation Table logical value is the level of " 0 ", and high level is exactly to represent level of the logical value as " 1 ".Preferably, multiple metal levels or multiple Via layer stablizes low level unit TIEL by offer in corresponding conductive path and device layer or provides stable high level Unit TIEH connections.Can also be that multiple metal levels or multiple via layers are grounded or connect power supply electricity by corresponding conductive path Pressure.

A section lead is shown as positioned at the conductive channel of the multiple metal level, the conduction positioned at the multiple via layer is led to Road shows as a through hole.

In each metal layer, each conductive channel shows as a section lead, and the wire can be by shift position in phase The conductive layer answered forms two conductive paths, and one of which conductive path makes its corresponding conductive layer be connected to low level, and another A kind of conductive path makes its corresponding conductive layer be connected to high level.

In each via layer, each conductive channel shows as a through hole, and the through hole can be by shift position in phase The via layer answered forms two kinds of through hole positions, and one of which through hole position makes its corresponding via layer be connected to low electricity Flat, another through hole position makes its corresponding via layer be connected to high level.

Each metal level or the conductive channel of each via layer are electric directly with low level or height via different conductive paths Flushconnection.

Each XOR gate via each via layer it is corresponding to two through holes.

One group of XOR gate is set in integrated circuits, multiple XOR gates cascade with one another, and via correspondingly conductive layer or logical Aperture layer is connected to low level or high level, exports one of a logical value as version number so that integrated circuit version number Modification can realize the modification of version number independent of specific layer in any metal level or via layer.

If version number is made up of multi-bit logical value (chipid [0]-chipid [i]), in integrated circuits will need Each metal level is divided into multiple regions being spaced apart, and each region is connected with corresponding one group of XOR gate, Mei Yiqu Domain corresponds to a logical value of version number respectively.Each logical value both corresponds to a region in version number, as long as any One region makes an amendment, it is possible to realizes any change of each logical value of version number.

Below by taking the integrated circuit of 4 metal levels as an example, integrated circuit structure is specifically described.Fig. 2 shows this The floor map of the integrated circuit of 4 metal levels in utility model first embodiment；Fig. 4 shows the utility model embodiment In 4 metal levels integrated circuit three-dimensional structure diagram；Fig. 5 shows Fig. 4 partial enlarged drawing.

With reference to Fig. 2, Fig. 4 and Fig. 5, the integrated circuit shares 4 metal levels, respectively M1, M2, M3 and M4,4 metal levels Between also clip 3 via layers, respectively VIA1, VIA2, VIA3, the metal level M1 of bottommost lower section also abuts 1 device Layer.

The integrated circuit also includes the first conductive channel A1 being located in M1, the second conductive channel A2 in M2, position The 3rd conductive channel A3 in M3, the 4th conductive channel A4 in M4, and the 5th conductive channel in VIA1 B1, the 6th conductive channel B2 in VIA2, the 7th conductive channel B3 in VIA3.Wherein, the first conductive channel is extremely 4th conductive channel (A1-A4) shows as a section lead respectively in the first metal layer into the 4th metal level (M1-M4)；5th leads Electric channel into third through-hole layer (VIA1-VIA3) shows as one respectively to the 7th conductive channel (B1-B3) in first through hole layer Individual through hole.

First conductive channel is to the 4th conductive channel (A1-A4) and the 5th conductive channel to the 7th conductive channel (B1- B3 multiple conductive paths from the 4th metal level to the first metal layer (M1-M4)) are formed.Each each in conductive path It is turned on or off and represents logical value.

Device layer comprises at least one group of XOR gate, and every group of XOR gate includes 6 XOR gates, i.e. the first XOR gate is to the 6th different OR gate (XOR1-XOR6).Each XOR gate is two input XOR gates.Wherein, the first conductive channel A1 and the 5th conductive channel B1 is connected with the first XOR gate XOR1 first input end and the second input respectively；Second conductive channel A2 and the first XOR gate XOR1 output end is connected with the second XOR gate XOR2 first input end and the second input respectively；6th conductive channel B2 and Second XOR gate XOR2 output end is connected with the 3rd XOR gate XOR3 first input end and the second input respectively；3rd leads Electric channel A3 and the 3rd XOR gate XOR3 the output end first input end and the second input with the 4th XOR gate XOR4 respectively Connection；7th conductive channel B3 and the 4th XOR gate XOR4 output end respectively with the 5th XOR gate XOR5 first input end and Second input connects；4th conductive channel A4 and the 5th XOR gate XOR5 output end is defeated with the first of the 6th XOR gate respectively Enter end to connect with the second input；6th XOR gate XOR6 output end reads logical value chipid [i].The logical value table Levy version number.

First conductive channel is to the 4th conductive channel (A1-A4) and the 5th conductive channel to the 7th conductive channel (B1- B3) by providing low level unit TIEL in corresponding conductive path and device layer or providing the unit TIEH of stable high level Connection.

As shown in figure 5, in the first metal layer M1, the first conductive channel A1 can make itself and low electricity by shift position The connection of flat or high level；Two conductive paths A11 and A12 can be formed, wherein, conductive path A11 makes the first XOR gate First input end is connected with low level；Conductive path A12 makes the first input end of the first XOR gate be connected with high level.

In first through hole layer VIA1, the 5th conductive channel B1 can make itself and low level or high electricity by shift position Flushconnection；Two lead to the hole site B11 and B12 can be formed, wherein, when the 5th conductive channel B1 is located at lead to the hole site B11, First XOR gate XOR1 the second input is connected with low level, and the first XOR gate XOR1 the second input and high level connect Connect.

Similarly, in other metal levels or via layer, the position by changing conductive channel makes and the conductive channel The input of connected XOR gate is connected with low level or high level.

Fig. 6 shows the domain of the integrated circuit of 4 metal levels in the utility model first embodiment.Such as Fig. 2 and Fig. 6 institutes Show, the first XOR gate to the 6th XOR gate (XOR1-XOR6) cascades with one another, and the first XOR gate to the 6th XOR gate (XOR1- XOR6 first input end) is respectively via the first metal layer M1, second metal layer M2, the second via layer VIA2, the 3rd metal level M3, third through-hole layer VIA3 and the 4th metal level M4 are connected to low level, and the first XOR gate XOR1 the second input is via One via layer VIA1 is connected to low level.Now, it is " 0 " that XOR6, which exports logical value chipid [i],.In fig. 2, each metal level The conductive path connected with each via layer with low level turns on, and the conductive path being connected with high level disconnects.

If changing the version number of integrated circuit, for example the logical value of this group of XOR gate output is changed into " 1 ", then can change gold Belong to any one in layer and via layer, an input of XOR gate is connected with high level, then the logic of this group of XOR gate Value chipid [i] is changed into " 1 ".

Fig. 3 a- Fig. 3 b show a logic in M4 layers and VIA3 layers to version number in the utility model first embodiment The example that value is modified.Fig. 7 a- Fig. 7 b are shown in the utility model first embodiment in M4 layers and VIA3 layers to version number The domain modified of a logical value.

As shown in Figure 7a, mobile 4th conductive channel A4 connects the 6th XOR gate XOR2 first input end and high level Connect, correspondingly, in fig. 3 a, the conductive path that the 4th conductive layer M4 is connected with low level disconnects, the conduction being connected with high level Path turns on.

As shown in Figure 7b, mobile 7th conductive channel B3 connects the 5th XOR gate XOR2 first input end and high level Connect, correspondingly, in fig 3b, the conductive path that third through-hole layer VIA3 is connected with low level disconnects, and what is be connected with high level leads Power path turns on.

Integrated circuit, formed in multiple conductive channels that multiple metal levels and multiple via layers are set from top gold Belong to layer to bottommost metal level multiple conductive paths, in device layer at least provided with one group of XOR gate, wherein, in one group of XOR gate Multiple XOR gates cascade with one another, be connected to low level or high level via multiple conductive paths, and export logical value with Form version number.The integrated circuit can change each XOR by changing the metal wire of metal level or the position of through hole Door and high level or low level connection, to change the logical value of one group of XOR gate output.In addition, metal wire or through hole use The mode being directly connected with high level or low level, in revision, only it need to move a wires or a through hole Position, in the absence of the output result of floating, improve antijamming capability.

Fig. 8 shows the floor map of the integrated circuit of 4 metal levels in the utility model second embodiment.

As shown in figure 8, each metal level includes multiple regions being spaced apart, and each region with corresponding one group XOR gate is connected, and exports corresponding logical value, i.e. chipid [0]-chipid [i], wherein, i is natural number.Each region A logical value of version number is corresponded to respectively.

Illustrated by taking i=7 as an example, wherein, chipid [7:0] chipid [7 can be divided into:4]-chipid[3:0] two Part, 4 binary systems can also be represented by 1 16 system.I.e. 8 binary version numbers can also be by two hexadecimals come table Show.Wherein, chipid [7:4] it is used for recording Flow number, chipid [3:0] it is used for recording current Flow ECO number.

It is initial version, i.e., if not doing ECO processing when first time carrying out Flow：chipid[7:4]= 0000, chipid [3:0]=0000, it is denoted as 00 version；If an ECO processing is carried out, chipid [7:4] remain as 0000, and chipid [3:0] it is changed into " 0001 ", is denoted as 01 version；Second of ECO processing is on the basis of first time ECO correcting Upper progress, then chipid [7:4] 0000 is remained as, and chipid [3:0] it is changed into " 0010 ", is denoted as 02 version.It follows that Version number information can be completely corresponding with ECO number of processing, can truly reflect and carry out ECO number of processing.

Each ECO processing has the change that various ways realize logical value.It can specifically be looked into by corresponding modification domain See.

When carrying out Flow second, if not doing ECO processing, chipid [7:4]=0001, chipid [3:0] =0000, it is denoted as 10 versions；An ECO processing is carried out, then chipid [7:4] 0001 is remained as, and chipid [3:0] it is changed into " 0001 ", it is denoted as 11 versions；Second of ECO processing is carried out on the basis of the correcting of first time ECO, then chipid [7:4] Remain as 0001, and chipid [3:0] it is changed into " 0010 ", is denoted as 12 versions.

It can thus be seen that version number information can also be corresponding with carrying out Flow number, it can also truly reflect progress Flow number.

The Flow of different numbers and different numbers ECO processing, can be represented through the above way, can at most be produced 256 kinds of version numbers.

Logic circuit domain module provided by the utility model with version number in integrated circuits, can record respectively Whole design cycle Flow number and some Flow ECO number.

According to embodiment of the present utility model as described above, these embodiments do not have all details of detailed descriptionthe, Also it is only described specific embodiment not limit the utility model.Obviously, as described above, many modification and change can be made Change.This specification is chosen and specifically describes these embodiments, is to preferably explain that principle of the present utility model and reality should With so that skilled artisan can repairing using the utility model and on the basis of the utility model well Change use.The scope of protection of the utility model should be defined by the scope that the utility model claims are defined.

Claims (12)

1. a kind of integrated circuit, including：

The multiple metal levels being alternately stacked and multiple via layers；

Multiple conductive channels in the multiple metal level and the multiple via layer；And

Bottommost metal level adjoining in device layer, with the multiple metal level, and one group of XOR gate is comprised at least, every group is different OR gate includes multiple XOR gates,

Wherein, the multiple conductive channel is formed from the top metal level in the multiple metal level to bottommost metal level Multiple conductive paths, each in the multiple conductive path, which is turned on or off, represents logical value,

The multiple XOR gate is connected with the multiple conductive path, for reading the logical value, wherein, the logical value table Levy version number.

2. integrated circuit according to claim 1, wherein, multiple XOR gates in every group of XOR gate cascade with one another,

The first input end of each XOR gate is connected to low level or high level via corresponding metal level or via layer.

3. integrated circuit according to claim 2, wherein, the second input of the first XOR gate is via corresponding metal level It is connected to low level or high level.

4. integrated circuit according to claim 1, the logical value is 0 or 1.

5. integrated circuit according to claim 4, wherein, multiple metal levels or multiple via layers pass through corresponding conductive path The unit TIEH that footpath stablizes low level unit TIEL or the stable high level of offer with being provided in device layer is connected.

6. integrated circuit according to claim 1, wherein, show as one section positioned at the conductive channel of the multiple metal level Wire, a through hole is shown as positioned at the conductive channel of the multiple via layer.

7. integrated circuit according to claim 6, wherein, led corresponding to the conductive channel in the multiple metal level Line can form two conductive paths, and one of which conductive path makes its corresponding conductive layer be connected to low level, and another kind is led Power path makes its corresponding conductive layer be connected to high level.

8. integrated circuit according to claim 6, wherein, through hole corresponding to the conductive channel in the via layer can Two kinds of through hole positions are formed, wherein, a kind of through hole position makes its corresponding via layer be connected to low level, another Through hole position makes its corresponding via layer be connected to high level.

9. integrated circuit according to claim 8, wherein, the conductive channel of each metal level or each via layer is not via Same conductive path is directly connected with low level or high level.

10. integrated circuit according to claim 8, wherein, each XOR gate via each via layer it is corresponding To two through holes.

11. integrated circuit according to claim 3, wherein, the multiple metal level respectively includes multiple be spaced apart Region, the multiple via layer be used for the metal level is connected in different regions, wherein, each region with corresponding one group XOR gate is connected.

12. integrated circuit according to claim 11, wherein, multigroup XOR gate read respectively the logical value in multiple regions with Form version number.