CN206133410U - A JBOD board based on general storage system - Google Patents
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Abstract
本实用新型公开一种基于通用存储系统的JBOD板,涉及计算机零部件,安装使用在通用存储系统中,该JBOD板上设置有若干高速连接器,用于连接硬盘背板,JBOD板通过硬盘背板与HDD信号直接互联,以扩展系统存储空间;该JBOD板上还设置有1X2 e‑MiniSAS HD接口,其中一个口连接上游SAS控制器,另一个口接下一级同样JBOD板,用于做系统级联存储扩展;并且该JBOD板上设置了SAS3.0 Re‑driver芯片,用于增强JBOD板SAS3.0信号驱动能力;这样该JBOD板实现了JBOD级联扩展以及SAS3.0信号长距离传输。
The utility model discloses a JBOD board based on a general storage system, which relates to computer components and is installed and used in the general storage system. The JBOD board is provided with several high-speed connectors for connecting hard disk backplanes. The JBOD board passes through the hard disk backplane. The board is directly interconnected with the HDD signal to expand the system storage space; the JBOD board is also equipped with a 1X2 e-MiniSAS HD interface, one of which is connected to the upstream SAS controller, and the other is connected to the same next-level JBOD board for System cascade storage expansion; and the JBOD board is equipped with a SAS3.0 Re-driver chip to enhance the JBOD board SAS3.0 signal drive capability; thus the JBOD board realizes JBOD cascade expansion and SAS3.0 signal long distance transmission.
Description
技术领域technical field
本实用新型涉及计算机零部件,具体的说是一种基于通用存储系统的JBOD板。The utility model relates to computer components, in particular to a JBOD board based on a general storage system.
背景技术Background technique
存储系统是指计算机中由存放程序和数据的各种存储设备、控制部件及管理信息调度的设备(硬件)和算法(软件)所组成的系统。计算机的主存储器不能同时满足存取速度快、存储容量大和成本低的要求,在计算机中必须有速度由慢到快、容量由大到小的多级层次存储器,以最优的控制调度算法和合理的成本,构成具有性能可接受的存储系统。存储系统的性能在计算机中的地位日趋重要。A storage system refers to a computer system consisting of various storage devices for storing programs and data, control components, and devices (hardware) and algorithms (software) for managing information scheduling. The main memory of the computer cannot meet the requirements of fast access speed, large storage capacity and low cost at the same time. In the computer, there must be a multi-level memory with a speed from slow to fast and a capacity from large to small. With the optimal control scheduling algorithm and Reasonable cost constitutes a storage system with acceptable performance. The performance of the storage system plays an increasingly important role in the computer.
JBOD(Just a Bunch Of Disks,磁盘簇)是存储领域中在一个底板上安装的带有多个磁盘驱动器的存储设备。和RAID阵列不同,JBOD没有前端逻辑来管理磁盘上的数据分布,相反,每个磁盘进行单独寻址,作为分开的存储资源,或者基于主机软件的一部分,或者是RAID组的一个适配器卡。JBOD用来指还没有根据RAID(独立磁盘冗余阵列)系统配置以增加容错率和改进数据访问性能的电脑硬盘。JBOD使用独立的磁盘并没有带来任何好处,也不能提供任何RAID所能带来的容错或是更好的性能等好处。JBOD (Just a Bunch Of Disks) is a storage device with multiple disk drives installed on a backplane in the storage field. Unlike RAID arrays, JBODs have no front-end logic to manage the distribution of data across the disks. Instead, each disk is individually addressed as a separate storage resource, either based on part of the host software, or an adapter card in the RAID group. JBOD is used to refer to computer hard drives that have not been configured according to the RAID (Redundant Array of Independent Disks) system to increase fault tolerance and improve data access performance. Using separate disks for JBOD does not provide any benefits, nor does it provide any of the fault tolerance or better performance benefits that RAID can provide.
实用新型内容Utility model content
本实用新型针对目前技术发展的需求和不足之处,提供一种基于通用存储系统的JBOD板。The utility model provides a JBOD board based on a general storage system aiming at the needs and deficiencies of the current technical development.
本实用新型所述一种基于通用存储系统的JBOD板,解决上述技术问题采用的技术方案如下:所述一种基于通用存储系统的JBOD板,安装应用在通用存储系统中,其整体结构为一个PCB板卡,其上集成有一个PM8054芯片、一个CPLD芯片、若干高速连接器、SAS3.0 Re-driver 芯片、1X2 e-MiniSAS HD接口;其中,所述PM8054芯片与所述CPLD芯片、各个高速连接器、SAS3.0 Re-driver 芯片、1X2 e-MiniSAS HD接口均连接通信;所述PM8054芯片用于存储扩展以及系统级联;所述CPLD芯片用于控制JBOD板上电时序以及相关逻辑控制;所述高速连接器用于连接硬盘背板以扩展系统存储空间;所述1X2 e-MiniSAS HD接口中一个接口连接系统中SAS控制器,另一个接口接下一级同样JBOD板用于做系统级联存储扩展;所述SAS3.0 Re-driver 芯片用于增强JBOD板SAS3.0信号驱动能力。A JBOD board based on a general storage system described in the utility model adopts the following technical solution to solve the above technical problems: the JBOD board based on a general storage system is installed and applied in a general storage system, and its overall structure is a PCB board card, integrated with a PM8054 chip, a CPLD chip, several high-speed connectors, SAS3.0 Re-driver chip, 1X2 e-MiniSAS HD interface; wherein, the PM8054 chip and the CPLD chip, each high-speed The connector, SAS3.0 Re-driver chip, and 1X2 e-MiniSAS HD interface are all connected to communicate; the PM8054 chip is used for storage expansion and system cascading; the CPLD chip is used to control the power-on sequence of the JBOD board and related logic control ; The high-speed connector is used to connect the hard disk backplane to expand the system storage space; one of the 1X2 e-MiniSAS HD interfaces is connected to the SAS controller in the system, and the other interface is connected to the same JBOD board of the next level for system level Connected storage expansion; the SAS3.0 Re-driver chip is used to enhance the SAS3.0 signal driving capability of the JBOD board.
优选的,所述JBOD板上设置有5个Xcede HD系列高速连接器。Preferably, five Xcede HD series high-speed connectors are arranged on the JBOD board.
优选的,所述JBOD板上设置有两个SAS3.0 Re-driver 芯片。Preferably, two SAS3.0 Re-driver chips are arranged on the JBOD board.
优选的,JBOD板上还设置有3个Xcede HD系列电源连接器、存储器以及硬件监控芯片,所述电源连接器、存储器、硬件监控芯片均与所述PM8054芯片连接通信;所述硬件监控芯片并分别与所述CPLD芯片、高速连接器连接通信;所述电源连接器通过插接硬盘背板取电为JBOD板供电。Preferably, 3 Xcede HD series power connectors, memory and hardware monitoring chips are also arranged on the JBOD board, and the power connector, memory, and hardware monitoring chips are all connected and communicated with the PM8054 chip; It is respectively connected and communicated with the CPLD chip and the high-speed connector; the power connector is plugged into the hard disk backplane to obtain power for the JBOD board.
优选的,所述存储器包括PROM、SRAM静态随机存取存储器、NVSRAM。Preferably, the memory includes PROM, SRAM static random access memory, NVSRAM.
优选的,所述硬盘监控芯片采用NCT7904D。Preferably, the hard disk monitoring chip adopts NCT7904D.
优选的,所述JBOD板上还设置有时钟芯片、UART Debug Header、FRU现场可更换单元,其中,UART Debug Header用于UART调试,并且所述时钟芯片、UART Debug Header、FRU均与所述PM8054芯片连接通信。Preferably, a clock chip, UART Debug Header, and FRU field replaceable unit are also arranged on the JBOD board, wherein the UART Debug Header is used for UART debugging, and the clock chip, UART Debug Header, and FRU are all connected to the PM8054 Chip connection communication.
优选的,所述JBOD板上设置有2个Xcede HD系列导削,用于与硬盘背板互联时起导向作用。Preferably, two Xcede HD series guides are provided on the JBOD board to serve as guides when interconnecting with the hard disk backplane.
本实用新型所述一种基于通用存储系统的JBOD板与现有技术相比具有的有益效果是:在通用存储系统中,本实用新型所述JBOD板一端通过硬盘背板与HDD直接互联,形成本身系统的存储空间;另一端通过1X2 e-MiniSAS HD接口实现系统级联存储扩展;并且通过SAS3.0 Re-driver 芯片增强JBOD板 SAS3.0信号驱动能力,从而实现了JBOD级联扩展以及SAS3.0信号长距离传输;并且,本实用新型构思新颖、使用方便,存储扩展功能较强,具有较好的市场推广价值。Compared with the prior art, the JBOD board based on the general storage system described in the utility model has the beneficial effect that: in the general storage system, one end of the JBOD board described in the utility model is directly interconnected with the HDD through the hard disk backplane, forming The storage space of its own system; the other end realizes system cascade storage expansion through the 1X2 e-MiniSAS HD interface; and enhances the SAS3.0 signal drive capability of the JBOD board through the SAS3.0 Re-driver chip, thereby realizing JBOD cascade expansion and SAS3 .0 signal long-distance transmission; moreover, the utility model is novel in conception, easy to use, strong in storage expansion function, and has good market promotion value.
附图说明Description of drawings
附图1为所述JBOD板的结构示意图。Accompanying drawing 1 is the structural representation of described JBOD plate.
具体实施方式detailed description
为使本实用新型的目的、技术方案和优点更加清楚明白,以下结合具体实施例,对本实用新型所述一种基于通用存储系统的JBOD板进一步详细说明。In order to make the purpose, technical solution and advantages of the utility model clearer, the JBOD board based on the universal storage system described in the utility model will be further described in detail below in conjunction with specific embodiments.
针对通用存储系统,本实用新型提出了一种基于通用存储系统的JBOD板,安装使用在通用存储系统中,该JBOD板上设置有若干高速连接器,用于连接硬盘背板,JBOD板通过硬盘背板与HDD信号直接互联,以扩展系统存储空间;该JBOD板上还设置有1X2 e-MiniSASHD接口,其中一个口连接上游SAS控制器,另一个口接下一级同样JBOD板,用于做系统级联存储扩展;并且该JBOD板上设置了SAS3.0 Re-driver 芯片,用于增强JBOD板SAS3.0信号驱动能力;这样该JBOD板实现了JBOD级联扩展以及SAS3.0信号长距离传输。Aiming at the general storage system, the utility model proposes a JBOD board based on the general storage system, installed and used in the general storage system, the JBOD board is provided with several high-speed connectors for connecting the hard disk backplane, and the JBOD board passes through the hard disk The backplane is directly interconnected with the HDD signal to expand the system storage space; the JBOD board is also equipped with a 1X2 e-MiniSASHD interface, one of which is connected to the upstream SAS controller, and the other is connected to the same next-level JBOD board for System cascade storage expansion; and the JBOD board is equipped with a SAS3.0 Re-driver chip to enhance the JBOD board SAS3.0 signal drive capability; thus the JBOD board realizes JBOD cascade expansion and SAS3.0 signal long distance transmission.
实施例:Example:
本实施例一种基于通用存储系统的JBOD板,其整体结构如附图1所示,所述JBOD板为一个PCB板卡,安装应用在通用存储系统中,其上集成有一个SAS3.0 Expander 36 Ports(PM8054)芯片、一个CPLD芯片、若干高速连接器、SAS3.0 Re-driver 芯片、1X2 e-MiniSASHD接口;其中,所述PM8054芯片与所述CPLD芯片、各个高速连接器、SAS3.0 Re-driver 芯片、1X2 e-MiniSAS HD接口均连接通信;所述PM8054芯片用于存储扩展以及系统级联;所述CPLD芯片用于控制JBOD板上电时序以及相关逻辑控制;所述高速连接器用于连接硬盘背板以扩展系统存储空间;所述1X2 e-MiniSAS HD接口其中一个口连接上游SAS控制器,另一个口接下一级同样JBOD板用于做系统级联存储扩展;所述SAS3.0 Re-driver 芯片用于增强JBOD板SAS3.0信号驱动能力。In this embodiment, a JBOD board based on a general-purpose storage system has an overall structure as shown in Figure 1. The JBOD board is a PCB card installed and applied in a general-purpose storage system, and a SAS3.0 Expander is integrated on it. 36 Ports (PM8054) chip, a CPLD chip, several high-speed connectors, SAS3.0 Re-driver chip, 1X2 e-MiniSASHD interface; wherein, the PM8054 chip and the CPLD chip, each high-speed connector, SAS3.0 The Re-driver chip and the 1X2 e-MiniSAS HD interface are all connected for communication; the PM8054 chip is used for storage expansion and system cascading; the CPLD chip is used for controlling the power-on sequence of the JBOD board and related logic control; the high-speed connector is used for It is used to connect the hard disk backplane to expand the system storage space; one port of the 1X2 e-MiniSAS HD interface is connected to the upstream SAS controller, and the other port is connected to the same JBOD board of the next level for system cascade storage expansion; the SAS3 The .0 Re-driver chip is used to enhance the SAS3.0 signal driving capability of the JBOD board.
本实施例所述JBOD板中,如附图1所示,设置有5个Xcede HD系列高速连接器(CN0、CN1、CN2、CN3、CN4),用于连接硬盘背板,而硬盘背板上设置有机械式硬盘HDD;所述1X2 e-MiniSAS HD接口,支持2组X4 Lane SAS3.0信号扩展,每根e-MiniSAS HD线缆支持最高速率为12Gb/s。在通用存储系统中,所述JBOD板一端通过硬盘背板与HDD之间12GT/s SAS3.0信号直接互连,以扩展本身系统存储空间;所述JBOD板另一端通过e-MiniSAS HD线缆连接JBOD板板载的1X2 e-MiniSAS HD接口,其中一个接口连接上游SAS控制器e-MiniSAS HD接口,另一个接口接下一级同样JBOD板的e-MiniSAS HD接口,用于做系统级联存储扩展。In the JBOD board described in this embodiment, as shown in Figure 1, five Xcede HD series high-speed connectors (CN0, CN1, CN2, CN3, CN4) are provided for connecting the hard disk backplane, and the hard disk backplane It is equipped with a mechanical hard disk HDD; the 1X2 e-MiniSAS HD interface supports 2 sets of X4 Lane SAS3.0 signal expansion, and each e-MiniSAS HD cable supports a maximum rate of 12Gb/s. In a general storage system, one end of the JBOD board is directly interconnected with the 12GT/s SAS3.0 signal between the hard disk backplane and the HDD to expand the storage space of the system itself; the other end of the JBOD board is connected through the e-MiniSAS HD cable Connect to the 1X2 e-MiniSAS HD interface on the JBOD board, one of which is connected to the e-MiniSAS HD interface of the upstream SAS controller, and the other interface is connected to the e-MiniSAS HD interface of the same JBOD board at the next level for system cascading storage expansion.
本实施例所述JBOD板中,如附图1所示,所述SAS3.0 Re-driver 芯片设置有两个,能够支持X8 Lane SAS3.0 RX端信号的驱动。同时,该JBOD板上还设置有3个Xcede HD系列电源连接器(PWR0、PWR1、PWR2)、存储器以及硬件监控芯片,所述电源连接器、存储器、硬件监控芯片均与所述PM8054芯片连接通信;所述硬件监控芯片并分别与所述CPLD芯片、高速连接器连接通信;所述电源连接器能够插接在所述硬盘背板上,通过硬盘背板取电为JBOD板供电;所述存储器包括PROM(可编程只读存储器)、SRAM静态随机存取存储器、NVSRAM(非易失性SRAM);所述硬盘监控芯片采用NCT7904D。In the JBOD board described in this embodiment, as shown in FIG. 1 , there are two SAS3.0 Re-driver chips, which can support the driving of X8 Lane SAS3.0 RX terminal signals. At the same time, the JBOD board is also equipped with three Xcede HD series power connectors (PWR0, PWR1, PWR2), memory and hardware monitoring chip, and the power connector, memory, and hardware monitoring chip are all connected and communicated with the PM8054 chip The hardware monitoring chip is connected and communicated with the CPLD chip and the high-speed connector respectively; the power connector can be plugged on the hard disk backplane, and is powered by the hard disk backplane to supply power for the JBOD board; the memory includes PROM (programmable read-only memory), SRAM static random access memory, NVSRAM (non-volatile SRAM); the hard disk monitoring chip uses NCT7904D.
此外,本实施例所述JBOD板中,还设置有时钟芯片(Clock)、UART Debug Header、FRU(Field Replace Unit) 现场可更换单元,其中,UART Debug Header用于UART调试,UART(Universal Asynchronous Receiver/Transmitter)是一种异步收发传输器;并且所述时钟芯片、UART Debug Header、FRU均与所述PM8054芯片连接通信。In addition, the JBOD board described in this embodiment is also provided with a clock chip (Clock), a UART Debug Header, and a FRU (Field Replace Unit) field replaceable unit, wherein the UART Debug Header is used for UART debugging, and the UART (Universal Asynchronous Receiver /Transmitter) is an asynchronous transceiver; and the clock chip, UART Debug Header, and FRU are all connected to the PM8054 chip for communication.
为了方便硬盘背板的安装,所述JBOD板上设置有2个Xcede HD系列导削,用于与硬盘背板互联时起导向作用。采用该实用新型,可以快捷高效的实现基于通用存储系统的JBOD板设计,实现了JBOD级联扩展以及SAS3.0信号长距离传输。In order to facilitate the installation of the hard disk backplane, two Xcede HD series guides are provided on the JBOD board to play a guiding role when interconnecting with the hard disk backplane. By adopting the utility model, the JBOD board design based on the general storage system can be quickly and efficiently realized, and the JBOD cascading expansion and the long-distance transmission of SAS3.0 signals are realized.
上述具体实施方式仅是本实用新型的具体个案,本实用新型的专利保护范围包括但不限于上述具体实施方式,任何符合本实用新型的权利要求书的且任何所属技术领域的普通技术人员对其所做的适当变化或替换,皆应落入本实用新型的专利保护范围。The above-mentioned specific embodiments are only specific cases of the present utility model, and the scope of patent protection of the present utility model includes but not limited to the above-mentioned specific embodiments. Appropriate changes or substitutions made should fall within the patent protection scope of the present utility model.
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Cited By (2)
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CN110703870A (en) * | 2019-09-12 | 2020-01-17 | 苏州浪潮智能科技有限公司 | JBOD mainboard and storage system |
CN114780033A (en) * | 2022-04-22 | 2022-07-22 | 苏州浪潮智能科技有限公司 | JBOD cascade system, storage resource allocation method and device |
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CN110703870A (en) * | 2019-09-12 | 2020-01-17 | 苏州浪潮智能科技有限公司 | JBOD mainboard and storage system |
CN114780033A (en) * | 2022-04-22 | 2022-07-22 | 苏州浪潮智能科技有限公司 | JBOD cascade system, storage resource allocation method and device |
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