CN107688376A - A kind of hard disk backboard for supporting adaptive hard-disk interface - Google Patents
A kind of hard disk backboard for supporting adaptive hard-disk interface Download PDFInfo
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Abstract
Description
技术领域technical field
本发明属于硬盘背板领域,具体涉及一种支持自适应硬盘接口的硬盘背板。The invention belongs to the field of hard disk backplanes, and in particular relates to a hard disk backplane supporting self-adaptive hard disk interfaces.
背景技术Background technique
服务器前置硬盘当前主流硬盘是SATA和SAS硬盘以及SSD,但由于NVME SSD硬盘价格昂贵,普及有限,各个服务器厂商所生产硬盘背板均以支持SATA和SAS硬盘为主,随着服务器产业的快速发展,NVME硬盘以其更低的延时,更高的传输性能,更低的功耗控制,不断进化,从高端到主流,需求日益增多,在NVME硬盘日益增多的市场前提下,旧背板已经无法满足实际需求。The current mainstream hard disks for front-end hard disks of servers are SATA and SAS hard disks and SSDs. However, due to the high price and limited popularity of NVME SSD hard disks, the hard disk backplanes produced by various server manufacturers mainly support SATA and SAS hard disks. With the rapid development of the server industry With the development of NVME hard disk, with its lower latency, higher transmission performance, and lower power consumption control, it is constantly evolving, from high-end to mainstream, and the demand is increasing. It has been unable to meet the actual needs.
此为现有技术的不足,因此,针对现有技术中的上述缺陷,提供一种支持自适应硬盘接口的硬盘背板,是非常有必要的。This is the deficiency of the prior art. Therefore, it is very necessary to provide a hard disk backplane supporting an adaptive hard disk interface in view of the above-mentioned defects in the prior art.
发明内容Contents of the invention
本发明的目的在于,针对上述旧的硬盘背板无法满足实际需求的缺陷,提供一种支持自适应硬盘接口的硬盘背板,以解决上述技术问题。The object of the present invention is to provide a hard disk backplane supporting an adaptive hard disk interface to solve the above technical problems, aiming at the defect that the above-mentioned old hard disk backplane cannot meet actual needs.
为实现上述目的,本发明给出以下技术方案:To achieve the above object, the present invention provides the following technical solutions:
一种支持自适应硬盘接口的硬盘背板,包括硬盘接口,硬盘接口连接有SATA接口、PCIE接口、CPLD、缓冲模块、I2C总线扩展受控模块以及硬盘状态I2C协议转换模块;A hard disk backplane supporting an adaptive hard disk interface, including a hard disk interface, the hard disk interface is connected with a SATA interface, a PCIE interface, a CPLD, a buffer module, an I2C bus extension controlled module, and a hard disk state I2C protocol conversion module;
I2C总线扩展受控模块还连接有第一I2C总线,第一I2C总线还连接有第一I2C接口和温度传感器,第一I2C总线还与硬盘状态I2C协议转换模块和CPLD连接;The I2C bus extension controlled module is also connected with a first I2C bus, the first I2C bus is also connected with a first I2C interface and a temperature sensor, and the first I2C bus is also connected with the hard disk state I2C protocol conversion module and CPLD;
缓冲模块还与CPLD和PCIE接口连接;The buffer module is also connected with CPLD and PCIE interface;
I2C总线扩展受控模块还与CPLD连接;I2C bus extension controlled module is also connected with CPLD;
CPLD还连接有第二I2C接口、SGPIO接口、硬盘错误指示灯、硬盘在位指示灯以及硬盘活动指示灯;CPLD is also connected with the second I2C interface, SGPIO interface, hard disk error indicator light, hard disk presence indicator light and hard disk activity indicator light;
SATA接口还连接有南桥芯片PCH,PCIE接口还连接有CPU,第一I2C接口还连接有BMC,第二I2C接口也与CPU连接。The SATA interface is also connected to the south bridge chip PCH, the PCIE interface is also connected to the CPU, the first I2C interface is also connected to the BMC, and the second I2C interface is also connected to the CPU.
进一步地,I2C总线扩展受控模块包括I2C总线扩展单元和I2C总线受控单元;I2C总线扩展单元连接第一 I2C总线,I2C总线受控单元连接I2C总线扩展单元、硬盘接口和CPLD。Further, the I2C bus expansion controlled module includes an I2C bus expansion unit and an I2C bus controlled unit; the I2C bus expansion unit is connected to the first I2C bus, and the I2C bus controlled unit is connected to the I2C bus expansion unit, the hard disk interface and the CPLD.
进一步地,硬盘接口包括硬盘在位信息端口和硬盘错误信息端口,硬盘在位信息端口和硬盘错误信息端口均与CPLD连接。硬盘接口支持硬盘热插拔功能。Further, the hard disk interface includes a hard disk presence information port and a hard disk error information port, both of which are connected to the CPLD. The hard disk interface supports hard disk hot swap function.
进一步地,还包括外部电源接口,外部电源接口连接有电源转换模块,CPLD连接电源转换模块。CPLD也可连接硬盘电源供电,外部电源接口可接5V或12V,电源转换模块的输出电压为3.3V。Further, it also includes an external power interface, the external power interface is connected to a power conversion module, and the CPLD is connected to the power conversion module. The CPLD can also be connected to the hard disk power supply for power supply, the external power supply interface can be connected to 5V or 12V, and the output voltage of the power conversion module is 3.3V.
进一步地,硬盘接口的数量为4个,SATA接口的数量为4个,PCIE接口的数量为4个,缓冲模块的数量为4个,硬盘错误指示灯的数量为4个,硬盘定位指示灯的数量为4个,硬盘活动指示灯的数量为4个。Further, the number of hard disk interfaces is 4, the number of SATA interfaces is 4, the number of PCIE interfaces is 4, the number of buffer modules is 4, the number of hard disk error indicators is 4, and the number of hard disk positioning indicators is 4. The number is 4, and the number of hard disk activity indicators is 4.
进一步地,硬盘背板包括第一侧、第二侧、第三侧、第四侧、正面以及背面;Further, the hard disk backplane includes a first side, a second side, a third side, a fourth side, a front side and a back side;
四个硬盘接口均匀设置在硬盘背板正面的第四侧并与第四侧平行;The four hard disk interfaces are evenly arranged on the fourth side of the front of the hard disk backplane and parallel to the fourth side;
第一PCIE接口设置在硬盘背板背面靠近第一侧和第二侧的位置并与第二侧平行,第一SATA接口设置在硬盘背板背面靠近第一PCIE接口和第二侧的位置并与第二侧平行;The first PCIE interface is arranged on the back of the hard disk backplane near the first side and the second side and parallel to the second side, and the first SATA interface is arranged on the back of the hard disk backplane near the first PCIE interface and the second side and is parallel to the second side. the second side is parallel;
第三SATA接口设置在硬盘背板背面的中心位置,并与第二侧平行;The third SATA interface is set at the center of the back of the hard disk backplane and is parallel to the second side;
第三PCIE接口设置在硬盘背板背面从第三侧方向靠近第三SATA接口的位置,并与第二侧垂直;The third PCIE interface is set on the back of the hard disk backplane, close to the third SATA interface from the third side, and perpendicular to the second side;
第二PCIE接口设置在硬盘背板背面从第一侧方向靠近第三SATA接口的位置,并与第二侧垂直;The second PCIE interface is set on the back of the hard disk backplane, close to the third SATA interface from the first side, and perpendicular to the second side;
第二SATA接口设置在第一SATA接口和第三SATA接口中间的位置,并与第二侧垂直;The second SATA interface is arranged in the middle of the first SATA interface and the third SATA interface, and is perpendicular to the second side;
第四SATA接口设置在硬盘背板背面靠近第三侧和第二侧的位置并与第二侧平行,第四PCIE接口设置在靠近第四SATA接口和第二侧的位置并与第二侧垂直。The fourth SATA interface is set on the back of the hard disk backplane close to the third side and the second side and parallel to the second side, and the fourth PCIE interface is set close to the fourth SATA interface and the second side and perpendicular to the second side .
进一步地,硬盘接口采用SFF-8639型号的硬盘连接器,PCIE接口采用支持PCIEX4信号的光纤铜缆连接器OCUlink。Further, the hard disk interface adopts a SFF-8639 type hard disk connector, and the PCIE interface adopts an optical fiber copper cable connector OCUlink that supports PCIEX4 signals.
进一步地,CPLD采用LCMXO2-1200型号的CPLD芯片,硬盘状态I2C协议转换模块采用TCA6408型号的芯片。Further, the CPLD adopts the CPLD chip of the LCMXO2-1200 model, and the I2C protocol conversion module of the hard disk state adopts the chip of the TCA6408 model.
进一步地,I2C总线扩展单元采用PCA9546型号的I2C总线扩展芯片;I2C总线受控单元采用74LV3162型号的芯片。Further, the I2C bus expansion unit adopts the PCA9546 type I2C bus expansion chip; the I2C bus controlled unit adopts the 74LV3162 type chip.
进一步地,硬盘状态I2C协议转换模块和CPLD用于判断硬盘接口是否有硬盘插入及插入的硬盘类型;Further, the hard disk state I2C protocol conversion module and CPLD are used to judge whether the hard disk interface has a hard disk inserted and the inserted hard disk type;
当判断有硬盘插入且插入的硬盘类型为NVME硬盘时,When it is determined that a hard disk is inserted and the type of the inserted hard disk is an NVME hard disk,
硬盘状态I2C协议转换模块通知BMC硬盘的类型为NVME硬盘,BMC通知CPU与PCIE接口连接,CPU通过第二I2C接口与CPLD通信控制NVME硬盘的活动指示灯;The hard disk status I2C protocol conversion module notifies the BMC that the type of the hard disk is an NVME hard disk, and the BMC notifies the CPU to connect to the PCIE interface, and the CPU communicates with the CPLD through the second I2C interface to control the activity indicator of the NVME hard disk;
CPLD控制I2C总线扩展受控模块打开,BMC与硬盘接口的I2C通信开启;The CPLD controls the I2C bus expansion controlled module to open, and the I2C communication between the BMC and the hard disk interface is opened;
CPLD控制缓冲模块打开,PCIE接口与硬盘接口的通信开启;The CPLD controls the buffer module to open, and the communication between the PCIE interface and the hard disk interface is opened;
CPLD控制NVME硬盘的错误指示灯和NVME硬盘的在位指示灯;The CPLD controls the error indicator light of the NVME hard disk and the presence indicator light of the NVME hard disk;
当判断有硬盘插入且插入的硬盘类型为SAS或SATA硬盘时,When it is determined that a hard disk is inserted and the type of the inserted hard disk is a SAS or SATA hard disk,
硬盘状态I2C协议转换模块通知BMC硬盘的类型为SAS或SATA硬盘,BMC通知PCH与SATA接口连接,PCH通过SGPIO接口与CPLD通信控制SAS或SATA硬盘的活动指示灯;Hard disk status I2C protocol conversion module informs BMC that the type of hard disk is SAS or SATA hard disk, BMC informs PCH to connect with SATA interface, and PCH communicates with CPLD through SGPIO interface to control the activity indicator light of SAS or SATA hard disk;
CPLD控制SAS或SATA硬盘的错误指示灯以及SAS或SATAE硬盘的在位指示灯。The CPLD controls the error indicator of the SAS or SATA hard disk and the presence indicator of the SAS or SATAE hard disk.
本发明的有益效果在于:The beneficial effects of the present invention are:
本发明可以满足系统对NVME、SAS和SATA不同类型硬盘的需求,实现服务器对硬盘的点灯需求,支持硬盘的错误指示灯、在位指示灯和活动指示灯。The invention can meet the requirements of the system for different types of NVME, SAS and SATA hard disks, realize the server's lighting requirements for the hard disk, and support the error indicator light, presence indicator light and activity indicator light of the hard disk.
此外,本发明设计原理可靠,结构简单,具有非常广泛的应用前景。In addition, the design principle of the present invention is reliable, the structure is simple, and has very wide application prospects.
由此可见,本发明与现有技术相比,具有突出的实质性特点和显著的进步,其实施的有益效果也是显而易见的。It can be seen that, compared with the prior art, the present invention has outstanding substantive features and remarkable progress, and the beneficial effects of its implementation are also obvious.
附图说明Description of drawings
图1为本发明连接示意图;Fig. 1 is the connection schematic diagram of the present invention;
图2为本发明实施例连接示意图;Fig. 2 is the connection schematic diagram of the embodiment of the present invention;
图3为本发明正面结构示意图一;Fig. 3 is a schematic view of the front structure of the present invention;
图4为本发明背面结构示意图二;Fig. 4 is a schematic diagram of the back structure of the present invention II;
其中,1-硬盘接口;1.1-第一硬盘接口;1.2-第二硬盘接口;1.3-第三硬盘接口;1.4-第四硬盘接口;2-SATA接口;2.1-第一SATA接口;2.2-第二SATA接口;2.3-第三SATA接口;2.4-第四SATA接口;3-PCIE接口;3.1-第一PCIE接口;3.2-第二PCIE接口;3.3-第三PCIE接口;3.4-第四PCIE接口;4-CPLD;5-缓冲模块;5.1-第一缓冲模块;5.2-第二缓冲模块;5.3-第三缓冲模块;5.4-第四缓冲模块;6-I2C扩展受控模块;6.1-I2C总线扩展单元;6.2.1-第一I2C总线受控单元;6.2.2-第二I2C总线受控单元;7-硬盘状态I2C协议转换模块;8-第一I2C接口;9-温度传感器;10-第二I2C接口;11-SGPIO接口;12-硬盘错误指示灯;13-硬盘在位指示灯;14-硬盘活动指示灯;15-PCH;16-CPU;17-BMC; A.1-硬盘背板第一侧;A.2-硬盘背板第二侧;A.3-硬盘背板第三侧;A.4-硬盘背板第四侧。Among them, 1-hard disk interface; 1.1-first hard disk interface; 1.2-second hard disk interface; 1.3-third hard disk interface; 1.4-fourth hard disk interface; 2-SATA interface; 2.1-first SATA interface; 2.2-the first 2.3-third SATA interface; 2.4-fourth SATA interface; 3-PCIE interface; 3.1-first PCIE interface; 3.2-second PCIE interface; 3.3-third PCIE interface; 3.4-fourth PCIE interface ;4-CPLD; 5-buffer module; 5.1-first buffer module; 5.2-second buffer module; 5.3-third buffer module; 5.4-fourth buffer module; 6-I2C extended controlled module; 6.1-I2C bus Expansion unit; 6.2.1-first I2C bus controlled unit; 6.2.2-second I2C bus controlled unit; 7-hard disk status I2C protocol conversion module; 8-first I2C interface; 9-temperature sensor; 10- The second I2C interface; 11-SGPIO interface; 12-hard disk error indicator; 13-hard disk presence indicator; 14-hard disk activity indicator; 15-PCH; 16-CPU; 17-BMC; A.1-hard disk back The first side of the board; A.2- the second side of the hard disk backplane; A.3- the third side of the hard disk backplane; A.4- the fourth side of the hard disk backplane.
具体实施方式:detailed description:
为使得本发明的目的、特征、优点能够更加的明显和易懂,下面将结合本具体实施例中的附图,对本发明中的技术方案进行清楚、完整地描述。In order to make the purpose, features, and advantages of the present invention more obvious and understandable, the technical solutions in the present invention will be clearly and completely described below in conjunction with the drawings in this specific embodiment.
如图1所示,本发明提供一种支持自适应硬盘接口的硬盘背板,包括硬盘接口1,硬盘接口连接有SATA接口2、PCIE接口3、CPLD 4、缓冲模块5、I2C总线扩展受控模块6以及硬盘状态I2C协议转换模块7;As shown in Fig. 1, the present invention provides a kind of hard disk backboard that supports adaptive hard disk interface, comprises hard disk interface 1, and hard disk interface is connected with SATA interface 2, PCIE interface 3, CPLD 4, buffer module 5, I2C bus expansion controlled Module 6 and hard disk state I2C protocol conversion module 7;
I2C总线扩展受控模块还连接有第一I2C总线,第一I2C总线还连接有第一I2C接口8和温度传感器9,第一I2C总线还与硬盘状态I2C协议转换模块7和CPLD 4连接;The I2C bus extension controlled module is also connected with the first I2C bus, the first I2C bus is also connected with the first I2C interface 8 and the temperature sensor 9, and the first I2C bus is also connected with the hard disk state I2C protocol conversion module 7 and CPLD 4;
缓冲模块5还与CPLD 4和PCIE接口3连接;Buffer module 5 is also connected with CPLD 4 and PCIE interface 3;
I2C总线扩展受控模块6还与CPLD 4连接;I2C bus extension controlled module 6 is also connected with CPLD 4;
CPLD 4还连接有第二I2C接口10、SGPIO接口11、硬盘错误指示灯12、硬盘在位指示灯13以及硬盘活动指示灯14;The CPLD 4 is also connected with a second I2C interface 10, an SGPIO interface 11, a hard disk error indicator 12, a hard disk presence indicator 13 and a hard disk activity indicator 14;
SATA接口2还连接有南桥芯片PCH 15,PCIE接口3还连接有CPU 16,第一I2C接口9还连接有BMC 17,第二I2C接口10也与CPU 16连接。The SATA interface 2 is also connected to the south bridge chip PCH 15 , the PCIE interface 3 is also connected to the CPU 16 , the first I2C interface 9 is also connected to the BMC 17 , and the second I2C interface 10 is also connected to the CPU 16 .
如图2所示,上述实施例中的硬盘接口1的数量为4个,第一硬盘接口1.1,第二硬盘接口1.2,第三硬盘接口1.3以及第四硬盘接口1.4,SATA接口2的数量为4个,第一SATA接口2.1,第二SATA接口2.2,第三SATA接口2.3以及第四SATA接口2.4,PCIE接口3的数量为4个,第一PCIE接口3.1,第二PCIE接口3.2,第三PCIE接口3.3以及第四PCIE接口3.4,缓冲模块4的数量为4个,第一缓冲模块4.1,第二缓冲模块4.2,第三缓冲模块4.3以及第四缓冲模块4.4;I2C总线扩展受控模块6包括I2C总线扩展单元6.1,第一I2C总线受控单元6.2.1和第二I2C总线受控单元6.2.2;As shown in Figure 2, the quantity of hard disk interface 1 in the above-mentioned embodiment is 4, the first hard disk interface 1.1, the second hard disk interface 1.2, the 3rd hard disk interface 1.3 and the 4th hard disk interface 1.4, the quantity of SATA interface 2 is 4, the first SATA interface 2.1, the second SATA interface 2.2, the third SATA interface 2.3 and the fourth SATA interface 2.4, the number of PCIE interfaces 3 is 4, the first PCIE interface 3.1, the second PCIE interface 3.2, the third PCIE interface 3.3 and the fourth PCIE interface 3.4, the number of buffer modules 4 is 4, the first buffer module 4.1, the second buffer module 4.2, the third buffer module 4.3 and the fourth buffer module 4.4; I2C bus extension controlled module 6 Including an I2C bus expansion unit 6.1, a first I2C bus controlled unit 6.2.1 and a second I2C bus controlled unit 6.2.2;
第一硬盘接口1.1与第一SATA接口2.1、第一PCIE接口3.1、第一缓冲模块5.1、第一I2C总线受控单元6.2.1、CPLD 4、以及硬盘状态I2C协议转换模块7连接,The first hard disk interface 1.1 is connected with the first SATA interface 2.1, the first PCIE interface 3.1, the first buffer module 5.1, the first I2C bus controlled unit 6.2.1, CPLD 4, and the hard disk state I2C protocol conversion module 7,
第一缓冲模块5.1还与CPLD 4和第一PCIE接口3.1连接;The first buffer module 5.1 is also connected with the CPLD 4 and the first PCIE interface 3.1;
第二硬盘接口1.2与第二SATA接口2.2、第二PCIE接口3.2、第二缓冲模块5.2、第一I2C总线受控单元6.2.1、CPLD 4、以及硬盘状态I2C协议转换模块7连接,The second hard disk interface 1.2 is connected with the second SATA interface 2.2, the second PCIE interface 3.2, the second buffer module 5.2, the first I2C bus controlled unit 6.2.1, CPLD 4, and the hard disk state I2C protocol conversion module 7,
第二缓冲模块5.2还与CPLD 4和第二PCIE接口3.2连接;The second buffer module 5.2 is also connected with the CPLD 4 and the second PCIE interface 3.2;
第三硬盘接口1.3与第三SATA接口2.3、第三PCIE接口3.3、第三缓冲模块5.3、第二I2C总线受控单元6.2.2、CPLD 4、以及硬盘状态I2C协议转换模块7连接,The third hard disk interface 1.3 is connected with the third SATA interface 2.3, the third PCIE interface 3.3, the third buffer module 5.3, the second I2C bus controlled unit 6.2.2, CPLD 4, and the hard disk state I2C protocol conversion module 7,
第三缓冲模块5.3还与CPLD 4和第三PCIE接口3.3连接;The third buffer module 5.3 is also connected with the CPLD 4 and the third PCIE interface 3.3;
第四硬盘接口1.4与第四SATA接口2.4、第四PCIE接口3.4、第四缓冲模块5.4、第二I2C总线受控单元6.2.2、CPLD 4、以及硬盘状态I2C协议转换模块7连接,The fourth hard disk interface 1.4 is connected with the fourth SATA interface 2.4, the fourth PCIE interface 3.4, the fourth buffer module 5.4, the second I2C bus controlled unit 6.2.2, CPLD 4, and the hard disk state I2C protocol conversion module 7,
第四缓冲模块5.4还与CPLD 4和第四PCIE接口3.4连接;The fourth buffer module 5.4 is also connected with the CPLD 4 and the fourth PCIE interface 3.4;
第一I2C总线受控单元6.2.1连接I2C总线扩展单元6.1和CPLD 4,第二I2C总线受控单元6.2.2连接I2C总线扩展单元6.1和CPLD 4,I2C总线扩展单元6.1连接第一 I2C总线;The first I2C bus controlled unit 6.2.1 is connected to the I2C bus expansion unit 6.1 and the CPLD 4, the second I2C bus controlled unit 6.2.2 is connected to the I2C bus expansion unit 6.1 and the CPLD 4, and the I2C bus expansion unit 6.1 is connected to the first I2C bus ;
硬盘错误指示灯的数量也为4个,硬盘定位指示灯的数量为4个,硬盘活动指示灯的数量为4个,每个硬盘错误指示灯、每个硬盘定位指示灯以及每个硬盘活动指示灯指示对应的硬盘的状态;The number of hard disk error indicators is also 4, the number of hard disk location indicators is 4, the number of hard disk activity indicators is 4, each hard disk error indicator, each hard disk location indicator, and each hard disk activity indicator The light indicates the status of the corresponding hard disk;
硬盘接口包括硬盘在位信息端口和硬盘错误信息端口,硬盘在位信息端口和硬盘错误信息端口均与CPLD连接;The hard disk interface includes a hard disk presence information port and a hard disk error information port, both of which are connected to the CPLD;
背板还包括外部电源接口,外部电源接口连接有电源转换模块,CPLD连接电源转换模块。CPLD也可连接硬盘电源供电,外部电源接口可接5V或12V,电源转换模块的输出电压为3.3V;The backplane also includes an external power interface, the external power interface is connected to a power conversion module, and the CPLD is connected to the power conversion module. The CPLD can also be connected to the hard disk power supply, the external power supply interface can be connected to 5V or 12V, and the output voltage of the power conversion module is 3.3V;
如图3和图4所示,硬盘背板包括第一侧A.1、第二侧A.2、第三侧A.3、第四侧A.4、正面以及背面;As shown in Figure 3 and Figure 4, the hard disk backplane includes a first side A.1, a second side A.2, a third side A.3, a fourth side A.4, a front side and a back side;
四个硬盘接口,第一硬盘接口1.1、第二硬盘接口1.2、第三硬盘接口1.3和第四硬盘接口1.4均匀设置在硬盘背板正面的第四侧A.4并与第四侧A.4平行;Four hard disk interfaces, the first hard disk interface 1.1, the second hard disk interface 1.2, the third hard disk interface 1.3 and the fourth hard disk interface 1.4 are evenly arranged on the fourth side A.4 of the front of the hard disk backplane and connected to the fourth side A.4 parallel;
第一PCIE接口3.1设置在硬盘背板背面靠近第一侧A.1和第二侧A.2的位置并与第二侧A.2平行,第一SATA接口2.1设置在硬盘背板背面靠近第一PCIE接口3.1和第二侧A.2的位置并与第二侧A.2平行;The first PCIE interface 3.1 is arranged on the back of the hard disk backplane near the first side A.1 and the second side A.2 and parallel to the second side A.2, and the first SATA interface 2.1 is arranged on the back of the hard disk backplane near the second side A.2. The position of a PCIE interface 3.1 and the second side A.2 is parallel to the second side A.2;
第三SATA接口2.3设置在硬盘背板背面的中心位置,并与第二侧A.2平行;The third SATA interface 2.3 is arranged at the center position on the back of the hard disk backplane, and is parallel to the second side A.2;
第三PCIE接口3.3设置在硬盘背板背面从第三侧A.3方向靠近第三SATA接口2.3的位置,并与第二侧A.2垂直;The third PCIE interface 3.3 is arranged on the back of the hard disk backplane at a position close to the third SATA interface 2.3 from the direction of the third side A.3, and is perpendicular to the second side A.2;
第二PCIE接口3.2设置在硬盘背板背面从第一侧A.1方向靠近第三SATA接口2.3的位置,并与第二侧A.2垂直;The second PCIE interface 3.2 is arranged on the back of the hard disk backplane at a position close to the third SATA interface 2.3 from the direction of the first side A.1, and is perpendicular to the second side A.2;
第二SATA接口2.2设置在第一SATA接口2.1和第三SATA接口2.3中间的位置,并与第二侧A.2垂直;The second SATA interface 2.2 is arranged in the middle of the first SATA interface 2.1 and the third SATA interface 2.3, and is perpendicular to the second side A.2;
第四SATA接口2.4设置在硬盘背板背面靠近第三侧A.3和第二侧A.2的位置并与第二侧A.2平行,第四PCIE接口3.4设置在靠近第四SATA接口2.4和第二侧A.2的位置并与第二侧A.2垂直;The fourth SATA interface 2.4 is arranged on the back of the hard disk backplane close to the third side A.3 and the second side A.2 and parallel to the second side A.2, and the fourth PCIE interface 3.4 is arranged near the fourth SATA interface 2.4 and the position of the second side A.2 and perpendicular to the second side A.2;
第一硬盘接口1.1、第二硬盘接口1.2、第三硬盘接口1.3、第四硬盘接口1.4均采用SFF-8639型号的硬盘连接器,第一PCIE接口3.1、第二PCIE接口3.2、第三PCIE接口3.3、第四PCIE接口3.4采用支持PCIEX4信号的光纤铜缆连接器OCUlink;The first hard disk interface 1.1, the second hard disk interface 1.2, the third hard disk interface 1.3, and the fourth hard disk interface 1.4 all use SFF-8639 hard disk connectors, the first PCIE interface 3.1, the second PCIE interface 3.2, and the third PCIE interface 3.3. The fourth PCIE interface 3.4 adopts the optical fiber copper cable connector OCUlink that supports PCIEX4 signals;
CPLD采用LCMXO2-1200型号的CPLD芯片,硬盘状态I2C协议转换模块采用TCA6408型号的芯片;CPLD adopts LCMXO2-1200 type CPLD chip, hard disk state I2C protocol conversion module adopts TCA6408 type chip;
I2C总线扩展单元采用PCA9546型号的I2C总线扩展芯片;第一I2C总线受控单元和第二I2C总线受控单元采用74LV3162型号的芯片。The I2C bus expansion unit adopts the PCA9546 I2C bus expansion chip; the first I2C bus controlled unit and the second I2C bus controlled unit adopt the 74LV3162 chip.
硬盘状态I2C协议转换模块和CPLD用于判断硬盘接口是否有硬盘插入及插入的硬盘类型;The hard disk status I2C protocol conversion module and CPLD are used to judge whether there is a hard disk inserted in the hard disk interface and the type of the inserted hard disk;
当判断有硬盘插入且插入的硬盘类型为NVME硬盘时,When it is determined that a hard disk is inserted and the type of the inserted hard disk is an NVME hard disk,
硬盘状态I2C协议转换模块通知BMC硬盘的类型为NVME硬盘,BMC通知CPU与PCIE接口连接,CPU通过第二I2C接口与CPLD通信控制NVME硬盘的活动指示灯;The hard disk status I2C protocol conversion module notifies the BMC that the type of the hard disk is an NVME hard disk, and the BMC notifies the CPU to connect to the PCIE interface, and the CPU communicates with the CPLD through the second I2C interface to control the activity indicator of the NVME hard disk;
CPLD控制I2C总线扩展受控模块打开,BMC与硬盘接口的I2C通信开启;The CPLD controls the I2C bus expansion controlled module to open, and the I2C communication between the BMC and the hard disk interface is opened;
CPLD控制缓冲模块打开,PCIE接口与硬盘接口的通信开启;The CPLD controls the buffer module to open, and the communication between the PCIE interface and the hard disk interface is opened;
CPLD控制NVME硬盘的错误指示灯和NVME硬盘的在位指示灯;The CPLD controls the error indicator light of the NVME hard disk and the presence indicator light of the NVME hard disk;
当判断有硬盘插入且插入的硬盘类型为SAS或SATA硬盘时,When it is determined that a hard disk is inserted and the type of the inserted hard disk is a SAS or SATA hard disk,
硬盘状态I2C协议转换模块通知BMC硬盘的类型为SAS或SATA硬盘,BMC通知PCH与SATA接口连接,PCH通过SGPIO接口与CPLD通信控制SAS或SATA硬盘的活动指示灯;Hard disk status I2C protocol conversion module informs BMC that the type of hard disk is SAS or SATA hard disk, BMC informs PCH to connect with SATA interface, and PCH communicates with CPLD through SGPIO interface to control the activity indicator light of SAS or SATA hard disk;
CPLD控制SAS或SATA硬盘的错误指示灯以及SAS或SATAE硬盘的在位指示灯。The CPLD controls the error indicator of the SAS or SATA hard disk and the presence indicator of the SAS or SATAE hard disk.
在2U服务器中,通过3个上述四硬盘接口的背板组合,满足12个硬盘需求,并可根据实际需求选择不同类型的硬盘。In a 2U server, the requirements for 12 hard disks can be met through the combination of three backplanes with four hard disk interfaces mentioned above, and different types of hard disks can be selected according to actual needs.
SATA接口,是Serial ATA的缩写,是一种电脑总线,主要功能是用作主板和大量存储设备(如硬盘及光盘驱动器)之间的数据传输之用。ATA,AT AttachmentAT,嵌入式接口,ATA也被称为IDE接口。SATA interface, the abbreviation of Serial ATA, is a computer bus whose main function is to transmit data between the motherboard and a large number of storage devices (such as hard disks and optical drives). ATA, AT AttachmentAT, embedded interface, ATA is also called IDE interface.
OCuLink,Optical Copper Link,光纤/铜缆链接。OCuLink, Optical Copper Link, Fiber/Copper Link.
CPLD,Complex Programmable Logic Device,复杂可编程逻辑器件。CPLD, Complex Programmable Logic Device, complex programmable logic device.
BMC,Baseboard Management Controller,基板管理控制器。BMC, Baseboard Management Controller, Baseboard Management Controller.
本发明的实施例是说明性的,而非限定性的,上述实施例只是帮助理解本发明,因此本发明不限于具体实施方式中所述的实施例,凡是由本领域技术人员根据本发明的技术方案得出的其他的具体实施方式,同样属于本发明保护的范围。The embodiments of the present invention are illustrative, rather than limiting, and the above-mentioned embodiments are only to help understand the present invention, so the present invention is not limited to the embodiments described in the specific implementation manner, and those skilled in the art according to the technology of the present invention Other specific implementation modes derived from the scheme also belong to the protection scope of the present invention.
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CN112559408B (en) * | 2020-12-03 | 2022-03-22 | 山东云海国创云计算装备产业创新中心有限公司 | A motherboard and its signal transfer system |
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CN112667066A (en) * | 2020-12-14 | 2021-04-16 | 苏州浪潮智能科技有限公司 | Method, system and medium for expanding hard disk storage capacity |
CN112860327A (en) * | 2021-02-09 | 2021-05-28 | 山东英信计算机技术有限公司 | CPU port switching method, device, equipment and readable medium |
CN113434443A (en) * | 2021-06-11 | 2021-09-24 | 苏州浪潮智能科技有限公司 | System and method for supporting automatic switching of PCIE (peripheral component interface express) clock |
CN119065730A (en) * | 2024-11-05 | 2024-12-03 | 长沙湘计海盾科技有限公司 | A self-adaptive storage system and method |
CN119065730B (en) * | 2024-11-05 | 2025-02-25 | 长沙湘计海盾科技有限公司 | A self-adaptive storage system and method |
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