CN205984998U - Enhancement mode gaAs mHEMT device - Google Patents
Enhancement mode gaAs mHEMT device Download PDFInfo
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- CN205984998U CN205984998U CN201621071695.3U CN201621071695U CN205984998U CN 205984998 U CN205984998 U CN 205984998U CN 201621071695 U CN201621071695 U CN 201621071695U CN 205984998 U CN205984998 U CN 205984998U
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Abstract
The utility model provides an enhancement mode gaAs mHEMT device, include by the lower supreme substrate that forms in proper order, a gaAs buffer layer, alGaAsGaAs multi -quantum well buffer layer, the 2nd gaAs buffer layer, the 3rd gaAs buffer layer, a inP buffer layer, the 2nd inP buffer layer, channel layer, space isolation layer, delta doping plane doped layer, barrier layer and cap layer. The utility model discloses conventional growth secondary epitaxy or concave bars groove structure have been saved to the damage of device to this application, and the effectual reliability of improving the enhancement device can normally be worked at extreme environment, and technology is comparatively simple, adopt periodic multi -quantum well structural formation buffer layer of growing, be used for adjusting the stress of buffer layer, avoid lattice relaxation, effectively alleviate the diffusion of substrate defect to the channel, this application substrate comprises silicon, and this structure is favorable to reducing the cost of this problem device by a wide margin to can with seamless the agreeing with of conventional si base CMOS device, realize changing on a large scale applied radio frequency and numerical integration.
Description
Technical field
This utility model is related to technical field of manufacturing semiconductors, more particularly to a kind of enhancement mode GaAs mHEMT device.
Background technology
Using GaAs E/D mHEMT form DCFL logic circuit due to having low-power consumption, single power supply it is easy to design
The advantages of, cause extensive concern in the world, be the basis manufacturing LSI and VLSI circuit.But, due to lacking p-channel
It is impossible to form the complementary logic of low-power consumption, enhancement mode HEMT can alleviate the problem lacking p-channel to device, realizes the electricity simplifying
Line structure, can expand application in low-power consumption digital circuit for this device significantly.
The threshold voltage (Vth) of existing enhancement mode HEMT device cannot realize reliable and stable on the occasion of and device creepage asks
Topic is relatively difficult to resolve certainly, thus leading to digital circuit to lose efficacy.
Utility model content
This utility model, mainly solving the technical problems that providing a kind of enhancement mode GaAs mHEMT device, is capable of
PIN photoelectric detector, trans-impedance amplifier and amplitude limiter are highly integrated.
For solving above-mentioned technical problem, the technical scheme that this utility model adopts is：A kind of enhancement mode GaAs is provided
MHEMT device, including the Si substrate sequentially forming from the bottom to top, a GaAs cushion, AlGaAs/GaAs MQW buffering
Layer, the 2nd GaAs cushion, the 3rd GaAs cushion, an InP cushion, the 2nd InP cushion, channel layer, spatial separation
Layer, Delta-doping planar sheet doping layers, barrier layer and cap layers, cap layers are formed with source electrode, grid and drain electrode, described grid position
Between source electrode and drain electrode.
It is different from the situation of prior art, the beneficial effects of the utility model are：
(1) the application eliminates the damage to device of routine growth secondary epitaxy or concave grid groove structure, effectively improves
The reliability of enhancement device, can normal work in extreme circumstances, and technique is relatively simple；
(2) multi-quantum pit structure adopting cyclical growth forms cushion, for being adjusted to the stress of cushion,
Avoid lattice relaxation, effectively alleviate the diffusion to raceway groove for the substrate defects；
(3) the application substrate is made up of silicon, and this structure is conducive to the cost of this problem device is greatly lowered, and can be with
Conventional Si based CMOS devices are seamless to be agreed with, and realizes the radio frequency of large-scale application and the integrated of numeral.
Brief description
Fig. 1 is the structural representation of this utility model embodiment enhancement mode GaAs mHEMT device.
Specific embodiment
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out
Clearly and completely description is it is clear that described embodiment is only a part of embodiment of the present utility model rather than whole
Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under the premise of making creative work
The every other embodiment being obtained, broadly falls into the scope of this utility model protection.
Refer to Fig. 1, be the structural representation of this utility model embodiment enhancement mode GaAs mHEMT device.This practicality is new
The enhancement mode GaAs mHEMT device of type embodiment includes：
Substrate 1, predominantly p-type Si substrate 1, including but not limited to Si, SiC, GaN, sapphire, Diamond, Main Function
For backing material；
First GaAs cushion 2, Si substrate 1 arrives the cushion between GaInAs raceway groove, mainly adopts GaAs, 650 DEG C high
Temperature growth, undopes, thickness 400～800nm, for absorbing between Si substrate 1 and subsequent epitaxial layer because lattice mismatch produces
Stress, it is to avoid produce lattice relaxation.
AlGaAs/GaAs MQW cushion 3, using the multi-quantum pit structure of cyclical growth, is mainly used to slow
The stress rushing layer is adjusted, it is to avoid lattice relaxation.
2nd GaAs cushion 4, Si substrate 1 arrives the cushion between GaInAs raceway groove, mainly adopts GaAs, 550 DEG C low
Temperature growth, undopes, thickness 100～300nm.
3rd GaAs cushion 5, Si substrate 1 arrives the cushion between GaInAs raceway groove, mainly adopts GaAs, 650 DEG C high
Temperature growth, undopes, thickness 100～300nm.
First InP cushion 6, Si substrate 1 arrives the cushion between GaInAs raceway groove, mainly adopts InP, 650 DEG C of low temperature
Growth, undopes, thickness 400～800nm.
2nd InP cushion 7, Si substrate 1 arrives the cushion between GaInAs raceway groove, mainly adopts InP, 750 DEG C of high temperature
Growth, undopes, thickness 400～800nm.
Channel layer 8, using molecular beam epitaxial method growth, thickness isChemical formula is Ga1-XInXAs, wherein
X is 0～0.54, for providing conducting channel for two-dimensional electron gas under low field.
Spatial separation layer 9, is grown on channel layer 8GaInAs using molecular beam epitaxial method, thickness be 30 toChange
Formula is Al1-XInXAs, wherein x are 0～0.54, for by donor impurity spur and 2DEG spatial separation, reducing ionization
Scattering process it is ensured that in raceway groove 2DEG high electron mobility.
Delta-doping planar sheet doping layers 10, are grown on spatial separation layer 9AlInAs using molecular beam epitaxial method,
Thickness be 5 toFor providing free electron；The dosage of doping Si is 2.5 × 1012cm-2To 5 × 1012cm-2.
Barrier layer 11, is grown on planar sheet doping layers 10 using molecular beam epitaxial method, thickness be 150 toChemistry
Formula is Al1-XInXAs, wherein x are 0～0.54, for forming Schottky contacts with grid metal, so that planar sheet doping layers 10 is produced
Free electron shifts into raceway groove.Generally for being relatively easy to form enhancement mode, using 15nm.
Highly doped cap 12, is grown on barrier layer 11AlInAs using molecular beam epitaxial method, thickness isChemical formula is Ga1-XInXAs, wherein x are 0～0.54, for providing good Ohmic contact for device preparation；
The dosage of body doping Si is 5 × 1018cm-3～2 × 1019cm-3.
Source electrode 15, grid 14 and drain electrode 13 are provided with cap layers 12, grid 14 is located between source electrode 15 and drain electrode 13.
The preparation method of this utility model enhancement mode GaAs mHEMT device comprises the following steps：
1st, evaporation AuGe/Ni/Au forms source-drain electrode metal, forms the source and drain electricity of Ohmic contact through conventional lift-off process
Pole, this layer is made in the cap layers 12 of active layer the top, in order to reduce contact resistivity, then be aided with annealing formed good ohmic connect
Touch；
2nd, the method adopting ion implanting forms area of isolation, carries out B injection isolation using BF3 gas, until second
GaAs cushion 4, forms an isolation area, to provide the active area close to planar structure being mutually isolated；
4th, mask is made using photoresist, expose gate window area, wet etching falls the spatial separation layer 9 in gate region.
5th, adopt PECVD device, realize F base ion implanting using CF4 gas, improve device threshold voltage.
6th, evaporation Pt/Au forms enhanced grid 14 metal through conventional lift-off process, realizes enhancing of good performance
Type device.
The foregoing is only embodiment of the present utility model, not thereby limit the scope of the claims of the present utility model, every
The equivalent structure made using this utility model description and accompanying drawing content or equivalent flow conversion, or be directly or indirectly used in
Other related technical fields, are all included in the same manner in scope of patent protection of the present utility model.
Claims (10)
1. a kind of enhancement mode GaAs mHEMT device is it is characterised in that include substrate, the GaAs sequentially forming from the bottom to top
Cushion, AlGaAs/GaAs MQW cushion, the 2nd GaAs cushion, the 3rd GaAs cushion, an InP cushion,
2nd InP cushion, channel layer, spatial separation layer, Delta-doping planar sheet doping layers, barrier layer and cap layers；Described cap layers
On be formed with source electrode, grid and drain electrode, described grid be located at source electrode and drain electrode between.
2. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that a described GaAs cushion
Thickness is 400～800nm.
3. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that described 2nd GaAs cushion
Thickness is 100～300nm.
4. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that described 3rd GaAs cushion
Thickness is 100～300nm.
5. enhancement mode GaAs mHEMT device according to claim 1 it is characterised in that a described InP cushion and
The thickness of the 2nd InP cushion is 400～800nm.
6. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that the thickness of described channel layer isChemical formula is Ga1-XInXAs, wherein x are 0～0.54.
7. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that the thickness of described spatial separation layer
ForChemical formula is Al1-XInXAs, wherein x are 0～0.54.
8. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that described Delta-doping plane
The thickness of doped layer is
9. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that the thickness of described barrier layer isChemical formula is Al1-XInXAs, wherein x are 0～0.54.
10. enhancement mode GaAs mHEMT device according to claim 1 is it is characterised in that the thickness of described cap layers isChemical formula is Ga1-XInXAs, wherein x are 0～0.54.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201621071695.3U CN205984998U (en) | 2016-09-22 | 2016-09-22 | Enhancement mode gaAs mHEMT device |
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| CN201621071695.3U CN205984998U (en) | 2016-09-22 | 2016-09-22 | Enhancement mode gaAs mHEMT device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109742140A (en) * | 2018-11-23 | 2019-05-10 | 厦门市三安集成电路有限公司 | High resistant gallium nitride base buffer layer and preparation method with unilateral gradual change multiple quantum wells |
| CN116314296A (en) * | 2023-03-07 | 2023-06-23 | 中国电子科技集团公司第四十八研究所 | GaAs device structure based on electron beam direct writing T-shaped gate, preparation method of GaAs device structure and GaAs device |
-
2016
- 2016-09-22 CN CN201621071695.3U patent/CN205984998U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109742140A (en) * | 2018-11-23 | 2019-05-10 | 厦门市三安集成电路有限公司 | High resistant gallium nitride base buffer layer and preparation method with unilateral gradual change multiple quantum wells |
| CN109742140B (en) * | 2018-11-23 | 2020-10-27 | 厦门市三安集成电路有限公司 | High-resistance gallium nitride-based buffer layer with single-side gradually-changed multi-quantum well and preparation method |
| CN116314296A (en) * | 2023-03-07 | 2023-06-23 | 中国电子科技集团公司第四十八研究所 | GaAs device structure based on electron beam direct writing T-shaped gate, preparation method of GaAs device structure and GaAs device |
| CN116314296B (en) * | 2023-03-07 | 2025-04-04 | 中国电子科技集团公司第四十八研究所 | GaAs device structure based on electron beam direct writing T-type gate and its preparation method and GaAs device |
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