CN205451778U - Two port RAM test equipment's processing plate structure - Google Patents

Abstract

The utility model belongs to the field of electronic control, in particular to a processing board structure of a dual-port RAM testing device, comprising a housing, a display screen, a main board connected to the display screen, a processing board, and a SCSI-68 interface connected to the processing board The main board is connected with the processing board through the PCI-E interface; the processing board includes a PCI-E bridge chip, FPGA, drive circuit, and power supply module; the PCI-E interface is connected with the FPGA through the PCI-E bridge chip; The FPGA is electrically connected to the drive circuit; the utility model adopts a 10-inch tablet computer structure by highly integrating all test equipment, which saves space and is easy to carry, and has enhanced environmental adaptability, and is suitable for climbing high and low for operations; in addition, The structure of the processing board adopts the RAM signal-FPGA-Gigabit Ethernet-PCIE architecture, which makes the reading and writing speed much higher, saves a lot of manpower, and improves the test efficiency.

Description

A processing board structure of dual-port RAM testing equipment

technical field

The utility model belongs to the field of electronic control, in particular to a processing board structure of a dual-port RAM testing device.

Background technique

In the existing practical engineering applications, the dual-port RAM test equipment is not a whole, and its test modules are relatively discrete, all of which are discrete equipment, and the equipment is large in size. However, most of the existing improved equipment is a portable industrial computer structure, which is smaller than a notebook computer. It is 2-3 times thicker and weighs more than 10kg. The human workload in the test process is large, especially in the environment of climbing high and low, with low efficiency and poor applicability. In particular, the existing dual-port RAM test equipment The processing board structure in the device uses a PCIE dedicated chip architecture, and its read and write speed is slow, which makes the test efficiency low and cannot meet the test requirements. Based on the many problems and defects above, it is necessary to improve and transform the related test system.

Contents of the invention

The purpose of this utility model is to overcome the above-mentioned shortcoming of prior art, provide a kind of processing board structure of dual-port RAM testing equipment.

In order to achieve the above object, the technical solution adopted by the utility model is: a processing board structure of a dual-port RAM testing device, including a housing, a display screen, a main board connected to the display screen, a processing board, and a processing board connected to the processing board. SCSI-68 interface; the main board and the processing board are connected through the PCI-E interface; the display screen, the main board, the PCI-E interface, the processing board, and the SCSI-68 interface are all arranged inside the housing; the processing board Including PCI-E bridge chip, FPGA, driver circuit, power module; Described PCI-E interface is connected with FPGA through PCI-E bridge chip; Described power module is connected with PCI-E bridge chip, FPGA, driver circuit respectively; Said FPGA is electrically connected with the SCSI-68 interface through the drive circuit.

In the processing board structure of the above-mentioned dual-port RAM testing equipment, the PCI-E bridge chip is RTL8111E.

In the processing board structure of the above-mentioned dual-port RAM testing equipment, the power supply module adopts a switching power supply module.

A processing board structure includes a PCI-E bridge chip, a drive circuit connected to the PCI-E bridge chip, and a power supply module; the power supply module is connected to the PCI-E bridge chip and the drive circuit respectively.

In the aforementioned processing board structure, the PCI-E bridge chip is CH368.

In the aforementioned processing board structure, the driver circuit adopts a dual power supply bus driver chip SN74LVC4245A.

Beneficial effects of the utility model: the utility model highly integrates all test equipment and adopts a 10-inch tablet computer structure, which saves space and is easy to carry, enhances environmental adaptability, and is suitable for climbing high and low for operations; in addition, the processing board The structure adopts RAM signal-FPGA-Gigabit Ethernet-PCIE architecture, which makes the reading and writing speed much higher, saves a lot of manpower, and improves the test efficiency.

Description of drawings

The utility model will be described in detail below through the accompanying drawings and in conjunction with the embodiments. The advantages and implementation methods of the utility model will be more obvious. restrictions in any sense.

Fig. 1 is the structural block diagram of the processing plate structure of a kind of dual-port RAM testing equipment of the present utility model;

Fig. 2 is the structural block diagram of the processing board in the utility model embodiment 2;

Fig. 3 is the structural block diagram of the processing board in the utility model embodiment 3;

Explanation of reference signs: 1. shell; 2. display screen; 3. main board; 4. PCI-E interface; 5. processing board; 6. SCSI-68 interface; 7. PCI-E bridge chip; 8. FPGA; 9. Drive circuit; 10. Power module.

detailed description

The following is a detailed description of the embodiments of the utility model: this embodiment is implemented on the premise of the technical solution of the utility model, and provides detailed implementation methods and specific operating procedures. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the utility model, and these all belong to the protection scope of the utility model.

Example 1:

As shown in Figure 1, a kind of dual-port RAM testing equipment comprises housing 1, display screen 2, the main board 3 that is connected with described display screen 2, processing board 5, the SCSI-68 interface 6 that is connected with processing board 5; The main board 3 and the processing board 5 are connected through the PCI-E interface 4;

Among them, the dual-port RAM data processing board 5 (hereinafter referred to as the processing board 5 ) mainly completes functions such as dual-port RAM read and write timing conversion, docking with the PCI bridge chip, interrupt temporary storage, and store-and-forward.

The SCSI-68 interface 6 is connected to the device under test through a SCSI cable. One end of the cable adopts a male head of SCSI-68 to facilitate docking with the test device;

Example 2:

On the basis of embodiment 1, as shown in Figure 2, described processing board 5 comprises PCI-E bridge chip 7, FPGA8, driving circuit 9, power supply module 10; Described PCI-E interface 4 passes PCI-E bridge chip 7 is connected with FPGA8; described power module 10 is connected with PCI-E bridge chip 7, FPGA8, drive circuit 9 respectively; Described FPGA8 is electrically connected with SCSI-68 interface 6 through drive circuit 9.

Among them, the PCI-E bridge chip 7 is RTL8111E, the read and write speed of this solution is high, and the software and hardware design is relatively complicated. RTL8111E converts PCI-E to Gigabit Ethernet interface, Gigabit Ethernet interface is converted to RGMII interface through 88E1111, and FPGA completes the conversion between RGMII and dual-port RAM;

There are four kinds of power requirements in the scheme in the embodiment 2 are respectively:

1) 5V power supply: provide power to the cable side of the driver chip, which is consistent with the level of IDT7024;

2) 3.3V power supply: used to supply power to FPGA part Bank;

3) 2.5V power supply: There are many modules that need 2.5V power supply, which are the PLL of FPGA, some banks of FPGA, and VDDO, VDDOX, VDDOH, and AVDD of 88E1111;

4) 1.2V power supply: the core voltage of FPGA and the digital power supply of 88E1111.

It is a better way to choose a switching power supply module. The reason is that the module has high maturity, good stability and high switching power supply efficiency, which is very suitable for battery-powered equipment.

How to realize power on, power on, power off and power off also needs to be considered in the scheme. In order to reduce the development workload, the power management of the main board is used in the scheme to manage the processing board. The 5V power supply on the motherboard will only be provided when it is turned on. Taking advantage of this feature, a small 5V relay is used in the solution to control the 12V (battery pack voltage) power supply of the processing board. When starting up, the 5V power supply on the main board starts to supply power, and the control relay turns on and starts to supply power to the processing board.

Example 3:

On the basis of embodiment 1, as shown in Figure 3, described processing board 5 comprises PCI-E bridge chip 7, drive circuit 9 that links to each other with PCI-E bridge chip 7, power supply module 10; Described power supply module 10 is respectively It is connected with the PCI-E bridge chip 7 and the driving circuit 9; the dual power bus driving chip SN74LVC4245A is adopted in the driving circuit 9.

Among them, the PCI-E bridge chip 7 is CH368. The reading and writing speed of this solution is a bit low, but due to the characteristics of CH368, the circuit design and development are relatively simple, and the risk is relatively low. CH368 is a general interface chip connected to PCI-Express bus, which supports I/O port mapping, memory mapping, extended ROM and interrupt. CH368 converts the high-speed PCIE bus into an easy-to-use 32-bit or 8-bit active parallel interface similar to the ISA bus, which is used to make low-cost computer boards based on the PCIE bus, and to convert boards based on the ISA bus or PCI bus The card is upgraded to the PCIE bus. Compared with other mainstream buses, PCIE bus has faster speed, better real-time performance and better controllability, so CH368 is suitable for high-speed real-time I/O control cards, communication interface cards, data acquisition cards, etc.

There are four kinds of power requirements in the scheme in the embodiment 3, which are respectively:

1) Digital 5V power supply: provide power to the cable side of the driver chip, which is consistent with the level of IDT7024;

2) Digital 3.3V power supply: provide power for CH368, EEPROM, and the chip side of the driver chip;

3) Digital 1.8V power supply: the core voltage power supply of CH368;

4) Analog 1.8V power supply: CH368PCI-E differential drive voltage.

Since the power consumption of 5V and 3.3V is small, it can be powered by the onboard LDO or an external power supply module. According to experience and experiments, it is a better way to choose a switching power supply module. The reason is that the module has high maturity, good stability and high switching power supply efficiency, which is very suitable for battery-powered equipment.

How to realize power on, power on, power off and power off also needs to be considered in the scheme. In order to reduce the development workload, the power management of the main board is used in the scheme to manage the processing board. The 5V power supply on the motherboard will only be provided when it is turned on. Taking advantage of this feature, a small 5V relay is used in the solution to control the 12V (battery pack voltage) power supply of the processing board. When starting up, the 5V power supply on the main board starts to supply power, and the control relay turns on and starts to supply power to the processing board.

The above is a preferred application example of the utility model, not a limitation of the utility model. All simple modifications and structural changes made according to the technical points of the utility model belong to the protection scope of the utility model.

Claims (6)

1. a process plate structure for dual port RAM test equipment, the mainboard (3) being connected with described display screen (2) including housing (1), display screen (2), processes plate (5) and processes the SCSI-68 interface (6) that plate (5) is connected；Described mainboard (3) is connected by PCI-E interface (4) with processing plate (5)；Described display screen (2), mainboard (3), PCI-E interface (4), process plate (5), SCSI-68 interface (6) may be contained within housing (1) inside；It is characterized in that:

Described process plate (5) includes PCI-E bridging chip (7), FPGA(8), drive circuit (9), power module (10)；Described PCI-E interface (4) passes through PCI-E bridging chip (7) and FPGA(8) it is connected；Described power module (10) respectively with PCI-E bridging chip (7), FPGA(8), drive circuit (9) is connected；Described FPGA(8) electrically connected with SCSI-68 interface (6) by drive circuit (9).

The process plate structure of a kind of dual port RAM the most according to claim 1 test equipment, it is characterised in that: described PCI-E bridging chip (7) is RTL8111E.

The process plate structure of a kind of dual port RAM the most according to claim 1 test equipment, it is characterised in that: described power module (10) uses switch power module.

4. one kind processes plate structure, it is characterised in that: include drive circuit (9), power module (10) that PCI-E bridging chip (7) is connected with PCI-E bridging chip (7)；Described power module (10) is connected with PCI-E bridging chip (7), drive circuit (9) respectively.

A kind of process plate structure the most according to claim 4, it is characterised in that: described PCI-E bridging chip (7) is CH368.

A kind of process plate structure the most according to claim 4, it is characterised in that: described drive circuit (9) uses dual power supply bus driver chip SN74LVC4245A.