CN205177840U - Two -way transient voltage suppresses device - Google Patents
Two -way transient voltage suppresses device Download PDFInfo
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- CN205177840U CN205177840U CN201521026605.4U CN201521026605U CN205177840U CN 205177840 U CN205177840 U CN 205177840U CN 201521026605 U CN201521026605 U CN 201521026605U CN 205177840 U CN205177840 U CN 205177840U
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- 230000001052 transient effect Effects 0.000 title abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 66
- 239000007924 injection Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 23
- 230000005516 deep trap Effects 0.000 claims description 8
- 238000013461 design Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 9
- 238000012423 maintenance Methods 0.000 description 14
- 238000003466 welding Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
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- 238000004458 analytical method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
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Abstract
The utility model discloses a but the two -way transient voltage suppresses device based on silicon planar technique, the high maintaining voltage of NPNPN type, the excessive pressure of high peak current two way clamp transient state, including P type substrate, be equipped with N moldeed depth trap on the P type substrate, be equipped with a P trap, a N trap, the 2nd P trap in the N moldeed depth trap, from left to right be equipped with a P+ injection domain, a N+ injection domain, the 2nd N trap, the 2nd N+ injection domain in the P trap in proper order, the 2nd N+ injection domain stretches over a P trap and a N trap, from left to right be equipped with the 3rd N+ injection domain, the 3rd N trap, fourth N+ injection domain, the 5th P+ injection domain in the 2nd P trap in proper order, the 3rd N+ injection domain stretches over the 2nd a P trap and a N trap, the positive pole is connected with a N+ injection domain in a P+ injection domain, fourth N+ injection domain and the 2nd P+ injection domain are connected to the negative pole. This device can be used to the signal level and restraines for - 5V -+5V chip fin's transient state excessive pressure.
Description
Technical field
The utility model relates to integrated circuit fields, be specifically related to a kind of based on silicon planner technology, the bidirectional triode thyristor structure packet routing device that can be used for-5V-+5V chip pin.
Background technology
In the electronics industry, electrostatic is the key factor affecting integrated circuit (IntegratedCircuit, IC) reliability.The accumulation of electrostatic and electric discharge are inevitable phenomenons in IC manufacturing, encapsulation, transport, assembling and use links.Handheld device, outdoor utility, under the adverse circumstances such as the external space, the destructiveness of electrostatic is especially serious.According to statistics, the chip failure that static discharge (Electro-StaticDischarge, ESD) causes has accounted for 38% of integrated circuit (IC) products inefficacy sum.Therefore, electrostatic defending has become the importance that IC reliability design need be considered.
Transient Voltage Suppressor (TransientVoltageSuppressor, TVS) is a kind of circuit board level electrostatic and surge protective device, and its conventional semiconductor structure is diode, and therefore, TVS is also often called transient supression diode, and the longitudinal technique of general employing realizes.When moment, high energy pulse was added in TVS device; it can become low resistance state from high-impedance state within the extremely short time; thus allow big current to pass through from it, and voltage clamping to specific reduced levels, available protecting electronic circuit board or electronic equipment are not subject to the infringement of electrostatic and surge.The testing standard weighing TVS device antistatic capacity is IEC61000-4-2 international standard, contains contact discharge test and atmospherical discharges test in this standard.The general electronic system had higher requirements to electrostatic defending, be 8kV to the requirement of TVS device contact discharge ability, the requirement of atmospherical discharges ability is 15kV.
Silicon-controlled device (SiliconControlledRectifier, SCR) be the conventional device structure of electrostatic defending in chip, it is compared with diode, triode, field-effect transistor, there is the advantage that unit are electrostatic leakage efficiency is high, conducting resistance is little, robustness good, protection level is high, therefore, silicon-controlled device can based semiconductor planar technique, reaches higher electrostatic defending grade with less area.But as shown in Figure 1 and Figure 2, diode belongs to conducting type opening feature device; and SCR is rapid hollow opening feature device; in more than 5V semiconductor technology, the ME for maintenance of SCR device generally lower than the operating voltage of protected circuit, can cause the breech lock of protected IC.So, to SCR structure is substituted diode as TVS device, the ME for maintenance improving SCR device be considered.
Bidirectional triode thyristor device (BidirectionalSCR, BSCR) be a kind of compact ESD protective device, it can in positive and negative both direction to voltage clamp, for the electrostatic defending of I/O (I/O) pin signal transmission above and below ground level signal.As shown in Figure 3, be the two-way SCR profile of one typical NPNPN type, its equivalent circuit diagram as shown in Figure 4.When anode adds positive electrostatic pulse, parasitic triode T2 and T3 in BSCR device forms electrostatic leakage path (forward); When anode adds negative electrostatic pulse, parasitic triode T1 and T2 in BSCR device forms electrostatic leakage path (oppositely), forward and reverse path symmetry.The conventional methods improving BSCR device ME for maintenance is the lateral dimension increasing N trap in device architecture shown in Fig. 3, but this method increased device can realize area.
Another problem that electrostatic protection device design needs are considered is the domain way of realization of device.Interdigitated domain is the conventional domain form of electrostatic protection device on sheet.But, interdigitated device usually causes ESD protective device premature failure because current drain is uneven, and device potential electrometer protective capacities fails to play completely, and then causes the leakage current in device unit are less than normal.
From above-mentioned analysis, when BSCR device is applied as TVS device, its ME for maintenance to be improved on the one hand, be the non-homogeneous problem of releasing that will solve device on the other hand, letting out Current maxima to being issued at certain area.
Summary of the invention
The problem that the utility model solves is to provide a kind of semiconductor device, this semiconductor device have high ME for maintenance, high unit are electrostatic leakage electric current and can be integrated on sheet advantage, not only can be used as discrete packet routing device for the electrostatic of circuit board level and transient overvoltage protection, also can be used as the electrostatic defending of electrostatic protection device for chip I/O of core Embedded.
For achieving the above object, the technical solution adopted in the utility model is: a kind of semiconductor device, comprises P type substrate, is provided with N-type deep trap in described P type substrate, be provided with a symmetrical P trap and the 2nd P trap in described N-type deep trap, between a P trap and the 2nd P trap, be provided with a N trap; From left to right be provided with a P+ injection region, a N+ injection region, the 2nd N trap, the 2nd N+ injection region in one P trap successively, the 2nd N+ injection region is across the intersection of a P trap and a N trap; From left to right be provided with the 3rd N+ injection region, the 3rd N trap, the 4th N+ injection region, the 5th P+ injection region in 2nd P trap successively, the 3rd N+ injection region is across the intersection of the 2nd P trap and a N trap; A described P+ injection region and a N+ injection region jointed anode, the 4th N+ injection region is connected negative electrode with the 2nd P+ injection region.
Preferably, flush with on the left of the 2nd N+ injection region on the left of described 2nd N trap.
Preferably, flush with on the right side of the 3rd N+ injection region on the right side of described 3rd N trap.
Preferably, the transverse width of the 2nd N trap and the 3rd N trap is 5V silicon planner technology minimum design rule.
Semiconductor device of the present utility model, when not increasing technique level, non-increased device area, improves the ME for maintenance of device; Realize domain angle from device and improve device unit are electrostatic leakage ability; Device uses silicon planner technology to make, can be integrated together with protected circuit.
Accompanying drawing explanation
Fig. 1 is typical electrostatic protective device IV conducting type curve;
Fig. 2 is the rapid hollow curve of typical electrostatic protective device IV;
Fig. 3 is existing NPNPN type bidirectional triode thyristor device profile map;
Fig. 4 is existing NPNPN type bidirectional triode thyristor device equivalent circuit diagram;
Fig. 5 is semiconductor device profile of the present utility model;
Fig. 6 is the square packet routing device domain schematic diagram using semiconductor device structure of the present utility model;
Fig. 7 is the ring press welding block square packet routing device domain schematic diagram using semiconductor device structure of the present utility model.
Embodiment
As shown in Figure 5, semiconductor device of the present utility model comprises five layers, and wherein bottom is P type substrate 100; The second layer is the N-type deep trap 200 be arranged in P type substrate 100; Third layer is the P trap 301 be formed on N-type deep trap 200, the 2nd P trap 302; 4th layer for being formed at the N trap 402 on N-type deep trap, being formed at the 2nd N trap 401 in P trap 301, being formed at the 3rd N trap 403 in P trap 302; Layer 5 is six heavily doped regions: in a P trap 301, from left to right be followed successively by a P+ injection region 501, a N+ injection region 502, the 2nd N+ injection region 503, wherein, 2nd N+ injection region 503 flushes with the 2nd N trap 401 left margin across a P trap 301 and N trap the 401, two N+ injection region 503 left margin; In 2nd P trap 302, from left to right be provided with the 3rd N+ injection region 504, the 4th N+ injection region 505, the 2nd P+ injection region 506 successively, wherein, the 3rd N+ injection region 504 flushes with the 3rd N trap 403 right margin across the 2nd P trap 302 and N-type trap the 401, three N+ injection region 504 right margin.
One P+ injection region 501 and a N+ injection region 502 are all as electrical anode, and the 4th N+ injection region 505 and the 2nd P+ injection region 506 are all as electrical cathode.
Semiconductor device of the present utility model is from electrical anode to electrical cathode, SCR path is a P trap 301 and P+ injection region the 501, the first/the second/three N trap 402/401/403 and the second/three N+ injection region 503/504, the 2nd P trap 302 and the 2nd P+ injection region 506, the 4th N+ injection region 505, the PNPN SCR structure of formation.From electrical cathode to electrical anode, SCR path is the 2nd P trap 302 and the 2nd P+ injection region the 506, the first/the second/three N trap 402/401/403 and the second/three N+ injection region 503/504, a P trap 301 and a P+ injection region 501, a N+ injection region 502, the PNPN SCR structure of formation.
Semiconductor device of the present utility model does not change the basic functional principle of existing NPNPN type bidirectional triode thyristor device, the same Fig. 3 of equivalent circuit diagram.The parasitic triode of its inside is: form NPN transistor T1 by a N+ injection region 502, a P trap 301, a N trap 402; PNP transistor T2 is formed by a P trap 301, a N trap 402, the 2nd P trap 302; NPN transistor T3 is formed by a N trap 402, the 2nd P trap 302, the 4th N+ injection region 505.
When esd pulse is added in anode, the 3rd N+ injection region 504 and the 2nd P trap 302 reverse-biased, if pulse voltage is higher than the avalanche breakdown voltage of this knot, produce a large amount of avalanche current in device.Electric current is through the 2nd P trap 302 dead resistance R
p trap 2flow to negative electrode, when the voltage at these dead resistance two ends ties (the bc knot that the 2nd P trap 302 and the 4th N+ injection region form T3 transistor) forward conduction voltage higher than the bc of T3 transistor, T3 opens.The T3 opened provides base current for transistor T2, and subsequently, T2 opens and provides base current for T3.After this produce even without avalanche current, T2 and T3 constitutes positive feedback loop, and the SCR structure be made up of positive-negative-positive crystal T2 and NPN transistor T3 is switched on, static electricity discharge.In like manner, when there is esd pulse in negative electrode, or when negative esd pulse appears in anode, the 2nd N+ diffusion region 503 and P trap 301 avalanche breakdown, subsequently, the SCR structure conducting static electricity discharge be made up of PNP transistor T2 and NPN transistor T1.
As shown in Figure 3, hole current path during its forward static electricity discharge is P trap/N+-N trap-N+/P trap/N+ to structure before device improvements, and reverse path is symmetrical; It can improve the ME for maintenance of device by the width of increased device N trap, but also increase device simultaneously realize area.As shown in Figure 5, by increasing by the 2nd N trap 401, the 3rd N trap 403 reaches the object improving device ME for maintenance to semiconductor device of the present utility model.Hole current path during semiconductor device forward static electricity discharge of the present utility model is P trap/N trap 401-N+-N trap-N+-N trap 403/P trap/N+, and reverse path is symmetrical.From current drain path, N trap 401 and N trap 403, in the current path length longitudinally adding this device, can reach the object improving ME for maintenance.From equivalent circuit theory, when forward and reverse electrostatic leakage, N trap 401 and N trap 403 add the base width of parasitic triode T2 in the vertical, reduce the current amplification factor of T2 pipe, thus improve the ME for maintenance of device.Therefore, semiconductor device of the present utility model, under not increasing device and realizing the prerequisite of area, reaches the object improving ME for maintenance.
Be domain schematic diagram when semiconductor device of the present utility model realizes as shown in Figure 6, Figure 7, be namely Fig. 5 along the device profile map of A-A ' tangent line in figure, the label indication level in Fig. 6, Fig. 7 is consistent with label indication level in profile 5.Ring press welding block square domain is as shown in Figure 6 adopted during chip-scale application; Square domain is as shown in Figure 7 adopted during circuit board level application.Domain mainly comprises following technique level: P+ diffusion region; N+ diffusion region; P type trap zone territory; N-type trap region; N-type deep trap region; Metal level 1; Metal level 2; Contact hole; Through hole; Press welding block.
Domain shown in Fig. 6 possesses following feature: device is ring press welding block square structure, and anode press welding block 601 layout, in device middle, is convenient to electrostatic and is evenly released to four sides, improves device electrostatic defending grade; Device anode press welding block 601 layout, above square devices middle instead of other domain technique levels of device, avoids the device failure caused due to bond technology; When chip-scale is applied, can with chip common land press welding block GND, therefore, do not need to arrange separately negative electrode press welding block, only need by GND ground wire around device, and be connected to device cathodes, be more of value to electric current four sides even inflow or outflow.
Domain shown in Fig. 7 possesses following feature: device is square structure, and anode press welding block 601, negative electrode press welding block 602 layout are peripheral at other technique levels of element layout.Anode P+ diffusion region is the filled squares of larger area, is convenient to electrostatic and evenly releases to four sides, thus ensure the uniform conducting of device, effectively improves device electrostatic defending grade.
The square of the utility model design and ring press welding block square 5V high-performance semiconductor device, under not increasing device and realizing the prerequisite of area, have the characteristic of high maintenance voltage, high electrostatic leakage ability.Layout design of the present utility model and improve the design of device ME for maintenance by increasing darker technique level N trap, be applicable to other unidirectional device structures (NMOS, BJT, Diode) simultaneously, for the unit are electrostatic leakage efficiency and ME for maintenance improving device, there is generality.
Claims (4)
1. a semiconductor device, comprises P type substrate, it is characterized in that: be provided with N-type deep trap in described P type substrate, is provided with a symmetrical P trap and the 2nd P trap, is provided with a N trap between a P trap and the 2nd P trap in described N-type deep trap; From left to right be provided with a P+ injection region, a N+ injection region, the 2nd N trap, the 2nd N+ injection region in one P trap successively, the 2nd N+ injection region is across the intersection of a P trap and a N trap; From left to right be provided with the 3rd N+ injection region, the 3rd N trap, the 4th N+ injection region, the 5th P+ injection region in 2nd P trap successively, the 3rd N+ injection region is across the intersection of the 2nd P trap and a N trap; A described P+ injection region and a N+ injection region jointed anode, the 4th N+ injection region is connected negative electrode with the 2nd P+ injection region.
2. semiconductor device as claimed in claim 1, is characterized in that: flush with on the left of the 2nd N+ injection region on the left of described 2nd N trap.
3. semiconductor device as claimed in claim 1, is characterized in that: flush with on the right side of the 3rd N+ injection region on the right side of described 3rd N trap.
4. the semiconductor device as described in as arbitrary in claim 1-3, is characterized in that: the transverse width of the 2nd N trap and the 3rd N trap is 5V silicon planner technology minimum design rule.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521026605.4U CN205177840U (en) | 2015-12-10 | 2015-12-10 | Two -way transient voltage suppresses device |
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| CN201521026605.4U CN205177840U (en) | 2015-12-10 | 2015-12-10 | Two -way transient voltage suppresses device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374815A (en) * | 2015-12-10 | 2016-03-02 | 湖南静芯微电子技术有限公司 | Bidirectional transient voltage suppression device |
| CN108461491A (en) * | 2018-03-21 | 2018-08-28 | 湖南静芯微电子技术有限公司 | A kind of low triggering bidirectional thyristor electrostatic protection device of high maintenance voltage |
| CN108520875A (en) * | 2018-06-07 | 2018-09-11 | 湖南静芯微电子技术有限公司 | A High Sustain Voltage NPNPN Type Bidirectional Thyristor Electrostatic Protection Device |
-
2015
- 2015-12-10 CN CN201521026605.4U patent/CN205177840U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374815A (en) * | 2015-12-10 | 2016-03-02 | 湖南静芯微电子技术有限公司 | Bidirectional transient voltage suppression device |
| CN105374815B (en) * | 2015-12-10 | 2017-12-26 | 湖南静芯微电子技术有限公司 | A kind of semiconductor device |
| CN108461491A (en) * | 2018-03-21 | 2018-08-28 | 湖南静芯微电子技术有限公司 | A kind of low triggering bidirectional thyristor electrostatic protection device of high maintenance voltage |
| CN108461491B (en) * | 2018-03-21 | 2023-09-29 | 湖南静芯微电子技术有限公司 | Low-trigger bidirectional silicon controlled electrostatic protection device with high maintenance voltage |
| CN108520875A (en) * | 2018-06-07 | 2018-09-11 | 湖南静芯微电子技术有限公司 | A High Sustain Voltage NPNPN Type Bidirectional Thyristor Electrostatic Protection Device |
| CN108520875B (en) * | 2018-06-07 | 2023-08-22 | 湖南静芯微电子技术有限公司 | High-maintenance voltage NPNPN type bidirectional silicon controlled rectifier electrostatic protection device |
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Granted publication date: 20160420 Effective date of abandoning: 20171226 |